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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dc_features.h"
27
28#ifndef __DISPLAY_MODE_STRUCTS_H__
29#define __DISPLAY_MODE_STRUCTS_H__
30
31typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st;
32typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
33typedef struct _vcs_dpi_ip_params_st ip_params_st;
34typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st;
35typedef struct _vcs_dpi_display_output_params_st display_output_params_st;
36typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st;
37typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
38typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st;
39typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
40typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st;
41typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st;
42typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st;
43typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st;
44typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st;
45typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st;
46typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st;
47typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st;
48typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st;
49typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st;
50typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st;
51typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st;
52typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
53typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
54typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
55
56struct _vcs_dpi_voltage_scaling_st {
57 int state;
58 double dscclk_mhz;
59 double dcfclk_mhz;
60 double socclk_mhz;
61 double phyclk_d18_mhz;
62 double dram_speed_mts;
63 double fabricclk_mhz;
64 double dispclk_mhz;
65 double dram_bw_per_chan_gbps;
66 double phyclk_mhz;
67 double dppclk_mhz;
68 double dtbclk_mhz;
69};
70
71struct _vcs_dpi_soc_bounding_box_st {
72 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
73 unsigned int num_states;
74 double sr_exit_time_us;
75 double sr_enter_plus_exit_time_us;
76 double urgent_latency_us;
77 double urgent_latency_pixel_data_only_us;
78 double urgent_latency_pixel_mixed_with_vm_data_us;
79 double urgent_latency_vm_data_only_us;
80 double writeback_latency_us;
81 double ideal_dram_bw_after_urgent_percent;
82 double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
83 double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
84 double pct_ideal_dram_sdp_bw_after_urgent_vm_only;
85 double max_avg_sdp_bw_use_normal_percent;
86 double max_avg_dram_bw_use_normal_percent;
87 unsigned int max_request_size_bytes;
88 double downspread_percent;
89 double dram_page_open_time_ns;
90 double dram_rw_turnaround_time_ns;
91 double dram_return_buffer_per_channel_bytes;
92 double dram_channel_width_bytes;
93 double fabric_datapath_to_dcn_data_return_bytes;
94 double dcn_downspread_percent;
95 double dispclk_dppclk_vco_speed_mhz;
96 double dfs_vco_period_ps;
97 unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
98 unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
99 unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
100 unsigned int round_trip_ping_latency_dcfclk_cycles;
101 unsigned int urgent_out_of_order_return_per_channel_bytes;
102 unsigned int channel_interleave_bytes;
103 unsigned int num_banks;
104 unsigned int num_chans;
105 unsigned int vmm_page_size_bytes;
106 unsigned int hostvm_min_page_size_bytes;
107 unsigned int gpuvm_min_page_size_bytes;
108 double dram_clock_change_latency_us;
109 double dummy_pstate_latency_us;
110 double writeback_dram_clock_change_latency_us;
111 unsigned int return_bus_width_bytes;
112 unsigned int voltage_override;
113 double xfc_bus_transport_time_us;
114 double xfc_xbuf_latency_tolerance_us;
115 int use_urgent_burst_bw;
116 double min_dcfclk;
117 bool do_urgent_latency_adjustment;
118 double urgent_latency_adjustment_fabric_clock_component_us;
119 double urgent_latency_adjustment_fabric_clock_reference_mhz;
120 bool disable_dram_clock_change_vactive_support;
121 bool allow_dram_clock_one_display_vactive;
122};
123
124struct _vcs_dpi_ip_params_st {
125 bool use_min_dcfclk;
126 bool gpuvm_enable;
127 bool hostvm_enable;
128 unsigned int gpuvm_max_page_table_levels;
129 unsigned int hostvm_max_page_table_levels;
130 unsigned int hostvm_cached_page_table_levels;
131 unsigned int pte_group_size_bytes;
132 unsigned int max_inter_dcn_tile_repeaters;
133 unsigned int num_dsc;
134 unsigned int odm_capable;
135 unsigned int rob_buffer_size_kbytes;
136 unsigned int det_buffer_size_kbytes;
137 unsigned int dpte_buffer_size_in_pte_reqs_luma;
138 unsigned int dpte_buffer_size_in_pte_reqs_chroma;
139 unsigned int pde_proc_buffer_size_64k_reqs;
140 unsigned int dpp_output_buffer_pixels;
141 unsigned int opp_output_buffer_lines;
142 unsigned int pixel_chunk_size_kbytes;
143 unsigned char pte_enable;
144 unsigned int pte_chunk_size_kbytes;
145 unsigned int meta_chunk_size_kbytes;
146 unsigned int writeback_chunk_size_kbytes;
147 unsigned int line_buffer_size_bits;
148 unsigned int max_line_buffer_lines;
149 unsigned int writeback_luma_buffer_size_kbytes;
150 unsigned int writeback_chroma_buffer_size_kbytes;
151 unsigned int writeback_chroma_line_buffer_width_pixels;
152
153 unsigned int writeback_interface_buffer_size_kbytes;
154 unsigned int writeback_line_buffer_buffer_size;
155
156 unsigned int writeback_10bpc420_supported;
157 double writeback_max_hscl_ratio;
158 double writeback_max_vscl_ratio;
159 double writeback_min_hscl_ratio;
160 double writeback_min_vscl_ratio;
161 unsigned int writeback_max_hscl_taps;
162 unsigned int writeback_max_vscl_taps;
163 unsigned int writeback_line_buffer_luma_buffer_size;
164 unsigned int writeback_line_buffer_chroma_buffer_size;
165
166 unsigned int max_page_table_levels;
167 unsigned int max_num_dpp;
168 unsigned int max_num_otg;
169 unsigned int cursor_chunk_size;
170 unsigned int cursor_buffer_size;
171 unsigned int max_num_wb;
172 unsigned int max_dchub_pscl_bw_pix_per_clk;
173 unsigned int max_pscl_lb_bw_pix_per_clk;
174 unsigned int max_lb_vscl_bw_pix_per_clk;
175 unsigned int max_vscl_hscl_bw_pix_per_clk;
176 double max_hscl_ratio;
177 double max_vscl_ratio;
178 unsigned int hscl_mults;
179 unsigned int vscl_mults;
180 unsigned int max_hscl_taps;
181 unsigned int max_vscl_taps;
182 unsigned int xfc_supported;
183 unsigned int ptoi_supported;
184 unsigned int gfx7_compat_tiling_supported;
185
186 bool odm_combine_4to1_supported;
187 bool dynamic_metadata_vm_enabled;
188 unsigned int max_num_hdmi_frl_outputs;
189
190 unsigned int xfc_fill_constant_bytes;
191 double dispclk_ramp_margin_percent;
192 double xfc_fill_bw_overhead_percent;
193 double underscan_factor;
194 unsigned int min_vblank_lines;
195 unsigned int dppclk_delay_subtotal;
196 unsigned int dispclk_delay_subtotal;
197 double dcfclk_cstate_latency;
198 unsigned int dppclk_delay_scl;
199 unsigned int dppclk_delay_scl_lb_only;
200 unsigned int dppclk_delay_cnvc_formatter;
201 unsigned int dppclk_delay_cnvc_cursor;
202 unsigned int is_line_buffer_bpp_fixed;
203 unsigned int line_buffer_fixed_bpp;
204 unsigned int dcc_supported;
205
206 unsigned int IsLineBufferBppFixed;
207 unsigned int LineBufferFixedBpp;
208 unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
209 unsigned int bug_forcing_LC_req_same_size_fixed;
210 unsigned int number_of_cursors;
211};
212
213struct _vcs_dpi_display_xfc_params_st {
214 double xfc_tslv_vready_offset_us;
215 double xfc_tslv_vupdate_width_us;
216 double xfc_tslv_vupdate_offset_us;
217 int xfc_slv_chunk_size_bytes;
218};
219
220struct _vcs_dpi_display_pipe_source_params_st {
221 int source_format;
222 unsigned char dcc;
223 unsigned int dcc_rate;
224 unsigned int dcc_rate_chroma;
225 unsigned char dcc_use_global;
226 unsigned char vm;
227 bool gpuvm; // gpuvm enabled
228 bool hostvm; // hostvm enabled
229 bool gpuvm_levels_force_en;
230 unsigned int gpuvm_levels_force;
231 bool hostvm_levels_force_en;
232 unsigned int hostvm_levels_force;
233 int source_scan;
234 int sw_mode;
235 int macro_tile_size;
236 unsigned int surface_width_y;
237 unsigned int surface_height_y;
238 unsigned int surface_width_c;
239 unsigned int surface_height_c;
240 unsigned int viewport_width;
241 unsigned int viewport_height;
242 unsigned int viewport_y_y;
243 unsigned int viewport_y_c;
244 unsigned int viewport_width_c;
245 unsigned int viewport_height_c;
246 unsigned int data_pitch;
247 unsigned int data_pitch_c;
248 unsigned int meta_pitch;
249 unsigned int meta_pitch_c;
250 unsigned int cur0_src_width;
251 int cur0_bpp;
252 unsigned int cur1_src_width;
253 int cur1_bpp;
254 int num_cursors;
255 unsigned char is_hsplit;
256 unsigned char dynamic_metadata_enable;
257 unsigned int dynamic_metadata_lines_before_active;
258 unsigned int dynamic_metadata_xmit_bytes;
259 unsigned int hsplit_grp;
260 unsigned char xfc_enable;
261 unsigned char xfc_slave;
262 unsigned char immediate_flip;
263 struct _vcs_dpi_display_xfc_params_st xfc_params;
264 //for vstartuplines calculation freesync
265 unsigned char v_total_min;
266 unsigned char v_total_max;
267};
268struct writeback_st {
269 int wb_src_height;
270 int wb_src_width;
271 int wb_dst_width;
272 int wb_dst_height;
273 int wb_pixel_format;
274 int wb_htaps_luma;
275 int wb_vtaps_luma;
276 int wb_htaps_chroma;
277 int wb_vtaps_chroma;
278 double wb_hratio;
279 double wb_vratio;
280};
281
282struct _vcs_dpi_display_output_params_st {
283 int dp_lanes;
284 double output_bpp;
285 int dsc_enable;
286 int wb_enable;
287 int num_active_wb;
288 int output_bpc;
289 int output_type;
290 int output_format;
291 int dsc_slices;
292 int max_audio_sample_rate;
293 struct writeback_st wb;
294};
295
296struct _vcs_dpi_scaler_ratio_depth_st {
297 double hscl_ratio;
298 double vscl_ratio;
299 double hscl_ratio_c;
300 double vscl_ratio_c;
301 double vinit;
302 double vinit_c;
303 double vinit_bot;
304 double vinit_bot_c;
305 int lb_depth;
306 int scl_enable;
307};
308
309struct _vcs_dpi_scaler_taps_st {
310 unsigned int htaps;
311 unsigned int vtaps;
312 unsigned int htaps_c;
313 unsigned int vtaps_c;
314};
315
316struct _vcs_dpi_display_pipe_dest_params_st {
317 unsigned int recout_width;
318 unsigned int recout_height;
319 unsigned int full_recout_width;
320 unsigned int full_recout_height;
321 unsigned int hblank_start;
322 unsigned int hblank_end;
323 unsigned int vblank_start;
324 unsigned int vblank_end;
325 unsigned int htotal;
326 unsigned int vtotal;
327 unsigned int vactive;
328 unsigned int hactive;
329 unsigned int vstartup_start;
330 unsigned int vupdate_offset;
331 unsigned int vupdate_width;
332 unsigned int vready_offset;
333 unsigned char interlaced;
334 double pixel_rate_mhz;
335 unsigned char synchronized_vblank_all_planes;
336 unsigned char otg_inst;
337 unsigned int odm_combine;
338 unsigned char use_maximum_vstartup;
339 unsigned int vtotal_max;
340 unsigned int vtotal_min;
341};
342
343struct _vcs_dpi_display_pipe_params_st {
344 display_pipe_source_params_st src;
345 display_pipe_dest_params_st dest;
346 scaler_ratio_depth_st scale_ratio_depth;
347 scaler_taps_st scale_taps;
348};
349
350struct _vcs_dpi_display_clocks_and_cfg_st {
351 int voltage;
352 double dppclk_mhz;
353 double refclk_mhz;
354 double dispclk_mhz;
355 double dcfclk_mhz;
356 double socclk_mhz;
357};
358
359struct _vcs_dpi_display_e2e_pipe_params_st {
360 display_pipe_params_st pipe;
361 display_output_params_st dout;
362 display_clocks_and_cfg_st clks_cfg;
363};
364
365struct _vcs_dpi_display_data_rq_misc_params_st {
366 unsigned int full_swath_bytes;
367 unsigned int stored_swath_bytes;
368 unsigned int blk256_height;
369 unsigned int blk256_width;
370 unsigned int req_height;
371 unsigned int req_width;
372};
373
374struct _vcs_dpi_display_data_rq_sizing_params_st {
375 unsigned int chunk_bytes;
376 unsigned int min_chunk_bytes;
377 unsigned int meta_chunk_bytes;
378 unsigned int min_meta_chunk_bytes;
379 unsigned int mpte_group_bytes;
380 unsigned int dpte_group_bytes;
381};
382
383struct _vcs_dpi_display_data_rq_dlg_params_st {
384 unsigned int swath_width_ub;
385 unsigned int swath_height;
386 unsigned int req_per_swath_ub;
387 unsigned int meta_pte_bytes_per_frame_ub;
388 unsigned int dpte_req_per_row_ub;
389 unsigned int dpte_groups_per_row_ub;
390 unsigned int dpte_row_height;
391 unsigned int dpte_bytes_per_row_ub;
392 unsigned int meta_chunks_per_row_ub;
393 unsigned int meta_req_per_row_ub;
394 unsigned int meta_row_height;
395 unsigned int meta_bytes_per_row_ub;
396};
397
398struct _vcs_dpi_display_rq_dlg_params_st {
399 display_data_rq_dlg_params_st rq_l;
400 display_data_rq_dlg_params_st rq_c;
401};
402
403struct _vcs_dpi_display_rq_sizing_params_st {
404 display_data_rq_sizing_params_st rq_l;
405 display_data_rq_sizing_params_st rq_c;
406};
407
408struct _vcs_dpi_display_rq_misc_params_st {
409 display_data_rq_misc_params_st rq_l;
410 display_data_rq_misc_params_st rq_c;
411};
412
413struct _vcs_dpi_display_rq_params_st {
414 unsigned char yuv420;
415 unsigned char yuv420_10bpc;
416 unsigned char rgbe_alpha;
417 display_rq_misc_params_st misc;
418 display_rq_sizing_params_st sizing;
419 display_rq_dlg_params_st dlg;
420};
421
422struct _vcs_dpi_display_dlg_regs_st {
423 unsigned int refcyc_h_blank_end;
424 unsigned int dlg_vblank_end;
425 unsigned int min_dst_y_next_start;
426 unsigned int refcyc_per_htotal;
427 unsigned int refcyc_x_after_scaler;
428 unsigned int dst_y_after_scaler;
429 unsigned int dst_y_prefetch;
430 unsigned int dst_y_per_vm_vblank;
431 unsigned int dst_y_per_row_vblank;
432 unsigned int dst_y_per_vm_flip;
433 unsigned int dst_y_per_row_flip;
434 unsigned int ref_freq_to_pix_freq;
435 unsigned int vratio_prefetch;
436 unsigned int vratio_prefetch_c;
437 unsigned int refcyc_per_pte_group_vblank_l;
438 unsigned int refcyc_per_pte_group_vblank_c;
439 unsigned int refcyc_per_meta_chunk_vblank_l;
440 unsigned int refcyc_per_meta_chunk_vblank_c;
441 unsigned int refcyc_per_pte_group_flip_l;
442 unsigned int refcyc_per_pte_group_flip_c;
443 unsigned int refcyc_per_meta_chunk_flip_l;
444 unsigned int refcyc_per_meta_chunk_flip_c;
445 unsigned int dst_y_per_pte_row_nom_l;
446 unsigned int dst_y_per_pte_row_nom_c;
447 unsigned int refcyc_per_pte_group_nom_l;
448 unsigned int refcyc_per_pte_group_nom_c;
449 unsigned int dst_y_per_meta_row_nom_l;
450 unsigned int dst_y_per_meta_row_nom_c;
451 unsigned int refcyc_per_meta_chunk_nom_l;
452 unsigned int refcyc_per_meta_chunk_nom_c;
453 unsigned int refcyc_per_line_delivery_pre_l;
454 unsigned int refcyc_per_line_delivery_pre_c;
455 unsigned int refcyc_per_line_delivery_l;
456 unsigned int refcyc_per_line_delivery_c;
457 unsigned int chunk_hdl_adjust_cur0;
458 unsigned int chunk_hdl_adjust_cur1;
459 unsigned int vready_after_vcount0;
460 unsigned int dst_y_offset_cur0;
461 unsigned int dst_y_offset_cur1;
462 unsigned int xfc_reg_transfer_delay;
463 unsigned int xfc_reg_precharge_delay;
464 unsigned int xfc_reg_remote_surface_flip_latency;
465 unsigned int xfc_reg_prefetch_margin;
466 unsigned int dst_y_delta_drq_limit;
467 unsigned int refcyc_per_vm_group_vblank;
468 unsigned int refcyc_per_vm_group_flip;
469 unsigned int refcyc_per_vm_req_vblank;
470 unsigned int refcyc_per_vm_req_flip;
471 unsigned int refcyc_per_vm_dmdata;
472};
473
474struct _vcs_dpi_display_ttu_regs_st {
475 unsigned int qos_level_low_wm;
476 unsigned int qos_level_high_wm;
477 unsigned int min_ttu_vblank;
478 unsigned int qos_level_flip;
479 unsigned int refcyc_per_req_delivery_l;
480 unsigned int refcyc_per_req_delivery_c;
481 unsigned int refcyc_per_req_delivery_cur0;
482 unsigned int refcyc_per_req_delivery_cur1;
483 unsigned int refcyc_per_req_delivery_pre_l;
484 unsigned int refcyc_per_req_delivery_pre_c;
485 unsigned int refcyc_per_req_delivery_pre_cur0;
486 unsigned int refcyc_per_req_delivery_pre_cur1;
487 unsigned int qos_level_fixed_l;
488 unsigned int qos_level_fixed_c;
489 unsigned int qos_level_fixed_cur0;
490 unsigned int qos_level_fixed_cur1;
491 unsigned int qos_ramp_disable_l;
492 unsigned int qos_ramp_disable_c;
493 unsigned int qos_ramp_disable_cur0;
494 unsigned int qos_ramp_disable_cur1;
495};
496
497struct _vcs_dpi_display_data_rq_regs_st {
498 unsigned int chunk_size;
499 unsigned int min_chunk_size;
500 unsigned int meta_chunk_size;
501 unsigned int min_meta_chunk_size;
502 unsigned int dpte_group_size;
503 unsigned int mpte_group_size;
504 unsigned int swath_height;
505 unsigned int pte_row_height_linear;
506};
507
508struct _vcs_dpi_display_rq_regs_st {
509 display_data_rq_regs_st rq_regs_l;
510 display_data_rq_regs_st rq_regs_c;
511 unsigned int drq_expansion_mode;
512 unsigned int prq_expansion_mode;
513 unsigned int mrq_expansion_mode;
514 unsigned int crq_expansion_mode;
515 unsigned int plane1_base_address;
516};
517
518struct _vcs_dpi_display_dlg_sys_params_st {
519 double t_mclk_wm_us;
520 double t_urg_wm_us;
521 double t_sr_wm_us;
522 double t_extra_us;
523 double mem_trip_us;
524 double t_srx_delay_us;
525 double deepsleep_dcfclk_mhz;
526 double total_flip_bw;
527 unsigned int total_flip_bytes;
528};
529
530struct _vcs_dpi_display_arb_params_st {
531 int max_req_outstanding;
532 int min_req_outstanding;
533 int sat_level_us;
534};
535
536#endif /*__DISPLAY_MODE_STRUCTS_H__*/