tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
4 *
5 * Copyright (C) 2015 Atmel,
6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 */
8
9#include <dt-bindings/dma/at91.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/clock/at91.h>
12#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
13
14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 model = "Atmel SAMA5D2 family SoC";
18 compatible = "atmel,sama5d2";
19 interrupt-parent = <&aic>;
20
21 aliases {
22 serial0 = &uart1;
23 serial1 = &uart3;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu@0 {
31 device_type = "cpu";
32 compatible = "arm,cortex-a5";
33 reg = <0>;
34 next-level-cache = <&L2>;
35 };
36 };
37
38 pmu {
39 compatible = "arm,cortex-a5-pmu";
40 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
41 };
42
43 etb {
44 compatible = "arm,coresight-etb10", "arm,primecell";
45 reg = <0x740000 0x1000>;
46
47 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
48 clock-names = "apb_pclk";
49
50 in-ports {
51 port {
52 etb_in: endpoint {
53 remote-endpoint = <&etm_out>;
54 };
55 };
56 };
57 };
58
59 etm {
60 compatible = "arm,coresight-etm3x", "arm,primecell";
61 reg = <0x73C000 0x1000>;
62
63 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
64 clock-names = "apb_pclk";
65
66 out-ports {
67 port {
68 etm_out: endpoint {
69 remote-endpoint = <&etb_in>;
70 };
71 };
72 };
73 };
74
75 memory {
76 device_type = "memory";
77 reg = <0x20000000 0x20000000>;
78 };
79
80 clocks {
81 slow_xtal: slow_xtal {
82 compatible = "fixed-clock";
83 #clock-cells = <0>;
84 clock-frequency = <0>;
85 };
86
87 main_xtal: main_xtal {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <0>;
91 };
92 };
93
94 ns_sram: sram@200000 {
95 compatible = "mmio-sram";
96 reg = <0x00200000 0x20000>;
97 };
98
99 ahb {
100 compatible = "simple-bus";
101 #address-cells = <1>;
102 #size-cells = <1>;
103 ranges;
104
105 nfc_sram: sram@100000 {
106 compatible = "mmio-sram";
107 no-memory-wc;
108 reg = <0x00100000 0x2400>;
109 };
110
111 usb0: gadget@300000 {
112 compatible = "atmel,sama5d3-udc";
113 reg = <0x00300000 0x100000
114 0xfc02c000 0x400>;
115 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
116 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
117 clock-names = "pclk", "hclk";
118 status = "disabled";
119 };
120
121 usb1: ohci@400000 {
122 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
123 reg = <0x00400000 0x100000>;
124 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
125 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>;
126 clock-names = "ohci_clk", "hclk", "uhpck";
127 status = "disabled";
128 };
129
130 usb2: ehci@500000 {
131 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
132 reg = <0x00500000 0x100000>;
133 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
134 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>;
135 clock-names = "usb_clk", "ehci_clk";
136 status = "disabled";
137 };
138
139 L2: cache-controller@a00000 {
140 compatible = "arm,pl310-cache";
141 reg = <0x00a00000 0x1000>;
142 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
143 cache-unified;
144 cache-level = <2>;
145 };
146
147 ebi: ebi@10000000 {
148 compatible = "atmel,sama5d3-ebi";
149 #address-cells = <2>;
150 #size-cells = <1>;
151 atmel,smc = <&hsmc>;
152 reg = <0x10000000 0x10000000
153 0x60000000 0x30000000>;
154 ranges = <0x0 0x0 0x10000000 0x10000000
155 0x1 0x0 0x60000000 0x10000000
156 0x2 0x0 0x70000000 0x10000000
157 0x3 0x0 0x80000000 0x10000000>;
158 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
159 status = "disabled";
160
161 nand_controller: nand-controller {
162 compatible = "atmel,sama5d3-nand-controller";
163 atmel,nfc-sram = <&nfc_sram>;
164 atmel,nfc-io = <&nfc_io>;
165 ecc-engine = <&pmecc>;
166 #address-cells = <2>;
167 #size-cells = <1>;
168 ranges;
169 status = "disabled";
170 };
171 };
172
173 sdmmc0: sdio-host@a0000000 {
174 compatible = "atmel,sama5d2-sdhci";
175 reg = <0xa0000000 0x300>;
176 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
177 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
178 clock-names = "hclock", "multclk", "baseclk";
179 assigned-clocks = <&pmc PMC_TYPE_GCK 31>;
180 assigned-clock-rates = <480000000>;
181 status = "disabled";
182 };
183
184 sdmmc1: sdio-host@b0000000 {
185 compatible = "atmel,sama5d2-sdhci";
186 reg = <0xb0000000 0x300>;
187 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
188 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
189 clock-names = "hclock", "multclk", "baseclk";
190 assigned-clocks = <&pmc PMC_TYPE_GCK 32>;
191 assigned-clock-rates = <480000000>;
192 status = "disabled";
193 };
194
195 nfc_io: nfc-io@c0000000 {
196 compatible = "atmel,sama5d3-nfc-io", "syscon";
197 reg = <0xc0000000 0x8000000>;
198 };
199
200 apb {
201 compatible = "simple-bus";
202 #address-cells = <1>;
203 #size-cells = <1>;
204 ranges;
205
206 hlcdc: hlcdc@f0000000 {
207 compatible = "atmel,sama5d2-hlcdc";
208 reg = <0xf0000000 0x2000>;
209 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
210 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
211 clock-names = "periph_clk","sys_clk", "slow_clk";
212 status = "disabled";
213
214 hlcdc-display-controller {
215 compatible = "atmel,hlcdc-display-controller";
216 #address-cells = <1>;
217 #size-cells = <0>;
218
219 port@0 {
220 #address-cells = <1>;
221 #size-cells = <0>;
222 reg = <0>;
223 };
224 };
225
226 hlcdc_pwm: hlcdc-pwm {
227 compatible = "atmel,hlcdc-pwm";
228 #pwm-cells = <3>;
229 };
230 };
231
232 isc: isc@f0008000 {
233 compatible = "atmel,sama5d2-isc";
234 reg = <0xf0008000 0x4000>;
235 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
236 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>;
237 clock-names = "hclock", "iscck", "gck";
238 #clock-cells = <0>;
239 clock-output-names = "isc-mck";
240 status = "disabled";
241 };
242
243 ramc0: ramc@f000c000 {
244 compatible = "atmel,sama5d3-ddramc";
245 reg = <0xf000c000 0x200>;
246 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>;
247 clock-names = "ddrck", "mpddr";
248 };
249
250 dma0: dma-controller@f0010000 {
251 compatible = "atmel,sama5d4-dma";
252 reg = <0xf0010000 0x1000>;
253 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
254 #dma-cells = <1>;
255 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
256 clock-names = "dma_clk";
257 };
258
259 /* Place dma1 here despite its address */
260 dma1: dma-controller@f0004000 {
261 compatible = "atmel,sama5d4-dma";
262 reg = <0xf0004000 0x1000>;
263 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
264 #dma-cells = <1>;
265 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
266 clock-names = "dma_clk";
267 };
268
269 pmc: pmc@f0014000 {
270 compatible = "atmel,sama5d2-pmc", "syscon";
271 reg = <0xf0014000 0x160>;
272 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
273 #clock-cells = <2>;
274 clocks = <&clk32k>, <&main_xtal>;
275 clock-names = "slow_clk", "main_xtal";
276 };
277
278 qspi0: spi@f0020000 {
279 compatible = "atmel,sama5d2-qspi";
280 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
281 reg-names = "qspi_base", "qspi_mmap";
282 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
283 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
284 #address-cells = <1>;
285 #size-cells = <0>;
286 status = "disabled";
287 };
288
289 qspi1: spi@f0024000 {
290 compatible = "atmel,sama5d2-qspi";
291 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
292 reg-names = "qspi_base", "qspi_mmap";
293 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
294 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
295 #address-cells = <1>;
296 #size-cells = <0>;
297 status = "disabled";
298 };
299
300 sha@f0028000 {
301 compatible = "atmel,at91sam9g46-sha";
302 reg = <0xf0028000 0x100>;
303 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
304 dmas = <&dma0
305 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
306 AT91_XDMAC_DT_PERID(30))>;
307 dma-names = "tx";
308 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
309 clock-names = "sha_clk";
310 status = "okay";
311 };
312
313 aes@f002c000 {
314 compatible = "atmel,at91sam9g46-aes";
315 reg = <0xf002c000 0x100>;
316 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
317 dmas = <&dma0
318 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
319 AT91_XDMAC_DT_PERID(26))>,
320 <&dma0
321 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
322 AT91_XDMAC_DT_PERID(27))>;
323 dma-names = "tx", "rx";
324 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
325 clock-names = "aes_clk";
326 status = "okay";
327 };
328
329 spi0: spi@f8000000 {
330 compatible = "atmel,at91rm9200-spi";
331 reg = <0xf8000000 0x100>;
332 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
333 dmas = <&dma0
334 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
335 AT91_XDMAC_DT_PERID(6))>,
336 <&dma0
337 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
338 AT91_XDMAC_DT_PERID(7))>;
339 dma-names = "tx", "rx";
340 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
341 clock-names = "spi_clk";
342 atmel,fifo-size = <16>;
343 #address-cells = <1>;
344 #size-cells = <0>;
345 status = "disabled";
346 };
347
348 ssc0: ssc@f8004000 {
349 compatible = "atmel,at91sam9g45-ssc";
350 reg = <0xf8004000 0x4000>;
351 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
352 dmas = <&dma0
353 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
354 AT91_XDMAC_DT_PERID(21))>,
355 <&dma0
356 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
357 AT91_XDMAC_DT_PERID(22))>;
358 dma-names = "tx", "rx";
359 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
360 clock-names = "pclk";
361 status = "disabled";
362 };
363
364 macb0: ethernet@f8008000 {
365 compatible = "atmel,sama5d2-gem";
366 reg = <0xf8008000 0x1000>;
367 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
368 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
369 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
370 #address-cells = <1>;
371 #size-cells = <0>;
372 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
373 clock-names = "hclk", "pclk";
374 status = "disabled";
375 };
376
377 tcb0: timer@f800c000 {
378 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
379 #address-cells = <1>;
380 #size-cells = <0>;
381 reg = <0xf800c000 0x100>;
382 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
383 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&clk32k>;
384 clock-names = "t0_clk", "slow_clk";
385 };
386
387 tcb1: timer@f8010000 {
388 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
389 #address-cells = <1>;
390 #size-cells = <0>;
391 reg = <0xf8010000 0x100>;
392 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
393 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&clk32k>;
394 clock-names = "t0_clk", "slow_clk";
395 };
396
397 hsmc: hsmc@f8014000 {
398 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
399 reg = <0xf8014000 0x1000>;
400 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
401 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
402 #address-cells = <1>;
403 #size-cells = <1>;
404 ranges;
405
406 pmecc: ecc-engine@f8014070 {
407 compatible = "atmel,sama5d2-pmecc";
408 reg = <0xf8014070 0x490>,
409 <0xf8014500 0x100>;
410 };
411 };
412
413 pdmic: pdmic@f8018000 {
414 compatible = "atmel,sama5d2-pdmic";
415 reg = <0xf8018000 0x124>;
416 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
417 dmas = <&dma0
418 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
419 | AT91_XDMAC_DT_PERID(50))>;
420 dma-names = "rx";
421 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>;
422 clock-names = "pclk", "gclk";
423 status = "disabled";
424 };
425
426 uart0: serial@f801c000 {
427 compatible = "atmel,at91sam9260-usart";
428 reg = <0xf801c000 0x100>;
429 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
430 dmas = <&dma0
431 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
432 AT91_XDMAC_DT_PERID(35))>,
433 <&dma0
434 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
435 AT91_XDMAC_DT_PERID(36))>;
436 dma-names = "tx", "rx";
437 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
438 clock-names = "usart";
439 status = "disabled";
440 };
441
442 uart1: serial@f8020000 {
443 compatible = "atmel,at91sam9260-usart";
444 reg = <0xf8020000 0x100>;
445 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
446 dmas = <&dma0
447 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
448 AT91_XDMAC_DT_PERID(37))>,
449 <&dma0
450 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
451 AT91_XDMAC_DT_PERID(38))>;
452 dma-names = "tx", "rx";
453 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
454 clock-names = "usart";
455 status = "disabled";
456 };
457
458 uart2: serial@f8024000 {
459 compatible = "atmel,at91sam9260-usart";
460 reg = <0xf8024000 0x100>;
461 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
462 dmas = <&dma0
463 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
464 AT91_XDMAC_DT_PERID(39))>,
465 <&dma0
466 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
467 AT91_XDMAC_DT_PERID(40))>;
468 dma-names = "tx", "rx";
469 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
470 clock-names = "usart";
471 status = "disabled";
472 };
473
474 i2c0: i2c@f8028000 {
475 compatible = "atmel,sama5d2-i2c";
476 reg = <0xf8028000 0x100>;
477 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
478 dmas = <&dma0
479 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
480 AT91_XDMAC_DT_PERID(0))>,
481 <&dma0
482 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
483 AT91_XDMAC_DT_PERID(1))>;
484 dma-names = "tx", "rx";
485 #address-cells = <1>;
486 #size-cells = <0>;
487 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
488 atmel,fifo-size = <16>;
489 status = "disabled";
490 };
491
492 pwm0: pwm@f802c000 {
493 compatible = "atmel,sama5d2-pwm";
494 reg = <0xf802c000 0x4000>;
495 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
496 #pwm-cells = <3>;
497 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
498 status = "disabled";
499 };
500
501 sfr: sfr@f8030000 {
502 compatible = "atmel,sama5d2-sfr", "syscon";
503 reg = <0xf8030000 0x98>;
504 };
505
506 flx0: flexcom@f8034000 {
507 compatible = "atmel,sama5d2-flexcom";
508 reg = <0xf8034000 0x200>;
509 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
510 #address-cells = <1>;
511 #size-cells = <1>;
512 ranges = <0x0 0xf8034000 0x800>;
513 status = "disabled";
514
515 uart5: serial@200 {
516 compatible = "atmel,at91sam9260-usart";
517 reg = <0x200 0x200>;
518 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
519 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
520 clock-names = "usart";
521 dmas = <&dma0
522 (AT91_XDMAC_DT_MEM_IF(0) |
523 AT91_XDMAC_DT_PER_IF(1) |
524 AT91_XDMAC_DT_PERID(11))>,
525 <&dma0
526 (AT91_XDMAC_DT_MEM_IF(0) |
527 AT91_XDMAC_DT_PER_IF(1) |
528 AT91_XDMAC_DT_PERID(12))>;
529 dma-names = "tx", "rx";
530 atmel,fifo-size = <32>;
531 status = "disabled";
532 };
533
534 spi2: spi@400 {
535 compatible = "atmel,at91rm9200-spi";
536 reg = <0x400 0x200>;
537 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
538 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
539 clock-names = "spi_clk";
540 dmas = <&dma0
541 (AT91_XDMAC_DT_MEM_IF(0) |
542 AT91_XDMAC_DT_PER_IF(1) |
543 AT91_XDMAC_DT_PERID(11))>,
544 <&dma0
545 (AT91_XDMAC_DT_MEM_IF(0) |
546 AT91_XDMAC_DT_PER_IF(1) |
547 AT91_XDMAC_DT_PERID(12))>;
548 dma-names = "tx", "rx";
549 atmel,fifo-size = <16>;
550 status = "disabled";
551 };
552
553 i2c2: i2c@600 {
554 compatible = "atmel,sama5d2-i2c";
555 reg = <0x600 0x200>;
556 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
557 #address-cells = <1>;
558 #size-cells = <0>;
559 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
560 dmas = <&dma0
561 (AT91_XDMAC_DT_MEM_IF(0) |
562 AT91_XDMAC_DT_PER_IF(1) |
563 AT91_XDMAC_DT_PERID(11))>,
564 <&dma0
565 (AT91_XDMAC_DT_MEM_IF(0) |
566 AT91_XDMAC_DT_PER_IF(1) |
567 AT91_XDMAC_DT_PERID(12))>;
568 dma-names = "tx", "rx";
569 atmel,fifo-size = <16>;
570 status = "disabled";
571 };
572 };
573
574 flx1: flexcom@f8038000 {
575 compatible = "atmel,sama5d2-flexcom";
576 reg = <0xf8038000 0x200>;
577 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
578 #address-cells = <1>;
579 #size-cells = <1>;
580 ranges = <0x0 0xf8038000 0x800>;
581 status = "disabled";
582
583 uart6: serial@200 {
584 compatible = "atmel,at91sam9260-usart";
585 reg = <0x200 0x200>;
586 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
587 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
588 clock-names = "usart";
589 dmas = <&dma0
590 (AT91_XDMAC_DT_MEM_IF(0) |
591 AT91_XDMAC_DT_PER_IF(1) |
592 AT91_XDMAC_DT_PERID(13))>,
593 <&dma0
594 (AT91_XDMAC_DT_MEM_IF(0) |
595 AT91_XDMAC_DT_PER_IF(1) |
596 AT91_XDMAC_DT_PERID(14))>;
597 dma-names = "tx", "rx";
598 atmel,fifo-size = <32>;
599 status = "disabled";
600 };
601
602 spi3: spi@400 {
603 compatible = "atmel,at91rm9200-spi";
604 reg = <0x400 0x200>;
605 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
606 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
607 clock-names = "spi_clk";
608 dmas = <&dma0
609 (AT91_XDMAC_DT_MEM_IF(0) |
610 AT91_XDMAC_DT_PER_IF(1) |
611 AT91_XDMAC_DT_PERID(13))>,
612 <&dma0
613 (AT91_XDMAC_DT_MEM_IF(0) |
614 AT91_XDMAC_DT_PER_IF(1) |
615 AT91_XDMAC_DT_PERID(14))>;
616 dma-names = "tx", "rx";
617 atmel,fifo-size = <16>;
618 status = "disabled";
619 };
620
621 i2c3: i2c@600 {
622 compatible = "atmel,sama5d2-i2c";
623 reg = <0x600 0x200>;
624 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
625 #address-cells = <1>;
626 #size-cells = <0>;
627 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
628 dmas = <&dma0
629 (AT91_XDMAC_DT_MEM_IF(0) |
630 AT91_XDMAC_DT_PER_IF(1) |
631 AT91_XDMAC_DT_PERID(13))>,
632 <&dma0
633 (AT91_XDMAC_DT_MEM_IF(0) |
634 AT91_XDMAC_DT_PER_IF(1) |
635 AT91_XDMAC_DT_PERID(14))>;
636 dma-names = "tx", "rx";
637 atmel,fifo-size = <16>;
638 status = "disabled";
639 };
640 };
641
642 securam: sram@f8044000 {
643 compatible = "atmel,sama5d2-securam", "mmio-sram";
644 reg = <0xf8044000 0x1420>;
645 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
646 #address-cells = <1>;
647 #size-cells = <1>;
648 ranges = <0 0xf8044000 0x1420>;
649 };
650
651 reset_controller: rstc@f8048000 {
652 compatible = "atmel,sama5d3-rstc";
653 reg = <0xf8048000 0x10>;
654 clocks = <&clk32k>;
655 };
656
657 shutdown_controller: shdwc@f8048010 {
658 compatible = "atmel,sama5d2-shdwc";
659 reg = <0xf8048010 0x10>;
660 clocks = <&clk32k>;
661 #address-cells = <1>;
662 #size-cells = <0>;
663 atmel,wakeup-rtc-timer;
664 };
665
666 pit: timer@f8048030 {
667 compatible = "atmel,at91sam9260-pit";
668 reg = <0xf8048030 0x10>;
669 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
670 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
671 };
672
673 watchdog: watchdog@f8048040 {
674 compatible = "atmel,sama5d4-wdt";
675 reg = <0xf8048040 0x10>;
676 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
677 clocks = <&clk32k>;
678 status = "disabled";
679 };
680
681 clk32k: sckc@f8048050 {
682 compatible = "atmel,sama5d4-sckc";
683 reg = <0xf8048050 0x4>;
684
685 clocks = <&slow_xtal>;
686 #clock-cells = <0>;
687 };
688
689 rtc: rtc@f80480b0 {
690 compatible = "atmel,sama5d2-rtc";
691 reg = <0xf80480b0 0x30>;
692 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
693 clocks = <&clk32k>;
694 };
695
696 i2s0: i2s@f8050000 {
697 compatible = "atmel,sama5d2-i2s";
698 reg = <0xf8050000 0x100>;
699 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
700 dmas = <&dma0
701 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
702 AT91_XDMAC_DT_PERID(31))>,
703 <&dma0
704 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
705 AT91_XDMAC_DT_PERID(32))>;
706 dma-names = "tx", "rx";
707 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>;
708 clock-names = "pclk", "gclk";
709 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>;
710 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>;
711 status = "disabled";
712 };
713
714 can0: can@f8054000 {
715 compatible = "bosch,m_can";
716 reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
717 reg-names = "m_can", "message_ram";
718 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
719 <64 IRQ_TYPE_LEVEL_HIGH 7>;
720 interrupt-names = "int0", "int1";
721 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>;
722 clock-names = "hclk", "cclk";
723 assigned-clocks = <&pmc PMC_TYPE_GCK 56>;
724 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
725 assigned-clock-rates = <40000000>;
726 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
727 status = "disabled";
728 };
729
730 spi1: spi@fc000000 {
731 compatible = "atmel,at91rm9200-spi";
732 reg = <0xfc000000 0x100>;
733 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
734 dmas = <&dma0
735 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
736 AT91_XDMAC_DT_PERID(8))>,
737 <&dma0
738 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
739 AT91_XDMAC_DT_PERID(9))>;
740 dma-names = "tx", "rx";
741 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
742 clock-names = "spi_clk";
743 atmel,fifo-size = <16>;
744 #address-cells = <1>;
745 #size-cells = <0>;
746 status = "disabled";
747 };
748
749 uart3: serial@fc008000 {
750 compatible = "atmel,at91sam9260-usart";
751 reg = <0xfc008000 0x100>;
752 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
753 dmas = <&dma1
754 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
755 AT91_XDMAC_DT_PERID(41))>,
756 <&dma1
757 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
758 AT91_XDMAC_DT_PERID(42))>;
759 dma-names = "tx", "rx";
760 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
761 clock-names = "usart";
762 status = "disabled";
763 };
764
765 uart4: serial@fc00c000 {
766 compatible = "atmel,at91sam9260-usart";
767 reg = <0xfc00c000 0x100>;
768 dmas = <&dma0
769 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
770 AT91_XDMAC_DT_PERID(43))>,
771 <&dma0
772 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
773 AT91_XDMAC_DT_PERID(44))>;
774 dma-names = "tx", "rx";
775 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
776 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
777 clock-names = "usart";
778 status = "disabled";
779 };
780
781 flx2: flexcom@fc010000 {
782 compatible = "atmel,sama5d2-flexcom";
783 reg = <0xfc010000 0x200>;
784 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
785 #address-cells = <1>;
786 #size-cells = <1>;
787 ranges = <0x0 0xfc010000 0x800>;
788 status = "disabled";
789
790 uart7: serial@200 {
791 compatible = "atmel,at91sam9260-usart";
792 reg = <0x200 0x200>;
793 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
794 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
795 clock-names = "usart";
796 dmas = <&dma0
797 (AT91_XDMAC_DT_MEM_IF(0) |
798 AT91_XDMAC_DT_PER_IF(1) |
799 AT91_XDMAC_DT_PERID(15))>,
800 <&dma0
801 (AT91_XDMAC_DT_MEM_IF(0) |
802 AT91_XDMAC_DT_PER_IF(1) |
803 AT91_XDMAC_DT_PERID(16))>;
804 dma-names = "tx", "rx";
805 atmel,fifo-size = <32>;
806 status = "disabled";
807 };
808
809 spi4: spi@400 {
810 compatible = "atmel,at91rm9200-spi";
811 reg = <0x400 0x200>;
812 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
813 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
814 clock-names = "spi_clk";
815 dmas = <&dma0
816 (AT91_XDMAC_DT_MEM_IF(0) |
817 AT91_XDMAC_DT_PER_IF(1) |
818 AT91_XDMAC_DT_PERID(15))>,
819 <&dma0
820 (AT91_XDMAC_DT_MEM_IF(0) |
821 AT91_XDMAC_DT_PER_IF(1) |
822 AT91_XDMAC_DT_PERID(16))>;
823 dma-names = "tx", "rx";
824 atmel,fifo-size = <16>;
825 status = "disabled";
826 };
827
828 i2c4: i2c@600 {
829 compatible = "atmel,sama5d2-i2c";
830 reg = <0x600 0x200>;
831 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
832 #address-cells = <1>;
833 #size-cells = <0>;
834 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
835 dmas = <&dma0
836 (AT91_XDMAC_DT_MEM_IF(0) |
837 AT91_XDMAC_DT_PER_IF(1) |
838 AT91_XDMAC_DT_PERID(15))>,
839 <&dma0
840 (AT91_XDMAC_DT_MEM_IF(0) |
841 AT91_XDMAC_DT_PER_IF(1) |
842 AT91_XDMAC_DT_PERID(16))>;
843 dma-names = "tx", "rx";
844 atmel,fifo-size = <16>;
845 status = "disabled";
846 };
847 };
848
849 flx3: flexcom@fc014000 {
850 compatible = "atmel,sama5d2-flexcom";
851 reg = <0xfc014000 0x200>;
852 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
853 #address-cells = <1>;
854 #size-cells = <1>;
855 ranges = <0x0 0xfc014000 0x800>;
856 status = "disabled";
857
858 uart8: serial@200 {
859 compatible = "atmel,at91sam9260-usart";
860 reg = <0x200 0x200>;
861 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
862 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
863 clock-names = "usart";
864 dmas = <&dma0
865 (AT91_XDMAC_DT_MEM_IF(0) |
866 AT91_XDMAC_DT_PER_IF(1) |
867 AT91_XDMAC_DT_PERID(17))>,
868 <&dma0
869 (AT91_XDMAC_DT_MEM_IF(0) |
870 AT91_XDMAC_DT_PER_IF(1) |
871 AT91_XDMAC_DT_PERID(18))>;
872 dma-names = "tx", "rx";
873 atmel,fifo-size = <32>;
874 status = "disabled";
875 };
876
877 spi5: spi@400 {
878 compatible = "atmel,at91rm9200-spi";
879 reg = <0x400 0x200>;
880 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
881 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
882 clock-names = "spi_clk";
883 dmas = <&dma0
884 (AT91_XDMAC_DT_MEM_IF(0) |
885 AT91_XDMAC_DT_PER_IF(1) |
886 AT91_XDMAC_DT_PERID(17))>,
887 <&dma0
888 (AT91_XDMAC_DT_MEM_IF(0) |
889 AT91_XDMAC_DT_PER_IF(1) |
890 AT91_XDMAC_DT_PERID(18))>;
891 dma-names = "tx", "rx";
892 atmel,fifo-size = <16>;
893 status = "disabled";
894 };
895
896 i2c5: i2c@600 {
897 compatible = "atmel,sama5d2-i2c";
898 reg = <0x600 0x200>;
899 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
900 #address-cells = <1>;
901 #size-cells = <0>;
902 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
903 dmas = <&dma0
904 (AT91_XDMAC_DT_MEM_IF(0) |
905 AT91_XDMAC_DT_PER_IF(1) |
906 AT91_XDMAC_DT_PERID(17))>,
907 <&dma0
908 (AT91_XDMAC_DT_MEM_IF(0) |
909 AT91_XDMAC_DT_PER_IF(1) |
910 AT91_XDMAC_DT_PERID(18))>;
911 dma-names = "tx", "rx";
912 atmel,fifo-size = <16>;
913 status = "disabled";
914 };
915
916 };
917
918 flx4: flexcom@fc018000 {
919 compatible = "atmel,sama5d2-flexcom";
920 reg = <0xfc018000 0x200>;
921 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
922 #address-cells = <1>;
923 #size-cells = <1>;
924 ranges = <0x0 0xfc018000 0x800>;
925 status = "disabled";
926
927 uart9: serial@200 {
928 compatible = "atmel,at91sam9260-usart";
929 reg = <0x200 0x200>;
930 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
931 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
932 clock-names = "usart";
933 dmas = <&dma0
934 (AT91_XDMAC_DT_MEM_IF(0) |
935 AT91_XDMAC_DT_PER_IF(1) |
936 AT91_XDMAC_DT_PERID(19))>,
937 <&dma0
938 (AT91_XDMAC_DT_MEM_IF(0) |
939 AT91_XDMAC_DT_PER_IF(1) |
940 AT91_XDMAC_DT_PERID(20))>;
941 dma-names = "tx", "rx";
942 atmel,fifo-size = <32>;
943 status = "disabled";
944 };
945
946 spi6: spi@400 {
947 compatible = "atmel,at91rm9200-spi";
948 reg = <0x400 0x200>;
949 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
950 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
951 clock-names = "spi_clk";
952 dmas = <&dma0
953 (AT91_XDMAC_DT_MEM_IF(0) |
954 AT91_XDMAC_DT_PER_IF(1) |
955 AT91_XDMAC_DT_PERID(19))>,
956 <&dma0
957 (AT91_XDMAC_DT_MEM_IF(0) |
958 AT91_XDMAC_DT_PER_IF(1) |
959 AT91_XDMAC_DT_PERID(20))>;
960 dma-names = "tx", "rx";
961 atmel,fifo-size = <16>;
962 status = "disabled";
963 };
964
965 i2c6: i2c@600 {
966 compatible = "atmel,sama5d2-i2c";
967 reg = <0x600 0x200>;
968 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
969 #address-cells = <1>;
970 #size-cells = <0>;
971 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
972 dmas = <&dma0
973 (AT91_XDMAC_DT_MEM_IF(0) |
974 AT91_XDMAC_DT_PER_IF(1) |
975 AT91_XDMAC_DT_PERID(19))>,
976 <&dma0
977 (AT91_XDMAC_DT_MEM_IF(0) |
978 AT91_XDMAC_DT_PER_IF(1) |
979 AT91_XDMAC_DT_PERID(20))>;
980 dma-names = "tx", "rx";
981 atmel,fifo-size = <16>;
982 status = "disabled";
983 };
984 };
985
986 trng@fc01c000 {
987 compatible = "atmel,at91sam9g45-trng";
988 reg = <0xfc01c000 0x100>;
989 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
990 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
991 };
992
993 aic: interrupt-controller@fc020000 {
994 #interrupt-cells = <3>;
995 compatible = "atmel,sama5d2-aic";
996 interrupt-controller;
997 reg = <0xfc020000 0x200>;
998 atmel,external-irqs = <49>;
999 };
1000
1001 i2c1: i2c@fc028000 {
1002 compatible = "atmel,sama5d2-i2c";
1003 reg = <0xfc028000 0x100>;
1004 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1005 dmas = <&dma0
1006 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1007 AT91_XDMAC_DT_PERID(2))>,
1008 <&dma0
1009 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1010 AT91_XDMAC_DT_PERID(3))>;
1011 dma-names = "tx", "rx";
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1014 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
1015 atmel,fifo-size = <16>;
1016 status = "disabled";
1017 };
1018
1019 adc: adc@fc030000 {
1020 compatible = "atmel,sama5d2-adc";
1021 reg = <0xfc030000 0x100>;
1022 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1023 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
1024 clock-names = "adc_clk";
1025 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
1026 dma-names = "rx";
1027 atmel,min-sample-rate-hz = <200000>;
1028 atmel,max-sample-rate-hz = <20000000>;
1029 atmel,startup-time-ms = <4>;
1030 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
1031 #io-channel-cells = <1>;
1032 status = "disabled";
1033 };
1034
1035 resistive_touch: resistive-touch {
1036 compatible = "resistive-adc-touch";
1037 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
1038 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
1039 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
1040 io-channel-names = "x", "y", "pressure";
1041 touchscreen-min-pressure = <50000>;
1042 status = "disabled";
1043 };
1044
1045 pioA: pinctrl@fc038000 {
1046 compatible = "atmel,sama5d2-pinctrl";
1047 reg = <0xfc038000 0x600>;
1048 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1049 <68 IRQ_TYPE_LEVEL_HIGH 7>,
1050 <69 IRQ_TYPE_LEVEL_HIGH 7>,
1051 <70 IRQ_TYPE_LEVEL_HIGH 7>;
1052 interrupt-controller;
1053 #interrupt-cells = <2>;
1054 gpio-controller;
1055 #gpio-cells = <2>;
1056 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
1057 };
1058
1059 pioBU: secumod@fc040000 {
1060 compatible = "atmel,sama5d2-secumod", "syscon";
1061 reg = <0xfc040000 0x100>;
1062
1063 gpio-controller;
1064 #gpio-cells = <2>;
1065 };
1066
1067 tdes@fc044000 {
1068 compatible = "atmel,at91sam9g46-tdes";
1069 reg = <0xfc044000 0x100>;
1070 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1071 dmas = <&dma0
1072 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1073 AT91_XDMAC_DT_PERID(28))>,
1074 <&dma0
1075 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1076 AT91_XDMAC_DT_PERID(29))>;
1077 dma-names = "tx", "rx";
1078 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
1079 clock-names = "tdes_clk";
1080 status = "okay";
1081 };
1082
1083 classd: classd@fc048000 {
1084 compatible = "atmel,sama5d2-classd";
1085 reg = <0xfc048000 0x100>;
1086 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
1087 dmas = <&dma0
1088 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1089 AT91_XDMAC_DT_PERID(47))>;
1090 dma-names = "tx";
1091 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
1092 clock-names = "pclk", "gclk";
1093 status = "disabled";
1094 };
1095
1096 i2s1: i2s@fc04c000 {
1097 compatible = "atmel,sama5d2-i2s";
1098 reg = <0xfc04c000 0x100>;
1099 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
1100 dmas = <&dma0
1101 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1102 AT91_XDMAC_DT_PERID(33))>,
1103 <&dma0
1104 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1105 AT91_XDMAC_DT_PERID(34))>;
1106 dma-names = "tx", "rx";
1107 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>;
1108 clock-names = "pclk", "gclk";
1109 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>;
1110 assigned-parrents = <&pmc PMC_TYPE_GCK 55>;
1111 status = "disabled";
1112 };
1113
1114 can1: can@fc050000 {
1115 compatible = "bosch,m_can";
1116 reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
1117 reg-names = "m_can", "message_ram";
1118 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
1119 <65 IRQ_TYPE_LEVEL_HIGH 7>;
1120 interrupt-names = "int0", "int1";
1121 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
1122 clock-names = "hclk", "cclk";
1123 assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
1124 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
1125 assigned-clock-rates = <40000000>;
1126 bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
1127 status = "disabled";
1128 };
1129
1130 sfrbu: sfr@fc05c000 {
1131 compatible = "atmel,sama5d2-sfrbu", "syscon";
1132 reg = <0xfc05c000 0x20>;
1133 };
1134
1135 chipid@fc069000 {
1136 compatible = "atmel,sama5d2-chipid";
1137 reg = <0xfc069000 0x8>;
1138 };
1139 };
1140 };
1141};