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1Device Tree Bindings for the SDHCI Controllers present on TI's AM654 SOCs
2
3The bindings follow the mmc[1], clock[2] and interrupt[3] bindings.
4Only deviations are documented here.
5
6 [1] Documentation/devicetree/bindings/mmc/mmc.txt
7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
9
10Required Properties:
11 - compatible: should be one of:
12 "ti,am654-sdhci-5.1": SDHCI on AM654 device.
13 "ti,j721e-sdhci-8bit": 8 bit SDHCI on J721E device.
14 "ti,j721e-sdhci-4bit": 4 bit SDHCI on J721E device.
15 - reg: Must be two entries.
16 - The first should be the sdhci register space
17 - The second should the subsystem/phy register space
18 - clocks: Handles to the clock inputs.
19 - clock-names: Tuple including "clk_xin" and "clk_ahb"
20 - interrupts: Interrupt specifiers
21 Output tap delay for each speed mode:
22 - ti,otap-del-sel-legacy
23 - ti,otap-del-sel-mmc-hs
24 - ti,otap-del-sel-sd-hs
25 - ti,otap-del-sel-sdr12
26 - ti,otap-del-sel-sdr25
27 - ti,otap-del-sel-sdr50
28 - ti,otap-del-sel-sdr104
29 - ti,otap-del-sel-ddr50
30 - ti,otap-del-sel-ddr52
31 - ti,otap-del-sel-hs200
32 - ti,otap-del-sel-hs400
33 These bindings must be provided otherwise the driver will disable the
34 corresponding speed mode (i.e. all nodes must provide at least -legacy)
35
36Optional Properties (Required for ti,am654-sdhci-5.1 and ti,j721e-sdhci-8bit):
37 - ti,trm-icp: DLL trim select
38 - ti,driver-strength-ohm: driver strength in ohms.
39 Valid values are 33, 40, 50, 66 and 100 ohms.
40Optional Properties:
41 - ti,strobe-sel: strobe select delay for HS400 speed mode. Default value: 0x0.
42
43Example:
44
45 sdhci0: sdhci@4f80000 {
46 compatible = "ti,am654-sdhci-5.1";
47 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
48 power-domains = <&k3_pds 47>;
49 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
50 clock-names = "clk_ahb", "clk_xin";
51 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
52 sdhci-caps-mask = <0x80000007 0x0>;
53 mmc-ddr-1_8v;
54 ti,otap-del-sel-legacy = <0x0>;
55 ti,otap-del-sel-mmc-hs = <0x0>;
56 ti,otap-del-sel-ddr52 = <0x5>;
57 ti,otap-del-sel-hs200 = <0x5>;
58 ti,otap-del-sel-hs400 = <0x0>;
59 ti,trm-icp = <0x8>;
60 };