Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * DMA Engine test module
4 *
5 * Copyright (C) 2007 Atmel Corporation
6 * Copyright (C) 2013 Intel Corporation
7 */
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/delay.h>
11#include <linux/dma-mapping.h>
12#include <linux/dmaengine.h>
13#include <linux/freezer.h>
14#include <linux/init.h>
15#include <linux/kthread.h>
16#include <linux/sched/task.h>
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/random.h>
20#include <linux/slab.h>
21#include <linux/wait.h>
22
23static unsigned int test_buf_size = 16384;
24module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
25MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
26
27static char test_device[32];
28module_param_string(device, test_device, sizeof(test_device),
29 S_IRUGO | S_IWUSR);
30MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
31
32static unsigned int threads_per_chan = 1;
33module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
34MODULE_PARM_DESC(threads_per_chan,
35 "Number of threads to start per channel (default: 1)");
36
37static unsigned int max_channels;
38module_param(max_channels, uint, S_IRUGO | S_IWUSR);
39MODULE_PARM_DESC(max_channels,
40 "Maximum number of channels to use (default: all)");
41
42static unsigned int iterations;
43module_param(iterations, uint, S_IRUGO | S_IWUSR);
44MODULE_PARM_DESC(iterations,
45 "Iterations before stopping test (default: infinite)");
46
47static unsigned int dmatest;
48module_param(dmatest, uint, S_IRUGO | S_IWUSR);
49MODULE_PARM_DESC(dmatest,
50 "dmatest 0-memcpy 1-memset (default: 0)");
51
52static unsigned int xor_sources = 3;
53module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
54MODULE_PARM_DESC(xor_sources,
55 "Number of xor source buffers (default: 3)");
56
57static unsigned int pq_sources = 3;
58module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
59MODULE_PARM_DESC(pq_sources,
60 "Number of p+q source buffers (default: 3)");
61
62static int timeout = 3000;
63module_param(timeout, int, S_IRUGO | S_IWUSR);
64MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
65 "Pass -1 for infinite timeout");
66
67static bool noverify;
68module_param(noverify, bool, S_IRUGO | S_IWUSR);
69MODULE_PARM_DESC(noverify, "Disable data verification (default: verify)");
70
71static bool norandom;
72module_param(norandom, bool, 0644);
73MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)");
74
75static bool verbose;
76module_param(verbose, bool, S_IRUGO | S_IWUSR);
77MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
78
79static int alignment = -1;
80module_param(alignment, int, 0644);
81MODULE_PARM_DESC(alignment, "Custom data address alignment taken as 2^(alignment) (default: not used (-1))");
82
83static unsigned int transfer_size;
84module_param(transfer_size, uint, 0644);
85MODULE_PARM_DESC(transfer_size, "Optional custom transfer size in bytes (default: not used (0))");
86
87static bool polled;
88module_param(polled, bool, S_IRUGO | S_IWUSR);
89MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts");
90
91/**
92 * struct dmatest_params - test parameters.
93 * @buf_size: size of the memcpy test buffer
94 * @channel: bus ID of the channel to test
95 * @device: bus ID of the DMA Engine to test
96 * @threads_per_chan: number of threads to start per channel
97 * @max_channels: maximum number of channels to use
98 * @iterations: iterations before stopping test
99 * @xor_sources: number of xor source buffers
100 * @pq_sources: number of p+q source buffers
101 * @timeout: transfer timeout in msec, -1 for infinite timeout
102 * @noverify: disable data verification
103 * @norandom: disable random offset setup
104 * @alignment: custom data address alignment taken as 2^alignment
105 * @transfer_size: custom transfer size in bytes
106 * @polled: use polling for completion instead of interrupts
107 */
108struct dmatest_params {
109 unsigned int buf_size;
110 char channel[20];
111 char device[32];
112 unsigned int threads_per_chan;
113 unsigned int max_channels;
114 unsigned int iterations;
115 unsigned int xor_sources;
116 unsigned int pq_sources;
117 int timeout;
118 bool noverify;
119 bool norandom;
120 int alignment;
121 unsigned int transfer_size;
122 bool polled;
123};
124
125/**
126 * struct dmatest_info - test information.
127 * @params: test parameters
128 * @channels: channels under test
129 * @nr_channels: number of channels under test
130 * @lock: access protection to the fields of this structure
131 * @did_init: module has been initialized completely
132 */
133static struct dmatest_info {
134 /* Test parameters */
135 struct dmatest_params params;
136
137 /* Internal state */
138 struct list_head channels;
139 unsigned int nr_channels;
140 struct mutex lock;
141 bool did_init;
142} test_info = {
143 .channels = LIST_HEAD_INIT(test_info.channels),
144 .lock = __MUTEX_INITIALIZER(test_info.lock),
145};
146
147static int dmatest_run_set(const char *val, const struct kernel_param *kp);
148static int dmatest_run_get(char *val, const struct kernel_param *kp);
149static const struct kernel_param_ops run_ops = {
150 .set = dmatest_run_set,
151 .get = dmatest_run_get,
152};
153static bool dmatest_run;
154module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
155MODULE_PARM_DESC(run, "Run the test (default: false)");
156
157static int dmatest_chan_set(const char *val, const struct kernel_param *kp);
158static int dmatest_chan_get(char *val, const struct kernel_param *kp);
159static const struct kernel_param_ops multi_chan_ops = {
160 .set = dmatest_chan_set,
161 .get = dmatest_chan_get,
162};
163
164static char test_channel[20];
165static struct kparam_string newchan_kps = {
166 .string = test_channel,
167 .maxlen = 20,
168};
169module_param_cb(channel, &multi_chan_ops, &newchan_kps, 0644);
170MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
171
172static int dmatest_test_list_get(char *val, const struct kernel_param *kp);
173static const struct kernel_param_ops test_list_ops = {
174 .get = dmatest_test_list_get,
175};
176module_param_cb(test_list, &test_list_ops, NULL, 0444);
177MODULE_PARM_DESC(test_list, "Print current test list");
178
179/* Maximum amount of mismatched bytes in buffer to print */
180#define MAX_ERROR_COUNT 32
181
182/*
183 * Initialization patterns. All bytes in the source buffer has bit 7
184 * set, all bytes in the destination buffer has bit 7 cleared.
185 *
186 * Bit 6 is set for all bytes which are to be copied by the DMA
187 * engine. Bit 5 is set for all bytes which are to be overwritten by
188 * the DMA engine.
189 *
190 * The remaining bits are the inverse of a counter which increments by
191 * one for each byte address.
192 */
193#define PATTERN_SRC 0x80
194#define PATTERN_DST 0x00
195#define PATTERN_COPY 0x40
196#define PATTERN_OVERWRITE 0x20
197#define PATTERN_COUNT_MASK 0x1f
198#define PATTERN_MEMSET_IDX 0x01
199
200/* Fixed point arithmetic ops */
201#define FIXPT_SHIFT 8
202#define FIXPNT_MASK 0xFF
203#define FIXPT_TO_INT(a) ((a) >> FIXPT_SHIFT)
204#define INT_TO_FIXPT(a) ((a) << FIXPT_SHIFT)
205#define FIXPT_GET_FRAC(a) ((((a) & FIXPNT_MASK) * 100) >> FIXPT_SHIFT)
206
207/* poor man's completion - we want to use wait_event_freezable() on it */
208struct dmatest_done {
209 bool done;
210 wait_queue_head_t *wait;
211};
212
213struct dmatest_data {
214 u8 **raw;
215 u8 **aligned;
216 unsigned int cnt;
217 unsigned int off;
218};
219
220struct dmatest_thread {
221 struct list_head node;
222 struct dmatest_info *info;
223 struct task_struct *task;
224 struct dma_chan *chan;
225 struct dmatest_data src;
226 struct dmatest_data dst;
227 enum dma_transaction_type type;
228 wait_queue_head_t done_wait;
229 struct dmatest_done test_done;
230 bool done;
231 bool pending;
232};
233
234struct dmatest_chan {
235 struct list_head node;
236 struct dma_chan *chan;
237 struct list_head threads;
238};
239
240static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
241static bool wait;
242
243static bool is_threaded_test_run(struct dmatest_info *info)
244{
245 struct dmatest_chan *dtc;
246
247 list_for_each_entry(dtc, &info->channels, node) {
248 struct dmatest_thread *thread;
249
250 list_for_each_entry(thread, &dtc->threads, node) {
251 if (!thread->done && !thread->pending)
252 return true;
253 }
254 }
255
256 return false;
257}
258
259static bool is_threaded_test_pending(struct dmatest_info *info)
260{
261 struct dmatest_chan *dtc;
262
263 list_for_each_entry(dtc, &info->channels, node) {
264 struct dmatest_thread *thread;
265
266 list_for_each_entry(thread, &dtc->threads, node) {
267 if (thread->pending)
268 return true;
269 }
270 }
271
272 return false;
273}
274
275static int dmatest_wait_get(char *val, const struct kernel_param *kp)
276{
277 struct dmatest_info *info = &test_info;
278 struct dmatest_params *params = &info->params;
279
280 if (params->iterations)
281 wait_event(thread_wait, !is_threaded_test_run(info));
282 wait = true;
283 return param_get_bool(val, kp);
284}
285
286static const struct kernel_param_ops wait_ops = {
287 .get = dmatest_wait_get,
288 .set = param_set_bool,
289};
290module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
291MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
292
293static bool dmatest_match_channel(struct dmatest_params *params,
294 struct dma_chan *chan)
295{
296 if (params->channel[0] == '\0')
297 return true;
298 return strcmp(dma_chan_name(chan), params->channel) == 0;
299}
300
301static bool dmatest_match_device(struct dmatest_params *params,
302 struct dma_device *device)
303{
304 if (params->device[0] == '\0')
305 return true;
306 return strcmp(dev_name(device->dev), params->device) == 0;
307}
308
309static unsigned long dmatest_random(void)
310{
311 unsigned long buf;
312
313 prandom_bytes(&buf, sizeof(buf));
314 return buf;
315}
316
317static inline u8 gen_inv_idx(u8 index, bool is_memset)
318{
319 u8 val = is_memset ? PATTERN_MEMSET_IDX : index;
320
321 return ~val & PATTERN_COUNT_MASK;
322}
323
324static inline u8 gen_src_value(u8 index, bool is_memset)
325{
326 return PATTERN_SRC | gen_inv_idx(index, is_memset);
327}
328
329static inline u8 gen_dst_value(u8 index, bool is_memset)
330{
331 return PATTERN_DST | gen_inv_idx(index, is_memset);
332}
333
334static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
335 unsigned int buf_size, bool is_memset)
336{
337 unsigned int i;
338 u8 *buf;
339
340 for (; (buf = *bufs); bufs++) {
341 for (i = 0; i < start; i++)
342 buf[i] = gen_src_value(i, is_memset);
343 for ( ; i < start + len; i++)
344 buf[i] = gen_src_value(i, is_memset) | PATTERN_COPY;
345 for ( ; i < buf_size; i++)
346 buf[i] = gen_src_value(i, is_memset);
347 buf++;
348 }
349}
350
351static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
352 unsigned int buf_size, bool is_memset)
353{
354 unsigned int i;
355 u8 *buf;
356
357 for (; (buf = *bufs); bufs++) {
358 for (i = 0; i < start; i++)
359 buf[i] = gen_dst_value(i, is_memset);
360 for ( ; i < start + len; i++)
361 buf[i] = gen_dst_value(i, is_memset) |
362 PATTERN_OVERWRITE;
363 for ( ; i < buf_size; i++)
364 buf[i] = gen_dst_value(i, is_memset);
365 }
366}
367
368static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
369 unsigned int counter, bool is_srcbuf, bool is_memset)
370{
371 u8 diff = actual ^ pattern;
372 u8 expected = pattern | gen_inv_idx(counter, is_memset);
373 const char *thread_name = current->comm;
374
375 if (is_srcbuf)
376 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
377 thread_name, index, expected, actual);
378 else if ((pattern & PATTERN_COPY)
379 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
380 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
381 thread_name, index, expected, actual);
382 else if (diff & PATTERN_SRC)
383 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
384 thread_name, index, expected, actual);
385 else
386 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
387 thread_name, index, expected, actual);
388}
389
390static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
391 unsigned int end, unsigned int counter, u8 pattern,
392 bool is_srcbuf, bool is_memset)
393{
394 unsigned int i;
395 unsigned int error_count = 0;
396 u8 actual;
397 u8 expected;
398 u8 *buf;
399 unsigned int counter_orig = counter;
400
401 for (; (buf = *bufs); bufs++) {
402 counter = counter_orig;
403 for (i = start; i < end; i++) {
404 actual = buf[i];
405 expected = pattern | gen_inv_idx(counter, is_memset);
406 if (actual != expected) {
407 if (error_count < MAX_ERROR_COUNT)
408 dmatest_mismatch(actual, pattern, i,
409 counter, is_srcbuf,
410 is_memset);
411 error_count++;
412 }
413 counter++;
414 }
415 }
416
417 if (error_count > MAX_ERROR_COUNT)
418 pr_warn("%s: %u errors suppressed\n",
419 current->comm, error_count - MAX_ERROR_COUNT);
420
421 return error_count;
422}
423
424
425static void dmatest_callback(void *arg)
426{
427 struct dmatest_done *done = arg;
428 struct dmatest_thread *thread =
429 container_of(done, struct dmatest_thread, test_done);
430 if (!thread->done) {
431 done->done = true;
432 wake_up_all(done->wait);
433 } else {
434 /*
435 * If thread->done, it means that this callback occurred
436 * after the parent thread has cleaned up. This can
437 * happen in the case that driver doesn't implement
438 * the terminate_all() functionality and a dma operation
439 * did not occur within the timeout period
440 */
441 WARN(1, "dmatest: Kernel memory may be corrupted!!\n");
442 }
443}
444
445static unsigned int min_odd(unsigned int x, unsigned int y)
446{
447 unsigned int val = min(x, y);
448
449 return val % 2 ? val : val - 1;
450}
451
452static void result(const char *err, unsigned int n, unsigned int src_off,
453 unsigned int dst_off, unsigned int len, unsigned long data)
454{
455 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
456 current->comm, n, err, src_off, dst_off, len, data);
457}
458
459static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
460 unsigned int dst_off, unsigned int len,
461 unsigned long data)
462{
463 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
464 current->comm, n, err, src_off, dst_off, len, data);
465}
466
467#define verbose_result(err, n, src_off, dst_off, len, data) ({ \
468 if (verbose) \
469 result(err, n, src_off, dst_off, len, data); \
470 else \
471 dbg_result(err, n, src_off, dst_off, len, data);\
472})
473
474static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
475{
476 unsigned long long per_sec = 1000000;
477
478 if (runtime <= 0)
479 return 0;
480
481 /* drop precision until runtime is 32-bits */
482 while (runtime > UINT_MAX) {
483 runtime >>= 1;
484 per_sec <<= 1;
485 }
486
487 per_sec *= val;
488 per_sec = INT_TO_FIXPT(per_sec);
489 do_div(per_sec, runtime);
490
491 return per_sec;
492}
493
494static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
495{
496 return FIXPT_TO_INT(dmatest_persec(runtime, len >> 10));
497}
498
499static void __dmatest_free_test_data(struct dmatest_data *d, unsigned int cnt)
500{
501 unsigned int i;
502
503 for (i = 0; i < cnt; i++)
504 kfree(d->raw[i]);
505
506 kfree(d->aligned);
507 kfree(d->raw);
508}
509
510static void dmatest_free_test_data(struct dmatest_data *d)
511{
512 __dmatest_free_test_data(d, d->cnt);
513}
514
515static int dmatest_alloc_test_data(struct dmatest_data *d,
516 unsigned int buf_size, u8 align)
517{
518 unsigned int i = 0;
519
520 d->raw = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
521 if (!d->raw)
522 return -ENOMEM;
523
524 d->aligned = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
525 if (!d->aligned)
526 goto err;
527
528 for (i = 0; i < d->cnt; i++) {
529 d->raw[i] = kmalloc(buf_size + align, GFP_KERNEL);
530 if (!d->raw[i])
531 goto err;
532
533 /* align to alignment restriction */
534 if (align)
535 d->aligned[i] = PTR_ALIGN(d->raw[i], align);
536 else
537 d->aligned[i] = d->raw[i];
538 }
539
540 return 0;
541err:
542 __dmatest_free_test_data(d, i);
543 return -ENOMEM;
544}
545
546/*
547 * This function repeatedly tests DMA transfers of various lengths and
548 * offsets for a given operation type until it is told to exit by
549 * kthread_stop(). There may be multiple threads running this function
550 * in parallel for a single channel, and there may be multiple channels
551 * being tested in parallel.
552 *
553 * Before each test, the source and destination buffer is initialized
554 * with a known pattern. This pattern is different depending on
555 * whether it's in an area which is supposed to be copied or
556 * overwritten, and different in the source and destination buffers.
557 * So if the DMA engine doesn't copy exactly what we tell it to copy,
558 * we'll notice.
559 */
560static int dmatest_func(void *data)
561{
562 struct dmatest_thread *thread = data;
563 struct dmatest_done *done = &thread->test_done;
564 struct dmatest_info *info;
565 struct dmatest_params *params;
566 struct dma_chan *chan;
567 struct dma_device *dev;
568 unsigned int error_count;
569 unsigned int failed_tests = 0;
570 unsigned int total_tests = 0;
571 dma_cookie_t cookie;
572 enum dma_status status;
573 enum dma_ctrl_flags flags;
574 u8 *pq_coefs = NULL;
575 int ret;
576 unsigned int buf_size;
577 struct dmatest_data *src;
578 struct dmatest_data *dst;
579 int i;
580 ktime_t ktime, start, diff;
581 ktime_t filltime = 0;
582 ktime_t comparetime = 0;
583 s64 runtime = 0;
584 unsigned long long total_len = 0;
585 unsigned long long iops = 0;
586 u8 align = 0;
587 bool is_memset = false;
588 dma_addr_t *srcs;
589 dma_addr_t *dma_pq;
590
591 set_freezable();
592
593 ret = -ENOMEM;
594
595 smp_rmb();
596 thread->pending = false;
597 info = thread->info;
598 params = &info->params;
599 chan = thread->chan;
600 dev = chan->device;
601 src = &thread->src;
602 dst = &thread->dst;
603 if (thread->type == DMA_MEMCPY) {
604 align = params->alignment < 0 ? dev->copy_align :
605 params->alignment;
606 src->cnt = dst->cnt = 1;
607 } else if (thread->type == DMA_MEMSET) {
608 align = params->alignment < 0 ? dev->fill_align :
609 params->alignment;
610 src->cnt = dst->cnt = 1;
611 is_memset = true;
612 } else if (thread->type == DMA_XOR) {
613 /* force odd to ensure dst = src */
614 src->cnt = min_odd(params->xor_sources | 1, dev->max_xor);
615 dst->cnt = 1;
616 align = params->alignment < 0 ? dev->xor_align :
617 params->alignment;
618 } else if (thread->type == DMA_PQ) {
619 /* force odd to ensure dst = src */
620 src->cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
621 dst->cnt = 2;
622 align = params->alignment < 0 ? dev->pq_align :
623 params->alignment;
624
625 pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL);
626 if (!pq_coefs)
627 goto err_thread_type;
628
629 for (i = 0; i < src->cnt; i++)
630 pq_coefs[i] = 1;
631 } else
632 goto err_thread_type;
633
634 /* Check if buffer count fits into map count variable (u8) */
635 if ((src->cnt + dst->cnt) >= 255) {
636 pr_err("too many buffers (%d of 255 supported)\n",
637 src->cnt + dst->cnt);
638 goto err_free_coefs;
639 }
640
641 buf_size = params->buf_size;
642 if (1 << align > buf_size) {
643 pr_err("%u-byte buffer too small for %d-byte alignment\n",
644 buf_size, 1 << align);
645 goto err_free_coefs;
646 }
647
648 if (dmatest_alloc_test_data(src, buf_size, align) < 0)
649 goto err_free_coefs;
650
651 if (dmatest_alloc_test_data(dst, buf_size, align) < 0)
652 goto err_src;
653
654 set_user_nice(current, 10);
655
656 srcs = kcalloc(src->cnt, sizeof(dma_addr_t), GFP_KERNEL);
657 if (!srcs)
658 goto err_dst;
659
660 dma_pq = kcalloc(dst->cnt, sizeof(dma_addr_t), GFP_KERNEL);
661 if (!dma_pq)
662 goto err_srcs_array;
663
664 /*
665 * src and dst buffers are freed by ourselves below
666 */
667 if (params->polled)
668 flags = DMA_CTRL_ACK;
669 else
670 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
671
672 ktime = ktime_get();
673 while (!(kthread_should_stop() ||
674 (params->iterations && total_tests >= params->iterations))) {
675 struct dma_async_tx_descriptor *tx = NULL;
676 struct dmaengine_unmap_data *um;
677 dma_addr_t *dsts;
678 unsigned int len;
679
680 total_tests++;
681
682 if (params->transfer_size) {
683 if (params->transfer_size >= buf_size) {
684 pr_err("%u-byte transfer size must be lower than %u-buffer size\n",
685 params->transfer_size, buf_size);
686 break;
687 }
688 len = params->transfer_size;
689 } else if (params->norandom) {
690 len = buf_size;
691 } else {
692 len = dmatest_random() % buf_size + 1;
693 }
694
695 /* Do not alter transfer size explicitly defined by user */
696 if (!params->transfer_size) {
697 len = (len >> align) << align;
698 if (!len)
699 len = 1 << align;
700 }
701 total_len += len;
702
703 if (params->norandom) {
704 src->off = 0;
705 dst->off = 0;
706 } else {
707 src->off = dmatest_random() % (buf_size - len + 1);
708 dst->off = dmatest_random() % (buf_size - len + 1);
709
710 src->off = (src->off >> align) << align;
711 dst->off = (dst->off >> align) << align;
712 }
713
714 if (!params->noverify) {
715 start = ktime_get();
716 dmatest_init_srcs(src->aligned, src->off, len,
717 buf_size, is_memset);
718 dmatest_init_dsts(dst->aligned, dst->off, len,
719 buf_size, is_memset);
720
721 diff = ktime_sub(ktime_get(), start);
722 filltime = ktime_add(filltime, diff);
723 }
724
725 um = dmaengine_get_unmap_data(dev->dev, src->cnt + dst->cnt,
726 GFP_KERNEL);
727 if (!um) {
728 failed_tests++;
729 result("unmap data NULL", total_tests,
730 src->off, dst->off, len, ret);
731 continue;
732 }
733
734 um->len = buf_size;
735 for (i = 0; i < src->cnt; i++) {
736 void *buf = src->aligned[i];
737 struct page *pg = virt_to_page(buf);
738 unsigned long pg_off = offset_in_page(buf);
739
740 um->addr[i] = dma_map_page(dev->dev, pg, pg_off,
741 um->len, DMA_TO_DEVICE);
742 srcs[i] = um->addr[i] + src->off;
743 ret = dma_mapping_error(dev->dev, um->addr[i]);
744 if (ret) {
745 result("src mapping error", total_tests,
746 src->off, dst->off, len, ret);
747 goto error_unmap_continue;
748 }
749 um->to_cnt++;
750 }
751 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
752 dsts = &um->addr[src->cnt];
753 for (i = 0; i < dst->cnt; i++) {
754 void *buf = dst->aligned[i];
755 struct page *pg = virt_to_page(buf);
756 unsigned long pg_off = offset_in_page(buf);
757
758 dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len,
759 DMA_BIDIRECTIONAL);
760 ret = dma_mapping_error(dev->dev, dsts[i]);
761 if (ret) {
762 result("dst mapping error", total_tests,
763 src->off, dst->off, len, ret);
764 goto error_unmap_continue;
765 }
766 um->bidi_cnt++;
767 }
768
769 if (thread->type == DMA_MEMCPY)
770 tx = dev->device_prep_dma_memcpy(chan,
771 dsts[0] + dst->off,
772 srcs[0], len, flags);
773 else if (thread->type == DMA_MEMSET)
774 tx = dev->device_prep_dma_memset(chan,
775 dsts[0] + dst->off,
776 *(src->aligned[0] + src->off),
777 len, flags);
778 else if (thread->type == DMA_XOR)
779 tx = dev->device_prep_dma_xor(chan,
780 dsts[0] + dst->off,
781 srcs, src->cnt,
782 len, flags);
783 else if (thread->type == DMA_PQ) {
784 for (i = 0; i < dst->cnt; i++)
785 dma_pq[i] = dsts[i] + dst->off;
786 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
787 src->cnt, pq_coefs,
788 len, flags);
789 }
790
791 if (!tx) {
792 result("prep error", total_tests, src->off,
793 dst->off, len, ret);
794 msleep(100);
795 goto error_unmap_continue;
796 }
797
798 done->done = false;
799 if (!params->polled) {
800 tx->callback = dmatest_callback;
801 tx->callback_param = done;
802 }
803 cookie = tx->tx_submit(tx);
804
805 if (dma_submit_error(cookie)) {
806 result("submit error", total_tests, src->off,
807 dst->off, len, ret);
808 msleep(100);
809 goto error_unmap_continue;
810 }
811
812 if (params->polled) {
813 status = dma_sync_wait(chan, cookie);
814 dmaengine_terminate_sync(chan);
815 if (status == DMA_COMPLETE)
816 done->done = true;
817 } else {
818 dma_async_issue_pending(chan);
819
820 wait_event_freezable_timeout(thread->done_wait,
821 done->done,
822 msecs_to_jiffies(params->timeout));
823
824 status = dma_async_is_tx_complete(chan, cookie, NULL,
825 NULL);
826 }
827
828 if (!done->done) {
829 result("test timed out", total_tests, src->off, dst->off,
830 len, 0);
831 goto error_unmap_continue;
832 } else if (status != DMA_COMPLETE) {
833 result(status == DMA_ERROR ?
834 "completion error status" :
835 "completion busy status", total_tests, src->off,
836 dst->off, len, ret);
837 goto error_unmap_continue;
838 }
839
840 dmaengine_unmap_put(um);
841
842 if (params->noverify) {
843 verbose_result("test passed", total_tests, src->off,
844 dst->off, len, 0);
845 continue;
846 }
847
848 start = ktime_get();
849 pr_debug("%s: verifying source buffer...\n", current->comm);
850 error_count = dmatest_verify(src->aligned, 0, src->off,
851 0, PATTERN_SRC, true, is_memset);
852 error_count += dmatest_verify(src->aligned, src->off,
853 src->off + len, src->off,
854 PATTERN_SRC | PATTERN_COPY, true, is_memset);
855 error_count += dmatest_verify(src->aligned, src->off + len,
856 buf_size, src->off + len,
857 PATTERN_SRC, true, is_memset);
858
859 pr_debug("%s: verifying dest buffer...\n", current->comm);
860 error_count += dmatest_verify(dst->aligned, 0, dst->off,
861 0, PATTERN_DST, false, is_memset);
862
863 error_count += dmatest_verify(dst->aligned, dst->off,
864 dst->off + len, src->off,
865 PATTERN_SRC | PATTERN_COPY, false, is_memset);
866
867 error_count += dmatest_verify(dst->aligned, dst->off + len,
868 buf_size, dst->off + len,
869 PATTERN_DST, false, is_memset);
870
871 diff = ktime_sub(ktime_get(), start);
872 comparetime = ktime_add(comparetime, diff);
873
874 if (error_count) {
875 result("data error", total_tests, src->off, dst->off,
876 len, error_count);
877 failed_tests++;
878 } else {
879 verbose_result("test passed", total_tests, src->off,
880 dst->off, len, 0);
881 }
882
883 continue;
884
885error_unmap_continue:
886 dmaengine_unmap_put(um);
887 failed_tests++;
888 }
889 ktime = ktime_sub(ktime_get(), ktime);
890 ktime = ktime_sub(ktime, comparetime);
891 ktime = ktime_sub(ktime, filltime);
892 runtime = ktime_to_us(ktime);
893
894 ret = 0;
895 kfree(dma_pq);
896err_srcs_array:
897 kfree(srcs);
898err_dst:
899 dmatest_free_test_data(dst);
900err_src:
901 dmatest_free_test_data(src);
902err_free_coefs:
903 kfree(pq_coefs);
904err_thread_type:
905 iops = dmatest_persec(runtime, total_tests);
906 pr_info("%s: summary %u tests, %u failures %llu.%02llu iops %llu KB/s (%d)\n",
907 current->comm, total_tests, failed_tests,
908 FIXPT_TO_INT(iops), FIXPT_GET_FRAC(iops),
909 dmatest_KBs(runtime, total_len), ret);
910
911 /* terminate all transfers on specified channels */
912 if (ret || failed_tests)
913 dmaengine_terminate_sync(chan);
914
915 thread->done = true;
916 wake_up(&thread_wait);
917
918 return ret;
919}
920
921static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
922{
923 struct dmatest_thread *thread;
924 struct dmatest_thread *_thread;
925 int ret;
926
927 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
928 ret = kthread_stop(thread->task);
929 pr_debug("thread %s exited with status %d\n",
930 thread->task->comm, ret);
931 list_del(&thread->node);
932 put_task_struct(thread->task);
933 kfree(thread);
934 }
935
936 /* terminate all transfers on specified channels */
937 dmaengine_terminate_sync(dtc->chan);
938
939 kfree(dtc);
940}
941
942static int dmatest_add_threads(struct dmatest_info *info,
943 struct dmatest_chan *dtc, enum dma_transaction_type type)
944{
945 struct dmatest_params *params = &info->params;
946 struct dmatest_thread *thread;
947 struct dma_chan *chan = dtc->chan;
948 char *op;
949 unsigned int i;
950
951 if (type == DMA_MEMCPY)
952 op = "copy";
953 else if (type == DMA_MEMSET)
954 op = "set";
955 else if (type == DMA_XOR)
956 op = "xor";
957 else if (type == DMA_PQ)
958 op = "pq";
959 else
960 return -EINVAL;
961
962 for (i = 0; i < params->threads_per_chan; i++) {
963 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
964 if (!thread) {
965 pr_warn("No memory for %s-%s%u\n",
966 dma_chan_name(chan), op, i);
967 break;
968 }
969 thread->info = info;
970 thread->chan = dtc->chan;
971 thread->type = type;
972 thread->test_done.wait = &thread->done_wait;
973 init_waitqueue_head(&thread->done_wait);
974 smp_wmb();
975 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
976 dma_chan_name(chan), op, i);
977 if (IS_ERR(thread->task)) {
978 pr_warn("Failed to create thread %s-%s%u\n",
979 dma_chan_name(chan), op, i);
980 kfree(thread);
981 break;
982 }
983
984 /* srcbuf and dstbuf are allocated by the thread itself */
985 get_task_struct(thread->task);
986 list_add_tail(&thread->node, &dtc->threads);
987 thread->pending = true;
988 }
989
990 return i;
991}
992
993static int dmatest_add_channel(struct dmatest_info *info,
994 struct dma_chan *chan)
995{
996 struct dmatest_chan *dtc;
997 struct dma_device *dma_dev = chan->device;
998 unsigned int thread_count = 0;
999 int cnt;
1000
1001 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
1002 if (!dtc) {
1003 pr_warn("No memory for %s\n", dma_chan_name(chan));
1004 return -ENOMEM;
1005 }
1006
1007 dtc->chan = chan;
1008 INIT_LIST_HEAD(&dtc->threads);
1009
1010 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1011 if (dmatest == 0) {
1012 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
1013 thread_count += cnt > 0 ? cnt : 0;
1014 }
1015 }
1016
1017 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1018 if (dmatest == 1) {
1019 cnt = dmatest_add_threads(info, dtc, DMA_MEMSET);
1020 thread_count += cnt > 0 ? cnt : 0;
1021 }
1022 }
1023
1024 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1025 cnt = dmatest_add_threads(info, dtc, DMA_XOR);
1026 thread_count += cnt > 0 ? cnt : 0;
1027 }
1028 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1029 cnt = dmatest_add_threads(info, dtc, DMA_PQ);
1030 thread_count += cnt > 0 ? cnt : 0;
1031 }
1032
1033 pr_info("Added %u threads using %s\n",
1034 thread_count, dma_chan_name(chan));
1035
1036 list_add_tail(&dtc->node, &info->channels);
1037 info->nr_channels++;
1038
1039 return 0;
1040}
1041
1042static bool filter(struct dma_chan *chan, void *param)
1043{
1044 struct dmatest_params *params = param;
1045
1046 if (!dmatest_match_channel(params, chan) ||
1047 !dmatest_match_device(params, chan->device))
1048 return false;
1049 else
1050 return true;
1051}
1052
1053static void request_channels(struct dmatest_info *info,
1054 enum dma_transaction_type type)
1055{
1056 dma_cap_mask_t mask;
1057
1058 dma_cap_zero(mask);
1059 dma_cap_set(type, mask);
1060 for (;;) {
1061 struct dmatest_params *params = &info->params;
1062 struct dma_chan *chan;
1063
1064 chan = dma_request_channel(mask, filter, params);
1065 if (chan) {
1066 if (dmatest_add_channel(info, chan)) {
1067 dma_release_channel(chan);
1068 break; /* add_channel failed, punt */
1069 }
1070 } else
1071 break; /* no more channels available */
1072 if (params->max_channels &&
1073 info->nr_channels >= params->max_channels)
1074 break; /* we have all we need */
1075 }
1076}
1077
1078static void add_threaded_test(struct dmatest_info *info)
1079{
1080 struct dmatest_params *params = &info->params;
1081
1082 /* Copy test parameters */
1083 params->buf_size = test_buf_size;
1084 strlcpy(params->channel, strim(test_channel), sizeof(params->channel));
1085 strlcpy(params->device, strim(test_device), sizeof(params->device));
1086 params->threads_per_chan = threads_per_chan;
1087 params->max_channels = max_channels;
1088 params->iterations = iterations;
1089 params->xor_sources = xor_sources;
1090 params->pq_sources = pq_sources;
1091 params->timeout = timeout;
1092 params->noverify = noverify;
1093 params->norandom = norandom;
1094 params->alignment = alignment;
1095 params->transfer_size = transfer_size;
1096 params->polled = polled;
1097
1098 request_channels(info, DMA_MEMCPY);
1099 request_channels(info, DMA_MEMSET);
1100 request_channels(info, DMA_XOR);
1101 request_channels(info, DMA_PQ);
1102}
1103
1104static void run_pending_tests(struct dmatest_info *info)
1105{
1106 struct dmatest_chan *dtc;
1107 unsigned int thread_count = 0;
1108
1109 list_for_each_entry(dtc, &info->channels, node) {
1110 struct dmatest_thread *thread;
1111
1112 thread_count = 0;
1113 list_for_each_entry(thread, &dtc->threads, node) {
1114 wake_up_process(thread->task);
1115 thread_count++;
1116 }
1117 pr_info("Started %u threads using %s\n",
1118 thread_count, dma_chan_name(dtc->chan));
1119 }
1120}
1121
1122static void stop_threaded_test(struct dmatest_info *info)
1123{
1124 struct dmatest_chan *dtc, *_dtc;
1125 struct dma_chan *chan;
1126
1127 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
1128 list_del(&dtc->node);
1129 chan = dtc->chan;
1130 dmatest_cleanup_channel(dtc);
1131 pr_debug("dropped channel %s\n", dma_chan_name(chan));
1132 dma_release_channel(chan);
1133 }
1134
1135 info->nr_channels = 0;
1136}
1137
1138static void start_threaded_tests(struct dmatest_info *info)
1139{
1140 /* we might be called early to set run=, defer running until all
1141 * parameters have been evaluated
1142 */
1143 if (!info->did_init)
1144 return;
1145
1146 run_pending_tests(info);
1147}
1148
1149static int dmatest_run_get(char *val, const struct kernel_param *kp)
1150{
1151 struct dmatest_info *info = &test_info;
1152
1153 mutex_lock(&info->lock);
1154 if (is_threaded_test_run(info)) {
1155 dmatest_run = true;
1156 } else {
1157 if (!is_threaded_test_pending(info))
1158 stop_threaded_test(info);
1159 dmatest_run = false;
1160 }
1161 mutex_unlock(&info->lock);
1162
1163 return param_get_bool(val, kp);
1164}
1165
1166static int dmatest_run_set(const char *val, const struct kernel_param *kp)
1167{
1168 struct dmatest_info *info = &test_info;
1169 int ret;
1170
1171 mutex_lock(&info->lock);
1172 ret = param_set_bool(val, kp);
1173 if (ret) {
1174 mutex_unlock(&info->lock);
1175 return ret;
1176 } else if (dmatest_run) {
1177 if (!is_threaded_test_pending(info)) {
1178 pr_info("No channels configured, continue with any\n");
1179 if (!is_threaded_test_run(info))
1180 stop_threaded_test(info);
1181 add_threaded_test(info);
1182 }
1183 start_threaded_tests(info);
1184 } else {
1185 stop_threaded_test(info);
1186 }
1187
1188 mutex_unlock(&info->lock);
1189
1190 return ret;
1191}
1192
1193static int dmatest_chan_set(const char *val, const struct kernel_param *kp)
1194{
1195 struct dmatest_info *info = &test_info;
1196 struct dmatest_chan *dtc;
1197 char chan_reset_val[20];
1198 int ret = 0;
1199
1200 mutex_lock(&info->lock);
1201 ret = param_set_copystring(val, kp);
1202 if (ret) {
1203 mutex_unlock(&info->lock);
1204 return ret;
1205 }
1206 /*Clear any previously run threads */
1207 if (!is_threaded_test_run(info) && !is_threaded_test_pending(info))
1208 stop_threaded_test(info);
1209 /* Reject channels that are already registered */
1210 if (is_threaded_test_pending(info)) {
1211 list_for_each_entry(dtc, &info->channels, node) {
1212 if (strcmp(dma_chan_name(dtc->chan),
1213 strim(test_channel)) == 0) {
1214 dtc = list_last_entry(&info->channels,
1215 struct dmatest_chan,
1216 node);
1217 strlcpy(chan_reset_val,
1218 dma_chan_name(dtc->chan),
1219 sizeof(chan_reset_val));
1220 ret = -EBUSY;
1221 goto add_chan_err;
1222 }
1223 }
1224 }
1225
1226 add_threaded_test(info);
1227
1228 /* Check if channel was added successfully */
1229 dtc = list_last_entry(&info->channels, struct dmatest_chan, node);
1230
1231 if (dtc->chan) {
1232 /*
1233 * if new channel was not successfully added, revert the
1234 * "test_channel" string to the name of the last successfully
1235 * added channel. exception for when users issues empty string
1236 * to channel parameter.
1237 */
1238 if ((strcmp(dma_chan_name(dtc->chan), strim(test_channel)) != 0)
1239 && (strcmp("", strim(test_channel)) != 0)) {
1240 ret = -EINVAL;
1241 strlcpy(chan_reset_val, dma_chan_name(dtc->chan),
1242 sizeof(chan_reset_val));
1243 goto add_chan_err;
1244 }
1245
1246 } else {
1247 /* Clear test_channel if no channels were added successfully */
1248 strlcpy(chan_reset_val, "", sizeof(chan_reset_val));
1249 ret = -EBUSY;
1250 goto add_chan_err;
1251 }
1252
1253 mutex_unlock(&info->lock);
1254
1255 return ret;
1256
1257add_chan_err:
1258 param_set_copystring(chan_reset_val, kp);
1259 mutex_unlock(&info->lock);
1260
1261 return ret;
1262}
1263
1264static int dmatest_chan_get(char *val, const struct kernel_param *kp)
1265{
1266 struct dmatest_info *info = &test_info;
1267
1268 mutex_lock(&info->lock);
1269 if (!is_threaded_test_run(info) && !is_threaded_test_pending(info)) {
1270 stop_threaded_test(info);
1271 strlcpy(test_channel, "", sizeof(test_channel));
1272 }
1273 mutex_unlock(&info->lock);
1274
1275 return param_get_string(val, kp);
1276}
1277
1278static int dmatest_test_list_get(char *val, const struct kernel_param *kp)
1279{
1280 struct dmatest_info *info = &test_info;
1281 struct dmatest_chan *dtc;
1282 unsigned int thread_count = 0;
1283
1284 list_for_each_entry(dtc, &info->channels, node) {
1285 struct dmatest_thread *thread;
1286
1287 thread_count = 0;
1288 list_for_each_entry(thread, &dtc->threads, node) {
1289 thread_count++;
1290 }
1291 pr_info("%u threads using %s\n",
1292 thread_count, dma_chan_name(dtc->chan));
1293 }
1294
1295 return 0;
1296}
1297
1298static int __init dmatest_init(void)
1299{
1300 struct dmatest_info *info = &test_info;
1301 struct dmatest_params *params = &info->params;
1302
1303 if (dmatest_run) {
1304 mutex_lock(&info->lock);
1305 add_threaded_test(info);
1306 run_pending_tests(info);
1307 mutex_unlock(&info->lock);
1308 }
1309
1310 if (params->iterations && wait)
1311 wait_event(thread_wait, !is_threaded_test_run(info));
1312
1313 /* module parameters are stable, inittime tests are started,
1314 * let userspace take over 'run' control
1315 */
1316 info->did_init = true;
1317
1318 return 0;
1319}
1320/* when compiled-in wait for drivers to load first */
1321late_initcall(dmatest_init);
1322
1323static void __exit dmatest_exit(void)
1324{
1325 struct dmatest_info *info = &test_info;
1326
1327 mutex_lock(&info->lock);
1328 stop_threaded_test(info);
1329 mutex_unlock(&info->lock);
1330}
1331module_exit(dmatest_exit);
1332
1333MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1334MODULE_LICENSE("GPL v2");