tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM architected timer
8
9maintainers:
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
12description: |+
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
15 physical and optional virtual timer per frame.
16
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
19 to deliver its interrupts via SPIs.
20
21properties:
22 compatible:
23 oneOf:
24 - items:
25 - enum:
26 - arm,cortex-a15-timer
27 - enum:
28 - arm,armv7-timer
29 - items:
30 - enum:
31 - arm,armv7-timer
32 - items:
33 - enum:
34 - arm,armv8-timer
35
36 interrupts:
37 items:
38 - description: secure timer irq
39 - description: non-secure timer irq
40 - description: virtual timer irq
41 - description: hypervisor timer irq
42
43 clock-frequency:
44 description: The frequency of the main counter, in Hz. Should be present
45 only where necessary to work around broken firmware which does not configure
46 CNTFRQ on all CPUs to a uniform correct value. Use of this property is
47 strongly discouraged; fix your firmware unless absolutely impossible.
48
49 always-on:
50 type: boolean
51 description: If present, the timer is powered through an always-on power
52 domain, therefore it never loses context.
53
54 allwinner,erratum-unknown1:
55 type: boolean
56 description: Indicates the presence of an erratum found in Allwinner SoCs,
57 where reading certain values from the counter is unreliable. This also
58 affects writes to the tval register, due to the implicit counter read.
59
60 fsl,erratum-a008585:
61 type: boolean
62 description: Indicates the presence of QorIQ erratum A-008585, which says
63 that reading the counter is unreliable unless the same value is returned
64 by back-to-back reads. This also affects writes to the tval register, due
65 to the implicit counter read.
66
67 hisilicon,erratum-161010101:
68 type: boolean
69 description: Indicates the presence of Hisilicon erratum 161010101, which
70 says that reading the counters is unreliable in some cases, and reads may
71 return a value 32 beyond the correct value. This also affects writes to
72 the tval registers, due to the implicit counter read.
73
74 arm,cpu-registers-not-fw-configured:
75 type: boolean
76 description: Firmware does not initialize any of the generic timer CPU
77 registers, which contain their architecturally-defined reset values. Only
78 supported for 32-bit systems which follow the ARMv7 architected reset
79 values.
80
81 arm,no-tick-in-suspend:
82 type: boolean
83 description: The main counter does not tick when the system is in
84 low-power system suspend on some SoCs. This behavior does not match the
85 Architecture Reference Manual's specification that the system counter "must
86 be implemented in an always-on power domain."
87
88required:
89 - compatible
90
91additionalProperties: false
92
93oneOf:
94 - required:
95 - interrupts
96 - required:
97 - interrupts-extended
98
99examples:
100 - |
101 timer {
102 compatible = "arm,cortex-a15-timer",
103 "arm,armv7-timer";
104 interrupts = <1 13 0xf08>,
105 <1 14 0xf08>,
106 <1 11 0xf08>,
107 <1 10 0xf08>;
108 clock-frequency = <100000000>;
109 };
110
111...