tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2010 Matt Turner.
4 * Copyright 2012 Red Hat
5 *
6 * Authors: Matthew Garrett
7 * Matt Turner
8 * Dave Airlie
9 */
10
11#include <linux/delay.h>
12#include <linux/pci.h>
13
14#include <drm/drm_crtc_helper.h>
15#include <drm/drm_fourcc.h>
16#include <drm/drm_gem_framebuffer_helper.h>
17#include <drm/drm_plane_helper.h>
18#include <drm/drm_probe_helper.h>
19#include <drm/drm_simple_kms_helper.h>
20
21#include "mgag200_drv.h"
22
23#define MGAG200_LUT_SIZE 256
24
25/*
26 * This file contains setup code for the CRTC.
27 */
28
29static void mga_crtc_load_lut(struct drm_crtc *crtc)
30{
31 struct drm_device *dev = crtc->dev;
32 struct mga_device *mdev = to_mga_device(dev);
33 struct drm_framebuffer *fb = crtc->primary->fb;
34 u16 *r_ptr, *g_ptr, *b_ptr;
35 int i;
36
37 if (!crtc->enabled)
38 return;
39
40 r_ptr = crtc->gamma_store;
41 g_ptr = r_ptr + crtc->gamma_size;
42 b_ptr = g_ptr + crtc->gamma_size;
43
44 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
45
46 if (fb && fb->format->cpp[0] * 8 == 16) {
47 int inc = (fb->format->depth == 15) ? 8 : 4;
48 u8 r, b;
49 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
50 if (fb->format->depth == 16) {
51 if (i > (MGAG200_LUT_SIZE >> 1)) {
52 r = b = 0;
53 } else {
54 r = *r_ptr++ >> 8;
55 b = *b_ptr++ >> 8;
56 r_ptr++;
57 b_ptr++;
58 }
59 } else {
60 r = *r_ptr++ >> 8;
61 b = *b_ptr++ >> 8;
62 }
63 /* VGA registers */
64 WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
65 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
66 WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
67 }
68 return;
69 }
70 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
71 /* VGA registers */
72 WREG8(DAC_INDEX + MGA1064_COL_PAL, *r_ptr++ >> 8);
73 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
74 WREG8(DAC_INDEX + MGA1064_COL_PAL, *b_ptr++ >> 8);
75 }
76}
77
78static inline void mga_wait_vsync(struct mga_device *mdev)
79{
80 unsigned long timeout = jiffies + HZ/10;
81 unsigned int status = 0;
82
83 do {
84 status = RREG32(MGAREG_Status);
85 } while ((status & 0x08) && time_before(jiffies, timeout));
86 timeout = jiffies + HZ/10;
87 status = 0;
88 do {
89 status = RREG32(MGAREG_Status);
90 } while (!(status & 0x08) && time_before(jiffies, timeout));
91}
92
93static inline void mga_wait_busy(struct mga_device *mdev)
94{
95 unsigned long timeout = jiffies + HZ;
96 unsigned int status = 0;
97 do {
98 status = RREG8(MGAREG_Status + 2);
99 } while ((status & 0x01) && time_before(jiffies, timeout));
100}
101
102#define P_ARRAY_SIZE 9
103
104static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
105{
106 unsigned int vcomax, vcomin, pllreffreq;
107 unsigned int delta, tmpdelta, permitteddelta;
108 unsigned int testp, testm, testn;
109 unsigned int p, m, n;
110 unsigned int computed;
111 unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
112 unsigned int fvv;
113 unsigned int i;
114
115 if (mdev->unique_rev_id <= 0x03) {
116
117 m = n = p = 0;
118 vcomax = 320000;
119 vcomin = 160000;
120 pllreffreq = 25000;
121
122 delta = 0xffffffff;
123 permitteddelta = clock * 5 / 1000;
124
125 for (testp = 8; testp > 0; testp /= 2) {
126 if (clock * testp > vcomax)
127 continue;
128 if (clock * testp < vcomin)
129 continue;
130
131 for (testn = 17; testn < 256; testn++) {
132 for (testm = 1; testm < 32; testm++) {
133 computed = (pllreffreq * testn) /
134 (testm * testp);
135 if (computed > clock)
136 tmpdelta = computed - clock;
137 else
138 tmpdelta = clock - computed;
139 if (tmpdelta < delta) {
140 delta = tmpdelta;
141 m = testm - 1;
142 n = testn - 1;
143 p = testp - 1;
144 }
145 }
146 }
147 }
148 } else {
149
150
151 m = n = p = 0;
152 vcomax = 1600000;
153 vcomin = 800000;
154 pllreffreq = 25000;
155
156 if (clock < 25000)
157 clock = 25000;
158
159 clock = clock * 2;
160
161 delta = 0xFFFFFFFF;
162 /* Permited delta is 0.5% as VESA Specification */
163 permitteddelta = clock * 5 / 1000;
164
165 for (i = 0 ; i < P_ARRAY_SIZE ; i++) {
166 testp = pvalues_e4[i];
167
168 if ((clock * testp) > vcomax)
169 continue;
170 if ((clock * testp) < vcomin)
171 continue;
172
173 for (testn = 50; testn <= 256; testn++) {
174 for (testm = 1; testm <= 32; testm++) {
175 computed = (pllreffreq * testn) /
176 (testm * testp);
177 if (computed > clock)
178 tmpdelta = computed - clock;
179 else
180 tmpdelta = clock - computed;
181
182 if (tmpdelta < delta) {
183 delta = tmpdelta;
184 m = testm - 1;
185 n = testn - 1;
186 p = testp - 1;
187 }
188 }
189 }
190 }
191
192 fvv = pllreffreq * (n + 1) / (m + 1);
193 fvv = (fvv - 800000) / 50000;
194
195 if (fvv > 15)
196 fvv = 15;
197
198 p |= (fvv << 4);
199 m |= 0x80;
200
201 clock = clock / 2;
202 }
203
204 if (delta > permitteddelta) {
205 pr_warn("PLL delta too large\n");
206 return 1;
207 }
208
209 WREG_DAC(MGA1064_PIX_PLLC_M, m);
210 WREG_DAC(MGA1064_PIX_PLLC_N, n);
211 WREG_DAC(MGA1064_PIX_PLLC_P, p);
212
213 if (mdev->unique_rev_id >= 0x04) {
214 WREG_DAC(0x1a, 0x09);
215 msleep(20);
216 WREG_DAC(0x1a, 0x01);
217
218 }
219
220 return 0;
221}
222
223static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
224{
225 unsigned int vcomax, vcomin, pllreffreq;
226 unsigned int delta, tmpdelta;
227 unsigned int testp, testm, testn, testp2;
228 unsigned int p, m, n;
229 unsigned int computed;
230 int i, j, tmpcount, vcount;
231 bool pll_locked = false;
232 u8 tmp;
233
234 m = n = p = 0;
235
236 delta = 0xffffffff;
237
238 if (mdev->type == G200_EW3) {
239
240 vcomax = 800000;
241 vcomin = 400000;
242 pllreffreq = 25000;
243
244 for (testp = 1; testp < 8; testp++) {
245 for (testp2 = 1; testp2 < 8; testp2++) {
246 if (testp < testp2)
247 continue;
248 if ((clock * testp * testp2) > vcomax)
249 continue;
250 if ((clock * testp * testp2) < vcomin)
251 continue;
252 for (testm = 1; testm < 26; testm++) {
253 for (testn = 32; testn < 2048 ; testn++) {
254 computed = (pllreffreq * testn) /
255 (testm * testp * testp2);
256 if (computed > clock)
257 tmpdelta = computed - clock;
258 else
259 tmpdelta = clock - computed;
260 if (tmpdelta < delta) {
261 delta = tmpdelta;
262 m = ((testn & 0x100) >> 1) |
263 (testm);
264 n = (testn & 0xFF);
265 p = ((testn & 0x600) >> 3) |
266 (testp2 << 3) |
267 (testp);
268 }
269 }
270 }
271 }
272 }
273 } else {
274
275 vcomax = 550000;
276 vcomin = 150000;
277 pllreffreq = 48000;
278
279 for (testp = 1; testp < 9; testp++) {
280 if (clock * testp > vcomax)
281 continue;
282 if (clock * testp < vcomin)
283 continue;
284
285 for (testm = 1; testm < 17; testm++) {
286 for (testn = 1; testn < 151; testn++) {
287 computed = (pllreffreq * testn) /
288 (testm * testp);
289 if (computed > clock)
290 tmpdelta = computed - clock;
291 else
292 tmpdelta = clock - computed;
293 if (tmpdelta < delta) {
294 delta = tmpdelta;
295 n = testn - 1;
296 m = (testm - 1) |
297 ((n >> 1) & 0x80);
298 p = testp - 1;
299 }
300 }
301 }
302 }
303 }
304
305 for (i = 0; i <= 32 && pll_locked == false; i++) {
306 if (i > 0) {
307 WREG8(MGAREG_CRTC_INDEX, 0x1e);
308 tmp = RREG8(MGAREG_CRTC_DATA);
309 if (tmp < 0xff)
310 WREG8(MGAREG_CRTC_DATA, tmp+1);
311 }
312
313 /* set pixclkdis to 1 */
314 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
315 tmp = RREG8(DAC_DATA);
316 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
317 WREG8(DAC_DATA, tmp);
318
319 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
320 tmp = RREG8(DAC_DATA);
321 tmp |= MGA1064_REMHEADCTL_CLKDIS;
322 WREG8(DAC_DATA, tmp);
323
324 /* select PLL Set C */
325 tmp = RREG8(MGAREG_MEM_MISC_READ);
326 tmp |= 0x3 << 2;
327 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
328
329 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
330 tmp = RREG8(DAC_DATA);
331 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
332 WREG8(DAC_DATA, tmp);
333
334 udelay(500);
335
336 /* reset the PLL */
337 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
338 tmp = RREG8(DAC_DATA);
339 tmp &= ~0x04;
340 WREG8(DAC_DATA, tmp);
341
342 udelay(50);
343
344 /* program pixel pll register */
345 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
346 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
347 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
348
349 udelay(50);
350
351 /* turn pll on */
352 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
353 tmp = RREG8(DAC_DATA);
354 tmp |= 0x04;
355 WREG_DAC(MGA1064_VREF_CTL, tmp);
356
357 udelay(500);
358
359 /* select the pixel pll */
360 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
361 tmp = RREG8(DAC_DATA);
362 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
363 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
364 WREG8(DAC_DATA, tmp);
365
366 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
367 tmp = RREG8(DAC_DATA);
368 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
369 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
370 WREG8(DAC_DATA, tmp);
371
372 /* reset dotclock rate bit */
373 WREG8(MGAREG_SEQ_INDEX, 1);
374 tmp = RREG8(MGAREG_SEQ_DATA);
375 tmp &= ~0x8;
376 WREG8(MGAREG_SEQ_DATA, tmp);
377
378 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
379 tmp = RREG8(DAC_DATA);
380 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
381 WREG8(DAC_DATA, tmp);
382
383 vcount = RREG8(MGAREG_VCOUNT);
384
385 for (j = 0; j < 30 && pll_locked == false; j++) {
386 tmpcount = RREG8(MGAREG_VCOUNT);
387 if (tmpcount < vcount)
388 vcount = 0;
389 if ((tmpcount - vcount) > 2)
390 pll_locked = true;
391 else
392 udelay(5);
393 }
394 }
395 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
396 tmp = RREG8(DAC_DATA);
397 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
398 WREG_DAC(MGA1064_REMHEADCTL, tmp);
399 return 0;
400}
401
402static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
403{
404 unsigned int vcomax, vcomin, pllreffreq;
405 unsigned int delta, tmpdelta;
406 unsigned int testp, testm, testn;
407 unsigned int p, m, n;
408 unsigned int computed;
409 u8 tmp;
410
411 m = n = p = 0;
412 vcomax = 550000;
413 vcomin = 150000;
414 pllreffreq = 50000;
415
416 delta = 0xffffffff;
417
418 for (testp = 16; testp > 0; testp--) {
419 if (clock * testp > vcomax)
420 continue;
421 if (clock * testp < vcomin)
422 continue;
423
424 for (testn = 1; testn < 257; testn++) {
425 for (testm = 1; testm < 17; testm++) {
426 computed = (pllreffreq * testn) /
427 (testm * testp);
428 if (computed > clock)
429 tmpdelta = computed - clock;
430 else
431 tmpdelta = clock - computed;
432 if (tmpdelta < delta) {
433 delta = tmpdelta;
434 n = testn - 1;
435 m = testm - 1;
436 p = testp - 1;
437 }
438 }
439 }
440 }
441
442 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
443 tmp = RREG8(DAC_DATA);
444 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
445 WREG8(DAC_DATA, tmp);
446
447 tmp = RREG8(MGAREG_MEM_MISC_READ);
448 tmp |= 0x3 << 2;
449 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
450
451 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
452 tmp = RREG8(DAC_DATA);
453 WREG8(DAC_DATA, tmp & ~0x40);
454
455 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
456 tmp = RREG8(DAC_DATA);
457 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
458 WREG8(DAC_DATA, tmp);
459
460 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
461 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
462 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
463
464 udelay(50);
465
466 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
467 tmp = RREG8(DAC_DATA);
468 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
469 WREG8(DAC_DATA, tmp);
470
471 udelay(500);
472
473 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
474 tmp = RREG8(DAC_DATA);
475 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
476 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
477 WREG8(DAC_DATA, tmp);
478
479 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
480 tmp = RREG8(DAC_DATA);
481 WREG8(DAC_DATA, tmp | 0x40);
482
483 tmp = RREG8(MGAREG_MEM_MISC_READ);
484 tmp |= (0x3 << 2);
485 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
486
487 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
488 tmp = RREG8(DAC_DATA);
489 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
490 WREG8(DAC_DATA, tmp);
491
492 return 0;
493}
494
495static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
496{
497 unsigned int vcomax, vcomin, pllreffreq;
498 unsigned int delta, tmpdelta;
499 unsigned int testp, testm, testn;
500 unsigned int p, m, n;
501 unsigned int computed;
502 int i, j, tmpcount, vcount;
503 u8 tmp;
504 bool pll_locked = false;
505
506 m = n = p = 0;
507
508 if (mdev->type == G200_EH3) {
509 vcomax = 3000000;
510 vcomin = 1500000;
511 pllreffreq = 25000;
512
513 delta = 0xffffffff;
514
515 testp = 0;
516
517 for (testm = 150; testm >= 6; testm--) {
518 if (clock * testm > vcomax)
519 continue;
520 if (clock * testm < vcomin)
521 continue;
522 for (testn = 120; testn >= 60; testn--) {
523 computed = (pllreffreq * testn) / testm;
524 if (computed > clock)
525 tmpdelta = computed - clock;
526 else
527 tmpdelta = clock - computed;
528 if (tmpdelta < delta) {
529 delta = tmpdelta;
530 n = testn;
531 m = testm;
532 p = testp;
533 }
534 if (delta == 0)
535 break;
536 }
537 if (delta == 0)
538 break;
539 }
540 } else {
541
542 vcomax = 800000;
543 vcomin = 400000;
544 pllreffreq = 33333;
545
546 delta = 0xffffffff;
547
548 for (testp = 16; testp > 0; testp >>= 1) {
549 if (clock * testp > vcomax)
550 continue;
551 if (clock * testp < vcomin)
552 continue;
553
554 for (testm = 1; testm < 33; testm++) {
555 for (testn = 17; testn < 257; testn++) {
556 computed = (pllreffreq * testn) /
557 (testm * testp);
558 if (computed > clock)
559 tmpdelta = computed - clock;
560 else
561 tmpdelta = clock - computed;
562 if (tmpdelta < delta) {
563 delta = tmpdelta;
564 n = testn - 1;
565 m = (testm - 1);
566 p = testp - 1;
567 }
568 if ((clock * testp) >= 600000)
569 p |= 0x80;
570 }
571 }
572 }
573 }
574 for (i = 0; i <= 32 && pll_locked == false; i++) {
575 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
576 tmp = RREG8(DAC_DATA);
577 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
578 WREG8(DAC_DATA, tmp);
579
580 tmp = RREG8(MGAREG_MEM_MISC_READ);
581 tmp |= 0x3 << 2;
582 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
583
584 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
585 tmp = RREG8(DAC_DATA);
586 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
587 WREG8(DAC_DATA, tmp);
588
589 udelay(500);
590
591 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
592 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
593 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
594
595 udelay(500);
596
597 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
598 tmp = RREG8(DAC_DATA);
599 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
600 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
601 WREG8(DAC_DATA, tmp);
602
603 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
604 tmp = RREG8(DAC_DATA);
605 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
606 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
607 WREG8(DAC_DATA, tmp);
608
609 vcount = RREG8(MGAREG_VCOUNT);
610
611 for (j = 0; j < 30 && pll_locked == false; j++) {
612 tmpcount = RREG8(MGAREG_VCOUNT);
613 if (tmpcount < vcount)
614 vcount = 0;
615 if ((tmpcount - vcount) > 2)
616 pll_locked = true;
617 else
618 udelay(5);
619 }
620 }
621
622 return 0;
623}
624
625static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
626{
627 unsigned int vcomax, vcomin, pllreffreq;
628 unsigned int delta, tmpdelta;
629 int testr, testn, testm, testo;
630 unsigned int p, m, n;
631 unsigned int computed, vco;
632 int tmp;
633 const unsigned int m_div_val[] = { 1, 2, 4, 8 };
634
635 m = n = p = 0;
636 vcomax = 1488000;
637 vcomin = 1056000;
638 pllreffreq = 48000;
639
640 delta = 0xffffffff;
641
642 for (testr = 0; testr < 4; testr++) {
643 if (delta == 0)
644 break;
645 for (testn = 5; testn < 129; testn++) {
646 if (delta == 0)
647 break;
648 for (testm = 3; testm >= 0; testm--) {
649 if (delta == 0)
650 break;
651 for (testo = 5; testo < 33; testo++) {
652 vco = pllreffreq * (testn + 1) /
653 (testr + 1);
654 if (vco < vcomin)
655 continue;
656 if (vco > vcomax)
657 continue;
658 computed = vco / (m_div_val[testm] * (testo + 1));
659 if (computed > clock)
660 tmpdelta = computed - clock;
661 else
662 tmpdelta = clock - computed;
663 if (tmpdelta < delta) {
664 delta = tmpdelta;
665 m = testm | (testo << 3);
666 n = testn;
667 p = testr | (testr << 3);
668 }
669 }
670 }
671 }
672 }
673
674 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
675 tmp = RREG8(DAC_DATA);
676 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
677 WREG8(DAC_DATA, tmp);
678
679 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
680 tmp = RREG8(DAC_DATA);
681 tmp |= MGA1064_REMHEADCTL_CLKDIS;
682 WREG8(DAC_DATA, tmp);
683
684 tmp = RREG8(MGAREG_MEM_MISC_READ);
685 tmp |= (0x3<<2) | 0xc0;
686 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
687
688 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
689 tmp = RREG8(DAC_DATA);
690 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
691 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
692 WREG8(DAC_DATA, tmp);
693
694 udelay(500);
695
696 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
697 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
698 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
699
700 udelay(50);
701
702 return 0;
703}
704
705static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
706{
707 switch(mdev->type) {
708 case G200_SE_A:
709 case G200_SE_B:
710 return mga_g200se_set_plls(mdev, clock);
711 break;
712 case G200_WB:
713 case G200_EW3:
714 return mga_g200wb_set_plls(mdev, clock);
715 break;
716 case G200_EV:
717 return mga_g200ev_set_plls(mdev, clock);
718 break;
719 case G200_EH:
720 case G200_EH3:
721 return mga_g200eh_set_plls(mdev, clock);
722 break;
723 case G200_ER:
724 return mga_g200er_set_plls(mdev, clock);
725 break;
726 }
727 return 0;
728}
729
730static void mga_g200wb_prepare(struct drm_crtc *crtc)
731{
732 struct mga_device *mdev = to_mga_device(crtc->dev);
733 u8 tmp;
734 int iter_max;
735
736 /* 1- The first step is to warn the BMC of an upcoming mode change.
737 * We are putting the misc<0> to output.*/
738
739 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
740 tmp = RREG8(DAC_DATA);
741 tmp |= 0x10;
742 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
743
744 /* we are putting a 1 on the misc<0> line */
745 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
746 tmp = RREG8(DAC_DATA);
747 tmp |= 0x10;
748 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
749
750 /* 2- Second step to mask and further scan request
751 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
752 */
753 WREG8(DAC_INDEX, MGA1064_SPAREREG);
754 tmp = RREG8(DAC_DATA);
755 tmp |= 0x80;
756 WREG_DAC(MGA1064_SPAREREG, tmp);
757
758 /* 3a- the third step is to verifu if there is an active scan
759 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
760 */
761 iter_max = 300;
762 while (!(tmp & 0x1) && iter_max) {
763 WREG8(DAC_INDEX, MGA1064_SPAREREG);
764 tmp = RREG8(DAC_DATA);
765 udelay(1000);
766 iter_max--;
767 }
768
769 /* 3b- this step occurs only if the remove is actually scanning
770 * we are waiting for the end of the frame which is a 1 on
771 * remvsyncsts (XSPAREREG<1>)
772 */
773 if (iter_max) {
774 iter_max = 300;
775 while ((tmp & 0x2) && iter_max) {
776 WREG8(DAC_INDEX, MGA1064_SPAREREG);
777 tmp = RREG8(DAC_DATA);
778 udelay(1000);
779 iter_max--;
780 }
781 }
782}
783
784static void mga_g200wb_commit(struct drm_crtc *crtc)
785{
786 u8 tmp;
787 struct mga_device *mdev = to_mga_device(crtc->dev);
788
789 /* 1- The first step is to ensure that the vrsten and hrsten are set */
790 WREG8(MGAREG_CRTCEXT_INDEX, 1);
791 tmp = RREG8(MGAREG_CRTCEXT_DATA);
792 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
793
794 /* 2- second step is to assert the rstlvl2 */
795 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
796 tmp = RREG8(DAC_DATA);
797 tmp |= 0x8;
798 WREG8(DAC_DATA, tmp);
799
800 /* wait 10 us */
801 udelay(10);
802
803 /* 3- deassert rstlvl2 */
804 tmp &= ~0x08;
805 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
806 WREG8(DAC_DATA, tmp);
807
808 /* 4- remove mask of scan request */
809 WREG8(DAC_INDEX, MGA1064_SPAREREG);
810 tmp = RREG8(DAC_DATA);
811 tmp &= ~0x80;
812 WREG8(DAC_DATA, tmp);
813
814 /* 5- put back a 0 on the misc<0> line */
815 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
816 tmp = RREG8(DAC_DATA);
817 tmp &= ~0x10;
818 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
819}
820
821/*
822 This is how the framebuffer base address is stored in g200 cards:
823 * Assume @offset is the gpu_addr variable of the framebuffer object
824 * Then addr is the number of _pixels_ (not bytes) from the start of
825 VRAM to the first pixel we want to display. (divided by 2 for 32bit
826 framebuffers)
827 * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
828 addr<20> -> CRTCEXT0<6>
829 addr<19-16> -> CRTCEXT0<3-0>
830 addr<15-8> -> CRTCC<7-0>
831 addr<7-0> -> CRTCD<7-0>
832 CRTCEXT0 has to be programmed last to trigger an update and make the
833 new addr variable take effect.
834 */
835static void mga_set_start_address(struct drm_crtc *crtc, unsigned offset)
836{
837 struct mga_device *mdev = to_mga_device(crtc->dev);
838 u32 addr;
839 int count;
840 u8 crtcext0;
841
842 while (RREG8(0x1fda) & 0x08);
843 while (!(RREG8(0x1fda) & 0x08));
844
845 count = RREG8(MGAREG_VCOUNT) + 2;
846 while (RREG8(MGAREG_VCOUNT) < count);
847
848 WREG8(MGAREG_CRTCEXT_INDEX, 0);
849 crtcext0 = RREG8(MGAREG_CRTCEXT_DATA);
850 crtcext0 &= 0xB0;
851 addr = offset / 8;
852 /* Can't store addresses any higher than that...
853 but we also don't have more than 16MB of memory, so it should be fine. */
854 WARN_ON(addr > 0x1fffff);
855 crtcext0 |= (!!(addr & (1<<20)))<<6;
856 WREG_CRT(0x0d, (u8)(addr & 0xff));
857 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff);
858 WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0);
859}
860
861static int mga_crtc_do_set_base(struct drm_crtc *crtc,
862 struct drm_framebuffer *fb,
863 int x, int y, int atomic)
864{
865 struct drm_gem_vram_object *gbo;
866 int ret;
867 s64 gpu_addr;
868
869 if (!atomic && fb) {
870 gbo = drm_gem_vram_of_gem(fb->obj[0]);
871 drm_gem_vram_unpin(gbo);
872 }
873
874 gbo = drm_gem_vram_of_gem(crtc->primary->fb->obj[0]);
875
876 ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM);
877 if (ret)
878 return ret;
879 gpu_addr = drm_gem_vram_offset(gbo);
880 if (gpu_addr < 0) {
881 ret = (int)gpu_addr;
882 goto err_drm_gem_vram_unpin;
883 }
884
885 mga_set_start_address(crtc, (u32)gpu_addr);
886
887 return 0;
888
889err_drm_gem_vram_unpin:
890 drm_gem_vram_unpin(gbo);
891 return ret;
892}
893
894static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
895 struct drm_framebuffer *old_fb)
896{
897 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
898}
899
900static int mga_crtc_mode_set(struct drm_crtc *crtc,
901 struct drm_display_mode *mode,
902 struct drm_display_mode *adjusted_mode,
903 int x, int y, struct drm_framebuffer *old_fb)
904{
905 struct drm_device *dev = crtc->dev;
906 struct mga_device *mdev = to_mga_device(dev);
907 const struct drm_framebuffer *fb = crtc->primary->fb;
908 int hdisplay, hsyncstart, hsyncend, htotal;
909 int vdisplay, vsyncstart, vsyncend, vtotal;
910 int pitch;
911 int option = 0, option2 = 0;
912 int i;
913 unsigned char misc = 0;
914 unsigned char ext_vga[6];
915 u8 bppshift;
916
917 static unsigned char dacvalue[] = {
918 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
919 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
920 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
921 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
922 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
923 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
924 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
925 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
926 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
927 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
928 };
929
930 bppshift = mdev->bpp_shifts[fb->format->cpp[0] - 1];
931
932 switch (mdev->type) {
933 case G200_SE_A:
934 case G200_SE_B:
935 dacvalue[MGA1064_VREF_CTL] = 0x03;
936 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
937 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
938 MGA1064_MISC_CTL_VGA8 |
939 MGA1064_MISC_CTL_DAC_RAM_CS;
940 if (mdev->has_sdram)
941 option = 0x40049120;
942 else
943 option = 0x4004d120;
944 option2 = 0x00008000;
945 break;
946 case G200_WB:
947 case G200_EW3:
948 dacvalue[MGA1064_VREF_CTL] = 0x07;
949 option = 0x41049120;
950 option2 = 0x0000b000;
951 break;
952 case G200_EV:
953 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
954 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
955 MGA1064_MISC_CTL_DAC_RAM_CS;
956 option = 0x00000120;
957 option2 = 0x0000b000;
958 break;
959 case G200_EH:
960 case G200_EH3:
961 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
962 MGA1064_MISC_CTL_DAC_RAM_CS;
963 option = 0x00000120;
964 option2 = 0x0000b000;
965 break;
966 case G200_ER:
967 break;
968 }
969
970 switch (fb->format->cpp[0] * 8) {
971 case 8:
972 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits;
973 break;
974 case 16:
975 if (fb->format->depth == 15)
976 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits;
977 else
978 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits;
979 break;
980 case 24:
981 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits;
982 break;
983 case 32:
984 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits;
985 break;
986 }
987
988 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
989 misc |= 0x40;
990 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
991 misc |= 0x80;
992
993
994 for (i = 0; i < sizeof(dacvalue); i++) {
995 if ((i <= 0x17) ||
996 (i == 0x1b) ||
997 (i == 0x1c) ||
998 ((i >= 0x1f) && (i <= 0x29)) ||
999 ((i >= 0x30) && (i <= 0x37)))
1000 continue;
1001 if (IS_G200_SE(mdev) &&
1002 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
1003 continue;
1004 if ((mdev->type == G200_EV ||
1005 mdev->type == G200_WB ||
1006 mdev->type == G200_EH ||
1007 mdev->type == G200_EW3 ||
1008 mdev->type == G200_EH3) &&
1009 (i >= 0x44) && (i <= 0x4e))
1010 continue;
1011
1012 WREG_DAC(i, dacvalue[i]);
1013 }
1014
1015 if (mdev->type == G200_ER)
1016 WREG_DAC(0x90, 0);
1017
1018 if (option)
1019 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
1020 if (option2)
1021 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
1022
1023 WREG_SEQ(2, 0xf);
1024 WREG_SEQ(3, 0);
1025 WREG_SEQ(4, 0xe);
1026
1027 pitch = fb->pitches[0] / fb->format->cpp[0];
1028 if (fb->format->cpp[0] * 8 == 24)
1029 pitch = (pitch * 3) >> (4 - bppshift);
1030 else
1031 pitch = pitch >> (4 - bppshift);
1032
1033 hdisplay = mode->hdisplay / 8 - 1;
1034 hsyncstart = mode->hsync_start / 8 - 1;
1035 hsyncend = mode->hsync_end / 8 - 1;
1036 htotal = mode->htotal / 8 - 1;
1037
1038 /* Work around hardware quirk */
1039 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
1040 htotal++;
1041
1042 vdisplay = mode->vdisplay - 1;
1043 vsyncstart = mode->vsync_start - 1;
1044 vsyncend = mode->vsync_end - 1;
1045 vtotal = mode->vtotal - 2;
1046
1047 WREG_GFX(0, 0);
1048 WREG_GFX(1, 0);
1049 WREG_GFX(2, 0);
1050 WREG_GFX(3, 0);
1051 WREG_GFX(4, 0);
1052 WREG_GFX(5, 0x40);
1053 WREG_GFX(6, 0x5);
1054 WREG_GFX(7, 0xf);
1055 WREG_GFX(8, 0xf);
1056
1057 WREG_CRT(0, htotal - 4);
1058 WREG_CRT(1, hdisplay);
1059 WREG_CRT(2, hdisplay);
1060 WREG_CRT(3, (htotal & 0x1F) | 0x80);
1061 WREG_CRT(4, hsyncstart);
1062 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
1063 WREG_CRT(6, vtotal & 0xFF);
1064 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
1065 ((vdisplay & 0x100) >> 7) |
1066 ((vsyncstart & 0x100) >> 6) |
1067 ((vdisplay & 0x100) >> 5) |
1068 ((vdisplay & 0x100) >> 4) | /* linecomp */
1069 ((vtotal & 0x200) >> 4)|
1070 ((vdisplay & 0x200) >> 3) |
1071 ((vsyncstart & 0x200) >> 2));
1072 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
1073 ((vdisplay & 0x200) >> 3));
1074 WREG_CRT(10, 0);
1075 WREG_CRT(11, 0);
1076 WREG_CRT(12, 0);
1077 WREG_CRT(13, 0);
1078 WREG_CRT(14, 0);
1079 WREG_CRT(15, 0);
1080 WREG_CRT(16, vsyncstart & 0xFF);
1081 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
1082 WREG_CRT(18, vdisplay & 0xFF);
1083 WREG_CRT(19, pitch & 0xFF);
1084 WREG_CRT(20, 0);
1085 WREG_CRT(21, vdisplay & 0xFF);
1086 WREG_CRT(22, (vtotal + 1) & 0xFF);
1087 WREG_CRT(23, 0xc3);
1088 WREG_CRT(24, vdisplay & 0xFF);
1089
1090 ext_vga[0] = 0;
1091 ext_vga[5] = 0;
1092
1093 /* TODO interlace */
1094
1095 ext_vga[0] |= (pitch & 0x300) >> 4;
1096 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) |
1097 ((hdisplay & 0x100) >> 7) |
1098 ((hsyncstart & 0x100) >> 6) |
1099 (htotal & 0x40);
1100 ext_vga[2] = ((vtotal & 0xc00) >> 10) |
1101 ((vdisplay & 0x400) >> 8) |
1102 ((vdisplay & 0xc00) >> 7) |
1103 ((vsyncstart & 0xc00) >> 5) |
1104 ((vdisplay & 0x400) >> 3);
1105 if (fb->format->cpp[0] * 8 == 24)
1106 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
1107 else
1108 ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
1109 ext_vga[4] = 0;
1110 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1111 ext_vga[1] |= 0x88;
1112
1113 /* Set pixel clocks */
1114 misc = 0x2d;
1115 WREG8(MGA_MISC_OUT, misc);
1116
1117 mga_crtc_set_plls(mdev, mode->clock);
1118
1119 for (i = 0; i < 6; i++) {
1120 WREG_ECRT(i, ext_vga[i]);
1121 }
1122
1123 if (mdev->type == G200_ER)
1124 WREG_ECRT(0x24, 0x5);
1125
1126 if (mdev->type == G200_EW3)
1127 WREG_ECRT(0x34, 0x5);
1128
1129 if (mdev->type == G200_EV) {
1130 WREG_ECRT(6, 0);
1131 }
1132
1133 WREG_ECRT(0, ext_vga[0]);
1134 /* Enable mga pixel clock */
1135 misc = 0x2d;
1136
1137 WREG8(MGA_MISC_OUT, misc);
1138
1139 mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
1140
1141 /* reset tagfifo */
1142 if (mdev->type == G200_ER) {
1143 u32 mem_ctl = RREG32(MGAREG_MEMCTL);
1144 u8 seq1;
1145
1146 /* screen off */
1147 WREG8(MGAREG_SEQ_INDEX, 0x01);
1148 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20;
1149 WREG8(MGAREG_SEQ_DATA, seq1);
1150
1151 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000);
1152 udelay(1000);
1153 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000);
1154
1155 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20);
1156 }
1157
1158
1159 if (IS_G200_SE(mdev)) {
1160 if (mdev->unique_rev_id >= 0x04) {
1161 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1162 WREG8(MGAREG_CRTCEXT_DATA, 0);
1163 } else if (mdev->unique_rev_id >= 0x02) {
1164 u8 hi_pri_lvl;
1165 u32 bpp;
1166 u32 mb;
1167
1168 if (fb->format->cpp[0] * 8 > 16)
1169 bpp = 32;
1170 else if (fb->format->cpp[0] * 8 > 8)
1171 bpp = 16;
1172 else
1173 bpp = 8;
1174
1175 mb = (mode->clock * bpp) / 1000;
1176 if (mb > 3100)
1177 hi_pri_lvl = 0;
1178 else if (mb > 2600)
1179 hi_pri_lvl = 1;
1180 else if (mb > 1900)
1181 hi_pri_lvl = 2;
1182 else if (mb > 1160)
1183 hi_pri_lvl = 3;
1184 else if (mb > 440)
1185 hi_pri_lvl = 4;
1186 else
1187 hi_pri_lvl = 5;
1188
1189 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1190 WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl);
1191 } else {
1192 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1193 if (mdev->unique_rev_id >= 0x01)
1194 WREG8(MGAREG_CRTCEXT_DATA, 0x03);
1195 else
1196 WREG8(MGAREG_CRTCEXT_DATA, 0x04);
1197 }
1198 }
1199 return 0;
1200}
1201
1202#if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
1203static int mga_suspend(struct drm_crtc *crtc)
1204{
1205 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1206 struct drm_device *dev = crtc->dev;
1207 struct mga_device *mdev = dev->dev_private;
1208 struct pci_dev *pdev = dev->pdev;
1209 int option;
1210
1211 if (mdev->suspended)
1212 return 0;
1213
1214 WREG_SEQ(1, 0x20);
1215 WREG_ECRT(1, 0x30);
1216 /* Disable the pixel clock */
1217 WREG_DAC(0x1a, 0x05);
1218 /* Power down the DAC */
1219 WREG_DAC(0x1e, 0x18);
1220 /* Power down the pixel PLL */
1221 WREG_DAC(0x1a, 0x0d);
1222
1223 /* Disable PLLs and clocks */
1224 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1225 option &= ~(0x1F8024);
1226 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1227 pci_set_power_state(pdev, PCI_D3hot);
1228 pci_disable_device(pdev);
1229
1230 mdev->suspended = true;
1231
1232 return 0;
1233}
1234
1235static int mga_resume(struct drm_crtc *crtc)
1236{
1237 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1238 struct drm_device *dev = crtc->dev;
1239 struct mga_device *mdev = dev->dev_private;
1240 struct pci_dev *pdev = dev->pdev;
1241 int option;
1242
1243 if (!mdev->suspended)
1244 return 0;
1245
1246 pci_set_power_state(pdev, PCI_D0);
1247 pci_enable_device(pdev);
1248
1249 /* Disable sysclk */
1250 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1251 option &= ~(0x4);
1252 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1253
1254 mdev->suspended = false;
1255
1256 return 0;
1257}
1258
1259#endif
1260
1261static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
1262{
1263 struct drm_device *dev = crtc->dev;
1264 struct mga_device *mdev = to_mga_device(dev);
1265 u8 seq1 = 0, crtcext1 = 0;
1266
1267 switch (mode) {
1268 case DRM_MODE_DPMS_ON:
1269 seq1 = 0;
1270 crtcext1 = 0;
1271 mga_crtc_load_lut(crtc);
1272 break;
1273 case DRM_MODE_DPMS_STANDBY:
1274 seq1 = 0x20;
1275 crtcext1 = 0x10;
1276 break;
1277 case DRM_MODE_DPMS_SUSPEND:
1278 seq1 = 0x20;
1279 crtcext1 = 0x20;
1280 break;
1281 case DRM_MODE_DPMS_OFF:
1282 seq1 = 0x20;
1283 crtcext1 = 0x30;
1284 break;
1285 }
1286
1287#if 0
1288 if (mode == DRM_MODE_DPMS_OFF) {
1289 mga_suspend(crtc);
1290 }
1291#endif
1292 WREG8(MGAREG_SEQ_INDEX, 0x01);
1293 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
1294 mga_wait_vsync(mdev);
1295 mga_wait_busy(mdev);
1296 WREG8(MGAREG_SEQ_DATA, seq1);
1297 msleep(20);
1298 WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
1299 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
1300 WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
1301
1302#if 0
1303 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) {
1304 mga_resume(crtc);
1305 drm_helper_resume_force_mode(dev);
1306 }
1307#endif
1308}
1309
1310/*
1311 * This is called before a mode is programmed. A typical use might be to
1312 * enable DPMS during the programming to avoid seeing intermediate stages,
1313 * but that's not relevant to us
1314 */
1315static void mga_crtc_prepare(struct drm_crtc *crtc)
1316{
1317 struct drm_device *dev = crtc->dev;
1318 struct mga_device *mdev = to_mga_device(dev);
1319 u8 tmp;
1320
1321 /* mga_resume(crtc);*/
1322
1323 WREG8(MGAREG_CRTC_INDEX, 0x11);
1324 tmp = RREG8(MGAREG_CRTC_DATA);
1325 WREG_CRT(0x11, tmp | 0x80);
1326
1327 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1328 WREG_SEQ(0, 1);
1329 msleep(50);
1330 WREG_SEQ(1, 0x20);
1331 msleep(20);
1332 } else {
1333 WREG8(MGAREG_SEQ_INDEX, 0x1);
1334 tmp = RREG8(MGAREG_SEQ_DATA);
1335
1336 /* start sync reset */
1337 WREG_SEQ(0, 1);
1338 WREG_SEQ(1, tmp | 0x20);
1339 }
1340
1341 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1342 mga_g200wb_prepare(crtc);
1343
1344 WREG_CRT(17, 0);
1345}
1346
1347/*
1348 * This is called after a mode is programmed. It should reverse anything done
1349 * by the prepare function
1350 */
1351static void mga_crtc_commit(struct drm_crtc *crtc)
1352{
1353 struct drm_device *dev = crtc->dev;
1354 struct mga_device *mdev = to_mga_device(dev);
1355 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1356 u8 tmp;
1357
1358 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1359 mga_g200wb_commit(crtc);
1360
1361 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1362 msleep(50);
1363 WREG_SEQ(1, 0x0);
1364 msleep(20);
1365 WREG_SEQ(0, 0x3);
1366 } else {
1367 WREG8(MGAREG_SEQ_INDEX, 0x1);
1368 tmp = RREG8(MGAREG_SEQ_DATA);
1369
1370 tmp &= ~0x20;
1371 WREG_SEQ(0x1, tmp);
1372 WREG_SEQ(0, 3);
1373 }
1374 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1375}
1376
1377/*
1378 * The core can pass us a set of gamma values to program. We actually only
1379 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
1380 * but it's a requirement that we provide the function
1381 */
1382static int mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1383 u16 *blue, uint32_t size,
1384 struct drm_modeset_acquire_ctx *ctx)
1385{
1386 mga_crtc_load_lut(crtc);
1387
1388 return 0;
1389}
1390
1391/* Simple cleanup function */
1392static void mga_crtc_destroy(struct drm_crtc *crtc)
1393{
1394 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1395
1396 drm_crtc_cleanup(crtc);
1397 kfree(mga_crtc);
1398}
1399
1400static void mga_crtc_disable(struct drm_crtc *crtc)
1401{
1402 DRM_DEBUG_KMS("\n");
1403 mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1404 if (crtc->primary->fb) {
1405 struct drm_framebuffer *fb = crtc->primary->fb;
1406 struct drm_gem_vram_object *gbo =
1407 drm_gem_vram_of_gem(fb->obj[0]);
1408 drm_gem_vram_unpin(gbo);
1409 }
1410 crtc->primary->fb = NULL;
1411}
1412
1413/* These provide the minimum set of functions required to handle a CRTC */
1414static const struct drm_crtc_funcs mga_crtc_funcs = {
1415 .cursor_set = mgag200_crtc_cursor_set,
1416 .cursor_move = mgag200_crtc_cursor_move,
1417 .gamma_set = mga_crtc_gamma_set,
1418 .set_config = drm_crtc_helper_set_config,
1419 .destroy = mga_crtc_destroy,
1420};
1421
1422static const struct drm_crtc_helper_funcs mga_helper_funcs = {
1423 .disable = mga_crtc_disable,
1424 .dpms = mga_crtc_dpms,
1425 .mode_set = mga_crtc_mode_set,
1426 .mode_set_base = mga_crtc_mode_set_base,
1427 .prepare = mga_crtc_prepare,
1428 .commit = mga_crtc_commit,
1429};
1430
1431/* CRTC setup */
1432static void mga_crtc_init(struct mga_device *mdev)
1433{
1434 struct drm_device *dev = mdev->dev;
1435 struct mga_crtc *mga_crtc;
1436
1437 mga_crtc = kzalloc(sizeof(struct mga_crtc) +
1438 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)),
1439 GFP_KERNEL);
1440
1441 if (mga_crtc == NULL)
1442 return;
1443
1444 drm_crtc_init(dev, &mga_crtc->base, &mga_crtc_funcs);
1445
1446 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE);
1447
1448 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs);
1449}
1450
1451/*
1452 * Connector
1453 */
1454
1455static int mga_vga_get_modes(struct drm_connector *connector)
1456{
1457 struct mga_connector *mga_connector = to_mga_connector(connector);
1458 struct edid *edid;
1459 int ret = 0;
1460
1461 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1462 if (edid) {
1463 drm_connector_update_edid_property(connector, edid);
1464 ret = drm_add_edid_modes(connector, edid);
1465 kfree(edid);
1466 }
1467 return ret;
1468}
1469
1470static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
1471 int bits_per_pixel)
1472{
1473 uint32_t total_area, divisor;
1474 uint64_t active_area, pixels_per_second, bandwidth;
1475 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
1476
1477 divisor = 1024;
1478
1479 if (!mode->htotal || !mode->vtotal || !mode->clock)
1480 return 0;
1481
1482 active_area = mode->hdisplay * mode->vdisplay;
1483 total_area = mode->htotal * mode->vtotal;
1484
1485 pixels_per_second = active_area * mode->clock * 1000;
1486 do_div(pixels_per_second, total_area);
1487
1488 bandwidth = pixels_per_second * bytes_per_pixel * 100;
1489 do_div(bandwidth, divisor);
1490
1491 return (uint32_t)(bandwidth);
1492}
1493
1494#define MODE_BANDWIDTH MODE_BAD
1495
1496static enum drm_mode_status mga_vga_mode_valid(struct drm_connector *connector,
1497 struct drm_display_mode *mode)
1498{
1499 struct drm_device *dev = connector->dev;
1500 struct mga_device *mdev = to_mga_device(dev);
1501 int bpp = 32;
1502
1503 if (IS_G200_SE(mdev)) {
1504 if (mdev->unique_rev_id == 0x01) {
1505 if (mode->hdisplay > 1600)
1506 return MODE_VIRTUAL_X;
1507 if (mode->vdisplay > 1200)
1508 return MODE_VIRTUAL_Y;
1509 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1510 > (24400 * 1024))
1511 return MODE_BANDWIDTH;
1512 } else if (mdev->unique_rev_id == 0x02) {
1513 if (mode->hdisplay > 1920)
1514 return MODE_VIRTUAL_X;
1515 if (mode->vdisplay > 1200)
1516 return MODE_VIRTUAL_Y;
1517 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1518 > (30100 * 1024))
1519 return MODE_BANDWIDTH;
1520 } else {
1521 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1522 > (55000 * 1024))
1523 return MODE_BANDWIDTH;
1524 }
1525 } else if (mdev->type == G200_WB) {
1526 if (mode->hdisplay > 1280)
1527 return MODE_VIRTUAL_X;
1528 if (mode->vdisplay > 1024)
1529 return MODE_VIRTUAL_Y;
1530 if (mga_vga_calculate_mode_bandwidth(mode, bpp) >
1531 (31877 * 1024))
1532 return MODE_BANDWIDTH;
1533 } else if (mdev->type == G200_EV &&
1534 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1535 > (32700 * 1024))) {
1536 return MODE_BANDWIDTH;
1537 } else if (mdev->type == G200_EH &&
1538 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1539 > (37500 * 1024))) {
1540 return MODE_BANDWIDTH;
1541 } else if (mdev->type == G200_ER &&
1542 (mga_vga_calculate_mode_bandwidth(mode,
1543 bpp) > (55000 * 1024))) {
1544 return MODE_BANDWIDTH;
1545 }
1546
1547 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
1548 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
1549 return MODE_H_ILLEGAL;
1550 }
1551
1552 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1553 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1554 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1555 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1556 return MODE_BAD;
1557 }
1558
1559 /* Validate the mode input by the user */
1560 if (connector->cmdline_mode.specified) {
1561 if (connector->cmdline_mode.bpp_specified)
1562 bpp = connector->cmdline_mode.bpp;
1563 }
1564
1565 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->vram_fb_available) {
1566 if (connector->cmdline_mode.specified)
1567 connector->cmdline_mode.specified = false;
1568 return MODE_BAD;
1569 }
1570
1571 return MODE_OK;
1572}
1573
1574static void mga_connector_destroy(struct drm_connector *connector)
1575{
1576 struct mga_connector *mga_connector = to_mga_connector(connector);
1577 mgag200_i2c_destroy(mga_connector->i2c);
1578 drm_connector_cleanup(connector);
1579}
1580
1581static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1582 .get_modes = mga_vga_get_modes,
1583 .mode_valid = mga_vga_mode_valid,
1584};
1585
1586static const struct drm_connector_funcs mga_vga_connector_funcs = {
1587 .dpms = drm_helper_connector_dpms,
1588 .fill_modes = drm_helper_probe_single_connector_modes,
1589 .destroy = mga_connector_destroy,
1590};
1591
1592static int mgag200_vga_connector_init(struct mga_device *mdev)
1593{
1594 struct drm_device *dev = mdev->dev;
1595 struct mga_connector *mconnector = &mdev->connector;
1596 struct drm_connector *connector = &mconnector->base;
1597 struct mga_i2c_chan *i2c;
1598 int ret;
1599
1600 i2c = mgag200_i2c_create(dev);
1601 if (!i2c)
1602 drm_warn(dev, "failed to add DDC bus\n");
1603
1604 ret = drm_connector_init_with_ddc(dev, connector,
1605 &mga_vga_connector_funcs,
1606 DRM_MODE_CONNECTOR_VGA,
1607 &i2c->adapter);
1608 if (ret)
1609 goto err_mgag200_i2c_destroy;
1610 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1611
1612 mconnector->i2c = i2c;
1613
1614 return 0;
1615
1616err_mgag200_i2c_destroy:
1617 mgag200_i2c_destroy(i2c);
1618 return ret;
1619}
1620
1621static const struct drm_mode_config_funcs mgag200_mode_config_funcs = {
1622 .fb_create = drm_gem_fb_create
1623};
1624
1625static unsigned int mgag200_preferred_depth(struct mga_device *mdev)
1626{
1627 if (IS_G200_SE(mdev) && mdev->vram_fb_available < (2048*1024))
1628 return 16;
1629 else
1630 return 32;
1631}
1632
1633int mgag200_modeset_init(struct mga_device *mdev)
1634{
1635 struct drm_device *dev = mdev->dev;
1636 struct drm_encoder *encoder = &mdev->encoder;
1637 struct drm_connector *connector = &mdev->connector.base;
1638 int ret;
1639
1640 mdev->bpp_shifts[0] = 0;
1641 mdev->bpp_shifts[1] = 1;
1642 mdev->bpp_shifts[2] = 0;
1643 mdev->bpp_shifts[3] = 2;
1644
1645 ret = drmm_mode_config_init(dev);
1646 if (ret) {
1647 drm_err(dev, "drmm_mode_config_init() failed, error %d\n",
1648 ret);
1649 return ret;
1650 }
1651
1652 dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1653 dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1654
1655 dev->mode_config.preferred_depth = mgag200_preferred_depth(mdev);
1656 dev->mode_config.prefer_shadow = 1;
1657
1658 dev->mode_config.fb_base = mdev->mc.vram_base;
1659
1660 dev->mode_config.funcs = &mgag200_mode_config_funcs;
1661
1662 mga_crtc_init(mdev);
1663
1664 ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC);
1665 if (ret) {
1666 drm_err(dev,
1667 "drm_simple_encoder_init() failed, error %d\n",
1668 ret);
1669 return ret;
1670 }
1671 encoder->possible_crtcs = 0x1;
1672
1673 ret = mgag200_vga_connector_init(mdev);
1674 if (ret) {
1675 drm_err(dev,
1676 "mgag200_vga_connector_init() failed, error %d\n",
1677 ret);
1678 return ret;
1679 }
1680
1681 drm_connector_attach_encoder(connector, encoder);
1682
1683 return 0;
1684}