tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26
27#include "amdgpu.h"
28#include "amdgpu_jpeg.h"
29#include "amdgpu_pm.h"
30#include "soc15d.h"
31#include "soc15_common.h"
32
33#define JPEG_IDLE_TIMEOUT msecs_to_jiffies(1000)
34
35static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);
36
37int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
38{
39 INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
40
41 return 0;
42}
43
44int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
45{
46 int i;
47
48 cancel_delayed_work_sync(&adev->jpeg.idle_work);
49
50 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
51 if (adev->jpeg.harvest_config & (1 << i))
52 continue;
53
54 amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec);
55 }
56
57 return 0;
58}
59
60int amdgpu_jpeg_suspend(struct amdgpu_device *adev)
61{
62 cancel_delayed_work_sync(&adev->jpeg.idle_work);
63
64 return 0;
65}
66
67int amdgpu_jpeg_resume(struct amdgpu_device *adev)
68{
69 return 0;
70}
71
72static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)
73{
74 struct amdgpu_device *adev =
75 container_of(work, struct amdgpu_device, jpeg.idle_work.work);
76 unsigned int fences = 0;
77 unsigned int i;
78
79 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
80 if (adev->jpeg.harvest_config & (1 << i))
81 continue;
82
83 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec);
84 }
85
86 if (fences == 0)
87 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
88 AMD_PG_STATE_GATE);
89 else
90 schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
91}
92
93void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
94{
95 struct amdgpu_device *adev = ring->adev;
96 bool set_clocks = !cancel_delayed_work_sync(&adev->jpeg.idle_work);
97
98 if (set_clocks)
99 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
100 AMD_PG_STATE_UNGATE);
101}
102
103void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring)
104{
105 schedule_delayed_work(&ring->adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
106}
107
108int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
109{
110 struct amdgpu_device *adev = ring->adev;
111 uint32_t tmp = 0;
112 unsigned i;
113 int r;
114
115 WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD);
116 r = amdgpu_ring_alloc(ring, 3);
117 if (r)
118 return r;
119
120 amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch, 0));
121 amdgpu_ring_write(ring, 0xDEADBEEF);
122 amdgpu_ring_commit(ring);
123
124 for (i = 0; i < adev->usec_timeout; i++) {
125 tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch);
126 if (tmp == 0xDEADBEEF)
127 break;
128 udelay(1);
129 }
130
131 if (i >= adev->usec_timeout)
132 r = -ETIMEDOUT;
133
134 return r;
135}
136
137static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
138 struct dma_fence **fence)
139{
140 struct amdgpu_device *adev = ring->adev;
141 struct amdgpu_job *job;
142 struct amdgpu_ib *ib;
143 struct dma_fence *f = NULL;
144 const unsigned ib_size_dw = 16;
145 int i, r;
146
147 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
148 AMDGPU_IB_POOL_DIRECT, &job);
149 if (r)
150 return r;
151
152 ib = &job->ibs[0];
153
154 ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch, 0, 0, PACKETJ_TYPE0);
155 ib->ptr[1] = 0xDEADBEEF;
156 for (i = 2; i < 16; i += 2) {
157 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
158 ib->ptr[i+1] = 0;
159 }
160 ib->length_dw = 16;
161
162 r = amdgpu_job_submit_direct(job, ring, &f);
163 if (r)
164 goto err;
165
166 if (fence)
167 *fence = dma_fence_get(f);
168 dma_fence_put(f);
169
170 return 0;
171
172err:
173 amdgpu_job_free(job);
174 return r;
175}
176
177int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
178{
179 struct amdgpu_device *adev = ring->adev;
180 uint32_t tmp = 0;
181 unsigned i;
182 struct dma_fence *fence = NULL;
183 long r = 0;
184
185 r = amdgpu_jpeg_dec_set_reg(ring, 1, &fence);
186 if (r)
187 goto error;
188
189 r = dma_fence_wait_timeout(fence, false, timeout);
190 if (r == 0) {
191 r = -ETIMEDOUT;
192 goto error;
193 } else if (r < 0) {
194 goto error;
195 } else {
196 r = 0;
197 }
198
199 for (i = 0; i < adev->usec_timeout; i++) {
200 tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch);
201 if (tmp == 0xDEADBEEF)
202 break;
203 udelay(1);
204 }
205
206 if (i >= adev->usec_timeout)
207 r = -ETIMEDOUT;
208
209 dma_fence_put(fence);
210error:
211 return r;
212}