tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/* Copyright (c) 2017 Microsemi Corporation
3 */
4
5#ifndef _SOC_MSCC_OCELOT_H
6#define _SOC_MSCC_OCELOT_H
7
8#include <linux/ptp_clock_kernel.h>
9#include <linux/net_tstamp.h>
10#include <linux/if_vlan.h>
11#include <linux/regmap.h>
12#include <net/dsa.h>
13
14/* Port Group IDs (PGID) are masks of destination ports.
15 *
16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each
17 * frame, and forwards the frame to the ports that are present in the logical
18 * AND of all 3 PGIDs.
19 *
20 * These PGID lookups are:
21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
22 * which the switch selects a destination PGID:
23 * - The {DMAC, VID} is present in the MAC table. In that case, the
24 * destination PGID is given by the DEST_IDX field of the MAC table entry
25 * that matched.
26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The
27 * frame is disseminated as being either unicast, multicast or broadcast,
28 * and according to that, the destination PGID is chosen as being the
29 * value contained by ANA_FLOODING_FLD_UNICAST,
30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
31 * The destination PGID can be an unicast set: the first PGIDs, 0 to
32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
34 * a physical port and has a single bit set in the destination ports mask:
35 * that corresponding to the port number itself. In contrast, a multicast
36 * PGID will have potentially more than one single bit set in the destination
37 * ports mask.
38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
39 * dissects each frame and generates a 4-bit Link Aggregation Code which is
40 * used for this second PGID table lookup. The goal of link aggregation is to
41 * hash multiple flows within the same LAG on to different destination ports.
42 * The first lookup will result in a PGID with all the LAG members present in
43 * the destination ports mask, and the second lookup, by Link Aggregation
44 * Code, will ensure that each flow gets forwarded only to a single port out
45 * of that mask (there are no duplicates).
46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
47 * is indexed with the ingress port (plus 80). These PGIDs answer the
48 * question "is port i allowed to forward traffic to port j?" If yes, then
49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
51 */
52
53/* Reserve some destination PGIDs at the end of the range:
54 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
55 * of the switch port net devices, towards the CPU port module.
56 * PGID_UC: the flooding destinations for unknown unicast traffic.
57 * PGID_MC: the flooding destinations for broadcast and non-IP multicast
58 * traffic.
59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
61 */
62#define PGID_CPU 59
63#define PGID_UC 60
64#define PGID_MC 61
65#define PGID_MCIPV4 62
66#define PGID_MCIPV6 63
67
68/* Aggregation PGIDs, one per Link Aggregation Code */
69#define PGID_AGGR 64
70
71/* Source PGIDs, one per physical port */
72#define PGID_SRC 80
73
74#define IFH_INJ_BYPASS BIT(31)
75#define IFH_INJ_POP_CNT_DISABLE (3 << 28)
76
77#define IFH_TAG_TYPE_C 0
78#define IFH_TAG_TYPE_S 1
79
80#define IFH_REW_OP_NOOP 0x0
81#define IFH_REW_OP_DSCP 0x1
82#define IFH_REW_OP_ONE_STEP_PTP 0x2
83#define IFH_REW_OP_TWO_STEP_PTP 0x3
84#define IFH_REW_OP_ORIGIN_PTP 0x5
85
86#define OCELOT_TAG_LEN 16
87#define OCELOT_SHORT_PREFIX_LEN 4
88#define OCELOT_LONG_PREFIX_LEN 16
89
90#define OCELOT_SPEED_2500 0
91#define OCELOT_SPEED_1000 1
92#define OCELOT_SPEED_100 2
93#define OCELOT_SPEED_10 3
94
95#define OCELOT_PTP_PINS_NUM 4
96
97#define TARGET_OFFSET 24
98#define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
99#define REG(reg, offset) [reg & REG_MASK] = offset
100
101#define REG_RESERVED_ADDR 0xffffffff
102#define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
103
104enum ocelot_target {
105 ANA = 1,
106 QS,
107 QSYS,
108 REW,
109 SYS,
110 S2,
111 HSIO,
112 PTP,
113 GCB,
114 TARGET_MAX,
115};
116
117enum ocelot_reg {
118 ANA_ADVLEARN = ANA << TARGET_OFFSET,
119 ANA_VLANMASK,
120 ANA_PORT_B_DOMAIN,
121 ANA_ANAGEFIL,
122 ANA_ANEVENTS,
123 ANA_STORMLIMIT_BURST,
124 ANA_STORMLIMIT_CFG,
125 ANA_ISOLATED_PORTS,
126 ANA_COMMUNITY_PORTS,
127 ANA_AUTOAGE,
128 ANA_MACTOPTIONS,
129 ANA_LEARNDISC,
130 ANA_AGENCTRL,
131 ANA_MIRRORPORTS,
132 ANA_EMIRRORPORTS,
133 ANA_FLOODING,
134 ANA_FLOODING_IPMC,
135 ANA_SFLOW_CFG,
136 ANA_PORT_MODE,
137 ANA_CUT_THRU_CFG,
138 ANA_PGID_PGID,
139 ANA_TABLES_ANMOVED,
140 ANA_TABLES_MACHDATA,
141 ANA_TABLES_MACLDATA,
142 ANA_TABLES_STREAMDATA,
143 ANA_TABLES_MACACCESS,
144 ANA_TABLES_MACTINDX,
145 ANA_TABLES_VLANACCESS,
146 ANA_TABLES_VLANTIDX,
147 ANA_TABLES_ISDXACCESS,
148 ANA_TABLES_ISDXTIDX,
149 ANA_TABLES_ENTRYLIM,
150 ANA_TABLES_PTP_ID_HIGH,
151 ANA_TABLES_PTP_ID_LOW,
152 ANA_TABLES_STREAMACCESS,
153 ANA_TABLES_STREAMTIDX,
154 ANA_TABLES_SEQ_HISTORY,
155 ANA_TABLES_SEQ_MASK,
156 ANA_TABLES_SFID_MASK,
157 ANA_TABLES_SFIDACCESS,
158 ANA_TABLES_SFIDTIDX,
159 ANA_MSTI_STATE,
160 ANA_OAM_UPM_LM_CNT,
161 ANA_SG_ACCESS_CTRL,
162 ANA_SG_CONFIG_REG_1,
163 ANA_SG_CONFIG_REG_2,
164 ANA_SG_CONFIG_REG_3,
165 ANA_SG_CONFIG_REG_4,
166 ANA_SG_CONFIG_REG_5,
167 ANA_SG_GCL_GS_CONFIG,
168 ANA_SG_GCL_TI_CONFIG,
169 ANA_SG_STATUS_REG_1,
170 ANA_SG_STATUS_REG_2,
171 ANA_SG_STATUS_REG_3,
172 ANA_PORT_VLAN_CFG,
173 ANA_PORT_DROP_CFG,
174 ANA_PORT_QOS_CFG,
175 ANA_PORT_VCAP_CFG,
176 ANA_PORT_VCAP_S1_KEY_CFG,
177 ANA_PORT_VCAP_S2_CFG,
178 ANA_PORT_PCP_DEI_MAP,
179 ANA_PORT_CPU_FWD_CFG,
180 ANA_PORT_CPU_FWD_BPDU_CFG,
181 ANA_PORT_CPU_FWD_GARP_CFG,
182 ANA_PORT_CPU_FWD_CCM_CFG,
183 ANA_PORT_PORT_CFG,
184 ANA_PORT_POL_CFG,
185 ANA_PORT_PTP_CFG,
186 ANA_PORT_PTP_DLY1_CFG,
187 ANA_PORT_PTP_DLY2_CFG,
188 ANA_PORT_SFID_CFG,
189 ANA_PFC_PFC_CFG,
190 ANA_PFC_PFC_TIMER,
191 ANA_IPT_OAM_MEP_CFG,
192 ANA_IPT_IPT,
193 ANA_PPT_PPT,
194 ANA_FID_MAP_FID_MAP,
195 ANA_AGGR_CFG,
196 ANA_CPUQ_CFG,
197 ANA_CPUQ_CFG2,
198 ANA_CPUQ_8021_CFG,
199 ANA_DSCP_CFG,
200 ANA_DSCP_REWR_CFG,
201 ANA_VCAP_RNG_TYPE_CFG,
202 ANA_VCAP_RNG_VAL_CFG,
203 ANA_VRAP_CFG,
204 ANA_VRAP_HDR_DATA,
205 ANA_VRAP_HDR_MASK,
206 ANA_DISCARD_CFG,
207 ANA_FID_CFG,
208 ANA_POL_PIR_CFG,
209 ANA_POL_CIR_CFG,
210 ANA_POL_MODE_CFG,
211 ANA_POL_PIR_STATE,
212 ANA_POL_CIR_STATE,
213 ANA_POL_STATE,
214 ANA_POL_FLOWC,
215 ANA_POL_HYST,
216 ANA_POL_MISC_CFG,
217 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
218 QS_XTR_RD,
219 QS_XTR_FRM_PRUNING,
220 QS_XTR_FLUSH,
221 QS_XTR_DATA_PRESENT,
222 QS_XTR_CFG,
223 QS_INJ_GRP_CFG,
224 QS_INJ_WR,
225 QS_INJ_CTRL,
226 QS_INJ_STATUS,
227 QS_INJ_ERR,
228 QS_INH_DBG,
229 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
230 QSYS_SWITCH_PORT_MODE,
231 QSYS_STAT_CNT_CFG,
232 QSYS_EEE_CFG,
233 QSYS_EEE_THRES,
234 QSYS_IGR_NO_SHARING,
235 QSYS_EGR_NO_SHARING,
236 QSYS_SW_STATUS,
237 QSYS_EXT_CPU_CFG,
238 QSYS_PAD_CFG,
239 QSYS_CPU_GROUP_MAP,
240 QSYS_QMAP,
241 QSYS_ISDX_SGRP,
242 QSYS_TIMED_FRAME_ENTRY,
243 QSYS_TFRM_MISC,
244 QSYS_TFRM_PORT_DLY,
245 QSYS_TFRM_TIMER_CFG_1,
246 QSYS_TFRM_TIMER_CFG_2,
247 QSYS_TFRM_TIMER_CFG_3,
248 QSYS_TFRM_TIMER_CFG_4,
249 QSYS_TFRM_TIMER_CFG_5,
250 QSYS_TFRM_TIMER_CFG_6,
251 QSYS_TFRM_TIMER_CFG_7,
252 QSYS_TFRM_TIMER_CFG_8,
253 QSYS_RED_PROFILE,
254 QSYS_RES_QOS_MODE,
255 QSYS_RES_CFG,
256 QSYS_RES_STAT,
257 QSYS_EGR_DROP_MODE,
258 QSYS_EQ_CTRL,
259 QSYS_EVENTS_CORE,
260 QSYS_QMAXSDU_CFG_0,
261 QSYS_QMAXSDU_CFG_1,
262 QSYS_QMAXSDU_CFG_2,
263 QSYS_QMAXSDU_CFG_3,
264 QSYS_QMAXSDU_CFG_4,
265 QSYS_QMAXSDU_CFG_5,
266 QSYS_QMAXSDU_CFG_6,
267 QSYS_QMAXSDU_CFG_7,
268 QSYS_PREEMPTION_CFG,
269 QSYS_CIR_CFG,
270 QSYS_EIR_CFG,
271 QSYS_SE_CFG,
272 QSYS_SE_DWRR_CFG,
273 QSYS_SE_CONNECT,
274 QSYS_SE_DLB_SENSE,
275 QSYS_CIR_STATE,
276 QSYS_EIR_STATE,
277 QSYS_SE_STATE,
278 QSYS_HSCH_MISC_CFG,
279 QSYS_TAG_CONFIG,
280 QSYS_TAS_PARAM_CFG_CTRL,
281 QSYS_PORT_MAX_SDU,
282 QSYS_PARAM_CFG_REG_1,
283 QSYS_PARAM_CFG_REG_2,
284 QSYS_PARAM_CFG_REG_3,
285 QSYS_PARAM_CFG_REG_4,
286 QSYS_PARAM_CFG_REG_5,
287 QSYS_GCL_CFG_REG_1,
288 QSYS_GCL_CFG_REG_2,
289 QSYS_PARAM_STATUS_REG_1,
290 QSYS_PARAM_STATUS_REG_2,
291 QSYS_PARAM_STATUS_REG_3,
292 QSYS_PARAM_STATUS_REG_4,
293 QSYS_PARAM_STATUS_REG_5,
294 QSYS_PARAM_STATUS_REG_6,
295 QSYS_PARAM_STATUS_REG_7,
296 QSYS_PARAM_STATUS_REG_8,
297 QSYS_PARAM_STATUS_REG_9,
298 QSYS_GCL_STATUS_REG_1,
299 QSYS_GCL_STATUS_REG_2,
300 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
301 REW_TAG_CFG,
302 REW_PORT_CFG,
303 REW_DSCP_CFG,
304 REW_PCP_DEI_QOS_MAP_CFG,
305 REW_PTP_CFG,
306 REW_PTP_DLY1_CFG,
307 REW_RED_TAG_CFG,
308 REW_DSCP_REMAP_DP1_CFG,
309 REW_DSCP_REMAP_CFG,
310 REW_STAT_CFG,
311 REW_REW_STICKY,
312 REW_PPT,
313 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
314 SYS_COUNT_RX_UNICAST,
315 SYS_COUNT_RX_MULTICAST,
316 SYS_COUNT_RX_BROADCAST,
317 SYS_COUNT_RX_SHORTS,
318 SYS_COUNT_RX_FRAGMENTS,
319 SYS_COUNT_RX_JABBERS,
320 SYS_COUNT_RX_CRC_ALIGN_ERRS,
321 SYS_COUNT_RX_SYM_ERRS,
322 SYS_COUNT_RX_64,
323 SYS_COUNT_RX_65_127,
324 SYS_COUNT_RX_128_255,
325 SYS_COUNT_RX_256_1023,
326 SYS_COUNT_RX_1024_1526,
327 SYS_COUNT_RX_1527_MAX,
328 SYS_COUNT_RX_PAUSE,
329 SYS_COUNT_RX_CONTROL,
330 SYS_COUNT_RX_LONGS,
331 SYS_COUNT_RX_CLASSIFIED_DROPS,
332 SYS_COUNT_TX_OCTETS,
333 SYS_COUNT_TX_UNICAST,
334 SYS_COUNT_TX_MULTICAST,
335 SYS_COUNT_TX_BROADCAST,
336 SYS_COUNT_TX_COLLISION,
337 SYS_COUNT_TX_DROPS,
338 SYS_COUNT_TX_PAUSE,
339 SYS_COUNT_TX_64,
340 SYS_COUNT_TX_65_127,
341 SYS_COUNT_TX_128_511,
342 SYS_COUNT_TX_512_1023,
343 SYS_COUNT_TX_1024_1526,
344 SYS_COUNT_TX_1527_MAX,
345 SYS_COUNT_TX_AGING,
346 SYS_RESET_CFG,
347 SYS_SR_ETYPE_CFG,
348 SYS_VLAN_ETYPE_CFG,
349 SYS_PORT_MODE,
350 SYS_FRONT_PORT_MODE,
351 SYS_FRM_AGING,
352 SYS_STAT_CFG,
353 SYS_SW_STATUS,
354 SYS_MISC_CFG,
355 SYS_REW_MAC_HIGH_CFG,
356 SYS_REW_MAC_LOW_CFG,
357 SYS_TIMESTAMP_OFFSET,
358 SYS_CMID,
359 SYS_PAUSE_CFG,
360 SYS_PAUSE_TOT_CFG,
361 SYS_ATOP,
362 SYS_ATOP_TOT_CFG,
363 SYS_MAC_FC_CFG,
364 SYS_MMGT,
365 SYS_MMGT_FAST,
366 SYS_EVENTS_DIF,
367 SYS_EVENTS_CORE,
368 SYS_CNT,
369 SYS_PTP_STATUS,
370 SYS_PTP_TXSTAMP,
371 SYS_PTP_NXT,
372 SYS_PTP_CFG,
373 SYS_RAM_INIT,
374 SYS_CM_ADDR,
375 SYS_CM_DATA_WR,
376 SYS_CM_DATA_RD,
377 SYS_CM_OP,
378 SYS_CM_DATA,
379 S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
380 S2_CORE_MV_CFG,
381 S2_CACHE_ENTRY_DAT,
382 S2_CACHE_MASK_DAT,
383 S2_CACHE_ACTION_DAT,
384 S2_CACHE_CNT_DAT,
385 S2_CACHE_TG_DAT,
386 PTP_PIN_CFG = PTP << TARGET_OFFSET,
387 PTP_PIN_TOD_SEC_MSB,
388 PTP_PIN_TOD_SEC_LSB,
389 PTP_PIN_TOD_NSEC,
390 PTP_PIN_WF_HIGH_PERIOD,
391 PTP_PIN_WF_LOW_PERIOD,
392 PTP_CFG_MISC,
393 PTP_CLK_CFG_ADJ_CFG,
394 PTP_CLK_CFG_ADJ_FREQ,
395 GCB_SOFT_RST = GCB << TARGET_OFFSET,
396};
397
398enum ocelot_regfield {
399 ANA_ADVLEARN_VLAN_CHK,
400 ANA_ADVLEARN_LEARN_MIRROR,
401 ANA_ANEVENTS_FLOOD_DISCARD,
402 ANA_ANEVENTS_MSTI_DROP,
403 ANA_ANEVENTS_ACLKILL,
404 ANA_ANEVENTS_ACLUSED,
405 ANA_ANEVENTS_AUTOAGE,
406 ANA_ANEVENTS_VS2TTL1,
407 ANA_ANEVENTS_STORM_DROP,
408 ANA_ANEVENTS_LEARN_DROP,
409 ANA_ANEVENTS_AGED_ENTRY,
410 ANA_ANEVENTS_CPU_LEARN_FAILED,
411 ANA_ANEVENTS_AUTO_LEARN_FAILED,
412 ANA_ANEVENTS_LEARN_REMOVE,
413 ANA_ANEVENTS_AUTO_LEARNED,
414 ANA_ANEVENTS_AUTO_MOVED,
415 ANA_ANEVENTS_DROPPED,
416 ANA_ANEVENTS_CLASSIFIED_DROP,
417 ANA_ANEVENTS_CLASSIFIED_COPY,
418 ANA_ANEVENTS_VLAN_DISCARD,
419 ANA_ANEVENTS_FWD_DISCARD,
420 ANA_ANEVENTS_MULTICAST_FLOOD,
421 ANA_ANEVENTS_UNICAST_FLOOD,
422 ANA_ANEVENTS_DEST_KNOWN,
423 ANA_ANEVENTS_BUCKET3_MATCH,
424 ANA_ANEVENTS_BUCKET2_MATCH,
425 ANA_ANEVENTS_BUCKET1_MATCH,
426 ANA_ANEVENTS_BUCKET0_MATCH,
427 ANA_ANEVENTS_CPU_OPERATION,
428 ANA_ANEVENTS_DMAC_LOOKUP,
429 ANA_ANEVENTS_SMAC_LOOKUP,
430 ANA_ANEVENTS_SEQ_GEN_ERR_0,
431 ANA_ANEVENTS_SEQ_GEN_ERR_1,
432 ANA_TABLES_MACACCESS_B_DOM,
433 ANA_TABLES_MACTINDX_BUCKET,
434 ANA_TABLES_MACTINDX_M_INDEX,
435 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
436 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
437 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
438 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
439 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
440 SYS_RESET_CFG_CORE_ENA,
441 SYS_RESET_CFG_MEM_ENA,
442 SYS_RESET_CFG_MEM_INIT,
443 GCB_SOFT_RST_SWC_RST,
444 REGFIELD_MAX
445};
446
447enum ocelot_ptp_pins {
448 PTP_PIN_0,
449 PTP_PIN_1,
450 PTP_PIN_2,
451 PTP_PIN_3,
452 TOD_ACC_PIN
453};
454
455struct ocelot_stat_layout {
456 u32 offset;
457 char name[ETH_GSTRING_LEN];
458};
459
460enum ocelot_tag_prefix {
461 OCELOT_TAG_PREFIX_DISABLED = 0,
462 OCELOT_TAG_PREFIX_NONE,
463 OCELOT_TAG_PREFIX_SHORT,
464 OCELOT_TAG_PREFIX_LONG,
465};
466
467struct ocelot;
468
469struct ocelot_ops {
470 int (*reset)(struct ocelot *ocelot);
471};
472
473struct ocelot_acl_block {
474 struct list_head rules;
475 int count;
476 int pol_lpr;
477};
478
479struct ocelot_port {
480 struct ocelot *ocelot;
481
482 void __iomem *regs;
483
484 bool vlan_aware;
485
486 /* Ingress default VLAN (pvid) */
487 u16 pvid;
488
489 /* Egress default VLAN (vid) */
490 u16 vid;
491
492 u8 ptp_cmd;
493 struct sk_buff_head tx_skbs;
494 u8 ts_id;
495
496 phy_interface_t phy_mode;
497};
498
499struct ocelot {
500 struct device *dev;
501
502 const struct ocelot_ops *ops;
503 struct regmap *targets[TARGET_MAX];
504 struct regmap_field *regfields[REGFIELD_MAX];
505 const u32 *const *map;
506 const struct ocelot_stat_layout *stats_layout;
507 unsigned int num_stats;
508
509 int shared_queue_sz;
510 int num_mact_rows;
511
512 struct net_device *hw_bridge_dev;
513 u16 bridge_mask;
514 u16 bridge_fwd_mask;
515
516 struct ocelot_port **ports;
517
518 u8 base_mac[ETH_ALEN];
519
520 /* Keep track of the vlan port masks */
521 u32 vlan_mask[VLAN_N_VID];
522
523 /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
524 * the CPU is located after the physical ports (at the
525 * num_phys_ports index).
526 */
527 u8 num_phys_ports;
528
529 int npi;
530
531 enum ocelot_tag_prefix inj_prefix;
532 enum ocelot_tag_prefix xtr_prefix;
533
534 u32 *lags;
535
536 struct list_head multicast;
537
538 struct ocelot_acl_block acl_block;
539
540 const struct vcap_field *vcap_is2_keys;
541 const struct vcap_field *vcap_is2_actions;
542 const struct vcap_props *vcap;
543
544 /* Workqueue to check statistics for overflow with its lock */
545 struct mutex stats_lock;
546 u64 *stats;
547 struct delayed_work stats_work;
548 struct workqueue_struct *stats_queue;
549
550 u8 ptp:1;
551 struct ptp_clock *ptp_clock;
552 struct ptp_clock_info ptp_info;
553 struct hwtstamp_config hwtstamp_config;
554 /* Protects the PTP interface state */
555 struct mutex ptp_lock;
556 /* Protects the PTP clock */
557 spinlock_t ptp_clock_lock;
558 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM];
559};
560
561struct ocelot_policer {
562 u32 rate; /* kilobit per second */
563 u32 burst; /* bytes */
564};
565
566#define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
567#define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
568#define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
569#define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
570
571#define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
572#define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
573#define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
574#define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
575
576#define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
577#define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
578#define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
579#define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
580
581/* I/O */
582u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
583void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
584u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
585void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
586void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
587 u32 offset);
588
589/* Hardware initialization */
590int ocelot_regfields_init(struct ocelot *ocelot,
591 const struct reg_field *const regfields);
592struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
593void ocelot_configure_cpu(struct ocelot *ocelot, int npi,
594 enum ocelot_tag_prefix injection,
595 enum ocelot_tag_prefix extraction);
596int ocelot_init(struct ocelot *ocelot);
597void ocelot_deinit(struct ocelot *ocelot);
598void ocelot_init_port(struct ocelot *ocelot, int port);
599
600/* DSA callbacks */
601void ocelot_port_enable(struct ocelot *ocelot, int port,
602 struct phy_device *phy);
603void ocelot_port_disable(struct ocelot *ocelot, int port);
604void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
605void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
606int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
607int ocelot_get_ts_info(struct ocelot *ocelot, int port,
608 struct ethtool_ts_info *info);
609void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
610void ocelot_adjust_link(struct ocelot *ocelot, int port,
611 struct phy_device *phydev);
612void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
613 bool vlan_aware);
614void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
615int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
616 struct net_device *bridge);
617int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
618 struct net_device *bridge);
619int ocelot_fdb_dump(struct ocelot *ocelot, int port,
620 dsa_fdb_dump_cb_t *cb, void *data);
621int ocelot_fdb_add(struct ocelot *ocelot, int port,
622 const unsigned char *addr, u16 vid);
623int ocelot_fdb_del(struct ocelot *ocelot, int port,
624 const unsigned char *addr, u16 vid);
625int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
626 bool untagged);
627int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
628int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
629int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
630int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port,
631 struct sk_buff *skb);
632void ocelot_get_txtstamp(struct ocelot *ocelot);
633void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu);
634int ocelot_get_max_mtu(struct ocelot *ocelot, int port);
635int ocelot_port_policer_add(struct ocelot *ocelot, int port,
636 struct ocelot_policer *pol);
637int ocelot_port_policer_del(struct ocelot *ocelot, int port);
638int ocelot_cls_flower_replace(struct ocelot *ocelot, int port,
639 struct flow_cls_offload *f, bool ingress);
640int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
641 struct flow_cls_offload *f, bool ingress);
642int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
643 struct flow_cls_offload *f, bool ingress);
644
645#endif