tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
4 * synchronization devices.
5 *
6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
7 */
8#ifndef PTP_IDTCLOCKMATRIX_H
9#define PTP_IDTCLOCKMATRIX_H
10
11#include <linux/ktime.h>
12
13#include "idt8a340_reg.h"
14
15#define FW_FILENAME "idtcm.bin"
16#define MAX_PHC_PLL 4
17
18#define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)
19
20#define PLL_MASK_ADDR (0xFFA5)
21#define DEFAULT_PLL_MASK (0x04)
22
23#define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8))
24#define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8))
25
26#define OUTPUT_MASK_PLL0_ADDR (0xFFB0)
27#define OUTPUT_MASK_PLL1_ADDR (0xFFB2)
28#define OUTPUT_MASK_PLL2_ADDR (0xFFB4)
29#define OUTPUT_MASK_PLL3_ADDR (0xFFB6)
30
31#define DEFAULT_OUTPUT_MASK_PLL0 (0x003)
32#define DEFAULT_OUTPUT_MASK_PLL1 (0x00c)
33#define DEFAULT_OUTPUT_MASK_PLL2 (0x030)
34#define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0)
35
36#define POST_SM_RESET_DELAY_MS (3000)
37#define PHASE_PULL_IN_THRESHOLD_NS (150000)
38#define TOD_WRITE_OVERHEAD_COUNT_MAX (5)
39#define TOD_BYTE_COUNT (11)
40#define WR_PHASE_SETUP_MS (5000)
41
42/* Values of DPLL_N.DPLL_MODE.PLL_MODE */
43enum pll_mode {
44 PLL_MODE_MIN = 0,
45 PLL_MODE_NORMAL = PLL_MODE_MIN,
46 PLL_MODE_WRITE_PHASE = 1,
47 PLL_MODE_WRITE_FREQUENCY = 2,
48 PLL_MODE_GPIO_INC_DEC = 3,
49 PLL_MODE_SYNTHESIS = 4,
50 PLL_MODE_PHASE_MEASUREMENT = 5,
51 PLL_MODE_MAX = PLL_MODE_PHASE_MEASUREMENT,
52};
53
54enum hw_tod_write_trig_sel {
55 HW_TOD_WR_TRIG_SEL_MIN = 0,
56 HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN,
57 HW_TOD_WR_TRIG_SEL_RESERVED = 1,
58 HW_TOD_WR_TRIG_SEL_TOD_PPS = 2,
59 HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3,
60 HW_TOD_WR_TRIG_SEL_PWM_PPS = 4,
61 HW_TOD_WR_TRIG_SEL_GPIO = 5,
62 HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6,
63 WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC,
64};
65
66struct idtcm;
67
68struct idtcm_channel {
69 struct ptp_clock_info caps;
70 struct ptp_clock *ptp_clock;
71 struct idtcm *idtcm;
72 u16 dpll_phase;
73 u16 dpll_freq;
74 u16 dpll_n;
75 u16 dpll_ctrl_n;
76 u16 dpll_phase_pull_in;
77 u16 tod_read_primary;
78 u16 tod_write;
79 u16 tod_n;
80 u16 hw_dpll_n;
81 enum pll_mode pll_mode;
82 u16 output_mask;
83 int write_phase_ready;
84};
85
86struct idtcm {
87 struct idtcm_channel channel[MAX_PHC_PLL];
88 struct i2c_client *client;
89 u8 page_offset;
90 u8 pll_mask;
91
92 /* Overhead calculation for adjtime */
93 u8 calculate_overhead_flag;
94 s64 tod_write_overhead_ns;
95 ktime_t start_time;
96
97 /* Protects I2C read/modify/write registers from concurrent access */
98 struct mutex reg_lock;
99};
100
101struct idtcm_fwrc {
102 u8 hiaddr;
103 u8 loaddr;
104 u8 value;
105 u8 reserved;
106} __packed;
107
108#endif /* PTP_IDTCLOCKMATRIX_H */