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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#ifdef pr_fmt
32#undef pr_fmt
33#endif
34
35#define pr_fmt(fmt) "amdgpu: " fmt
36
37#ifdef dev_fmt
38#undef dev_fmt
39#endif
40
41#define dev_fmt(fmt) "amdgpu: " fmt
42
43#include "amdgpu_ctx.h"
44
45#include <linux/atomic.h>
46#include <linux/wait.h>
47#include <linux/list.h>
48#include <linux/kref.h>
49#include <linux/rbtree.h>
50#include <linux/hashtable.h>
51#include <linux/dma-fence.h>
52
53#include <drm/ttm/ttm_bo_api.h>
54#include <drm/ttm/ttm_bo_driver.h>
55#include <drm/ttm/ttm_placement.h>
56#include <drm/ttm/ttm_module.h>
57#include <drm/ttm/ttm_execbuf_util.h>
58
59#include <drm/amdgpu_drm.h>
60#include <drm/drm_gem.h>
61#include <drm/drm_ioctl.h>
62#include <drm/gpu_scheduler.h>
63
64#include <kgd_kfd_interface.h>
65#include "dm_pp_interface.h"
66#include "kgd_pp_interface.h"
67
68#include "amd_shared.h"
69#include "amdgpu_mode.h"
70#include "amdgpu_ih.h"
71#include "amdgpu_irq.h"
72#include "amdgpu_ucode.h"
73#include "amdgpu_ttm.h"
74#include "amdgpu_psp.h"
75#include "amdgpu_gds.h"
76#include "amdgpu_sync.h"
77#include "amdgpu_ring.h"
78#include "amdgpu_vm.h"
79#include "amdgpu_dpm.h"
80#include "amdgpu_acp.h"
81#include "amdgpu_uvd.h"
82#include "amdgpu_vce.h"
83#include "amdgpu_vcn.h"
84#include "amdgpu_jpeg.h"
85#include "amdgpu_mn.h"
86#include "amdgpu_gmc.h"
87#include "amdgpu_gfx.h"
88#include "amdgpu_sdma.h"
89#include "amdgpu_nbio.h"
90#include "amdgpu_dm.h"
91#include "amdgpu_virt.h"
92#include "amdgpu_csa.h"
93#include "amdgpu_gart.h"
94#include "amdgpu_debugfs.h"
95#include "amdgpu_job.h"
96#include "amdgpu_bo_list.h"
97#include "amdgpu_gem.h"
98#include "amdgpu_doorbell.h"
99#include "amdgpu_amdkfd.h"
100#include "amdgpu_smu.h"
101#include "amdgpu_discovery.h"
102#include "amdgpu_mes.h"
103#include "amdgpu_umc.h"
104#include "amdgpu_mmhub.h"
105#include "amdgpu_df.h"
106
107#define MAX_GPU_INSTANCE 16
108
109struct amdgpu_gpu_instance
110{
111 struct amdgpu_device *adev;
112 int mgpu_fan_enabled;
113};
114
115struct amdgpu_mgpu_info
116{
117 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
118 struct mutex mutex;
119 uint32_t num_gpu;
120 uint32_t num_dgpu;
121 uint32_t num_apu;
122};
123
124#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
125
126/*
127 * Modules parameters.
128 */
129extern int amdgpu_modeset;
130extern int amdgpu_vram_limit;
131extern int amdgpu_vis_vram_limit;
132extern int amdgpu_gart_size;
133extern int amdgpu_gtt_size;
134extern int amdgpu_moverate;
135extern int amdgpu_benchmarking;
136extern int amdgpu_testing;
137extern int amdgpu_audio;
138extern int amdgpu_disp_priority;
139extern int amdgpu_hw_i2c;
140extern int amdgpu_pcie_gen2;
141extern int amdgpu_msi;
142extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
143extern int amdgpu_dpm;
144extern int amdgpu_fw_load_type;
145extern int amdgpu_aspm;
146extern int amdgpu_runtime_pm;
147extern uint amdgpu_ip_block_mask;
148extern int amdgpu_bapm;
149extern int amdgpu_deep_color;
150extern int amdgpu_vm_size;
151extern int amdgpu_vm_block_size;
152extern int amdgpu_vm_fragment_size;
153extern int amdgpu_vm_fault_stop;
154extern int amdgpu_vm_debug;
155extern int amdgpu_vm_update_mode;
156extern int amdgpu_exp_hw_support;
157extern int amdgpu_dc;
158extern int amdgpu_sched_jobs;
159extern int amdgpu_sched_hw_submission;
160extern uint amdgpu_pcie_gen_cap;
161extern uint amdgpu_pcie_lane_cap;
162extern uint amdgpu_cg_mask;
163extern uint amdgpu_pg_mask;
164extern uint amdgpu_sdma_phase_quantum;
165extern char *amdgpu_disable_cu;
166extern char *amdgpu_virtual_display;
167extern uint amdgpu_pp_feature_mask;
168extern uint amdgpu_force_long_training;
169extern int amdgpu_job_hang_limit;
170extern int amdgpu_lbpw;
171extern int amdgpu_compute_multipipe;
172extern int amdgpu_gpu_recovery;
173extern int amdgpu_emu_mode;
174extern uint amdgpu_smu_memory_pool_size;
175extern uint amdgpu_dc_feature_mask;
176extern uint amdgpu_dc_debug_mask;
177extern uint amdgpu_dm_abm_level;
178extern struct amdgpu_mgpu_info mgpu_info;
179extern int amdgpu_ras_enable;
180extern uint amdgpu_ras_mask;
181extern int amdgpu_async_gfx_ring;
182extern int amdgpu_mcbp;
183extern int amdgpu_discovery;
184extern int amdgpu_mes;
185extern int amdgpu_noretry;
186extern int amdgpu_force_asic_type;
187#ifdef CONFIG_HSA_AMD
188extern int sched_policy;
189#else
190static const int sched_policy = KFD_SCHED_POLICY_HWS;
191#endif
192
193extern int amdgpu_tmz;
194
195#ifdef CONFIG_DRM_AMDGPU_SI
196extern int amdgpu_si_support;
197#endif
198#ifdef CONFIG_DRM_AMDGPU_CIK
199extern int amdgpu_cik_support;
200#endif
201
202#define AMDGPU_VM_MAX_NUM_CTX 4096
203#define AMDGPU_SG_THRESHOLD (256*1024*1024)
204#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
205#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
206#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
207#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
208#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
209#define AMDGPUFB_CONN_LIMIT 4
210#define AMDGPU_BIOS_NUM_SCRATCH 16
211
212/* hard reset data */
213#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
214
215/* reset flags */
216#define AMDGPU_RESET_GFX (1 << 0)
217#define AMDGPU_RESET_COMPUTE (1 << 1)
218#define AMDGPU_RESET_DMA (1 << 2)
219#define AMDGPU_RESET_CP (1 << 3)
220#define AMDGPU_RESET_GRBM (1 << 4)
221#define AMDGPU_RESET_DMA1 (1 << 5)
222#define AMDGPU_RESET_RLC (1 << 6)
223#define AMDGPU_RESET_SEM (1 << 7)
224#define AMDGPU_RESET_IH (1 << 8)
225#define AMDGPU_RESET_VMC (1 << 9)
226#define AMDGPU_RESET_MC (1 << 10)
227#define AMDGPU_RESET_DISPLAY (1 << 11)
228#define AMDGPU_RESET_UVD (1 << 12)
229#define AMDGPU_RESET_VCE (1 << 13)
230#define AMDGPU_RESET_VCE1 (1 << 14)
231
232/* max cursor sizes (in pixels) */
233#define CIK_CURSOR_WIDTH 128
234#define CIK_CURSOR_HEIGHT 128
235
236struct amdgpu_device;
237struct amdgpu_ib;
238struct amdgpu_cs_parser;
239struct amdgpu_job;
240struct amdgpu_irq_src;
241struct amdgpu_fpriv;
242struct amdgpu_bo_va_mapping;
243struct amdgpu_atif;
244struct kfd_vm_fault_info;
245
246enum amdgpu_cp_irq {
247 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
248 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
249 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
250 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
251 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
252 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
253 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
254 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
255 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
256 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
257
258 AMDGPU_CP_IRQ_LAST
259};
260
261enum amdgpu_thermal_irq {
262 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
263 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
264
265 AMDGPU_THERMAL_IRQ_LAST
266};
267
268enum amdgpu_kiq_irq {
269 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
270 AMDGPU_CP_KIQ_IRQ_LAST
271};
272
273#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
274#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
275#define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
276
277int amdgpu_device_ip_set_clockgating_state(void *dev,
278 enum amd_ip_block_type block_type,
279 enum amd_clockgating_state state);
280int amdgpu_device_ip_set_powergating_state(void *dev,
281 enum amd_ip_block_type block_type,
282 enum amd_powergating_state state);
283void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
284 u32 *flags);
285int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
286 enum amd_ip_block_type block_type);
287bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
288 enum amd_ip_block_type block_type);
289
290#define AMDGPU_MAX_IP_NUM 16
291
292struct amdgpu_ip_block_status {
293 bool valid;
294 bool sw;
295 bool hw;
296 bool late_initialized;
297 bool hang;
298};
299
300struct amdgpu_ip_block_version {
301 const enum amd_ip_block_type type;
302 const u32 major;
303 const u32 minor;
304 const u32 rev;
305 const struct amd_ip_funcs *funcs;
306};
307
308#define HW_REV(_Major, _Minor, _Rev) \
309 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
310
311struct amdgpu_ip_block {
312 struct amdgpu_ip_block_status status;
313 const struct amdgpu_ip_block_version *version;
314};
315
316int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
317 enum amd_ip_block_type type,
318 u32 major, u32 minor);
319
320struct amdgpu_ip_block *
321amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
322 enum amd_ip_block_type type);
323
324int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
325 const struct amdgpu_ip_block_version *ip_block_version);
326
327/*
328 * BIOS.
329 */
330bool amdgpu_get_bios(struct amdgpu_device *adev);
331bool amdgpu_read_bios(struct amdgpu_device *adev);
332
333/*
334 * Clocks
335 */
336
337#define AMDGPU_MAX_PPLL 3
338
339struct amdgpu_clock {
340 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
341 struct amdgpu_pll spll;
342 struct amdgpu_pll mpll;
343 /* 10 Khz units */
344 uint32_t default_mclk;
345 uint32_t default_sclk;
346 uint32_t default_dispclk;
347 uint32_t current_dispclk;
348 uint32_t dp_extclk;
349 uint32_t max_pixel_clock;
350};
351
352/* sub-allocation manager, it has to be protected by another lock.
353 * By conception this is an helper for other part of the driver
354 * like the indirect buffer or semaphore, which both have their
355 * locking.
356 *
357 * Principe is simple, we keep a list of sub allocation in offset
358 * order (first entry has offset == 0, last entry has the highest
359 * offset).
360 *
361 * When allocating new object we first check if there is room at
362 * the end total_size - (last_object_offset + last_object_size) >=
363 * alloc_size. If so we allocate new object there.
364 *
365 * When there is not enough room at the end, we start waiting for
366 * each sub object until we reach object_offset+object_size >=
367 * alloc_size, this object then become the sub object we return.
368 *
369 * Alignment can't be bigger than page size.
370 *
371 * Hole are not considered for allocation to keep things simple.
372 * Assumption is that there won't be hole (all object on same
373 * alignment).
374 */
375
376#define AMDGPU_SA_NUM_FENCE_LISTS 32
377
378struct amdgpu_sa_manager {
379 wait_queue_head_t wq;
380 struct amdgpu_bo *bo;
381 struct list_head *hole;
382 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
383 struct list_head olist;
384 unsigned size;
385 uint64_t gpu_addr;
386 void *cpu_ptr;
387 uint32_t domain;
388 uint32_t align;
389};
390
391/* sub-allocation buffer */
392struct amdgpu_sa_bo {
393 struct list_head olist;
394 struct list_head flist;
395 struct amdgpu_sa_manager *manager;
396 unsigned soffset;
397 unsigned eoffset;
398 struct dma_fence *fence;
399};
400
401int amdgpu_fence_slab_init(void);
402void amdgpu_fence_slab_fini(void);
403
404/*
405 * IRQS.
406 */
407
408struct amdgpu_flip_work {
409 struct delayed_work flip_work;
410 struct work_struct unpin_work;
411 struct amdgpu_device *adev;
412 int crtc_id;
413 u32 target_vblank;
414 uint64_t base;
415 struct drm_pending_vblank_event *event;
416 struct amdgpu_bo *old_abo;
417 struct dma_fence *excl;
418 unsigned shared_count;
419 struct dma_fence **shared;
420 struct dma_fence_cb cb;
421 bool async;
422};
423
424
425/*
426 * CP & rings.
427 */
428
429struct amdgpu_ib {
430 struct amdgpu_sa_bo *sa_bo;
431 uint32_t length_dw;
432 uint64_t gpu_addr;
433 uint32_t *ptr;
434 uint32_t flags;
435};
436
437extern const struct drm_sched_backend_ops amdgpu_sched_ops;
438
439/*
440 * file private structure
441 */
442
443struct amdgpu_fpriv {
444 struct amdgpu_vm vm;
445 struct amdgpu_bo_va *prt_va;
446 struct amdgpu_bo_va *csa_va;
447 struct mutex bo_list_lock;
448 struct idr bo_list_handles;
449 struct amdgpu_ctx_mgr ctx_mgr;
450};
451
452int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
453
454int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
455 unsigned size,
456 enum amdgpu_ib_pool_type pool,
457 struct amdgpu_ib *ib);
458void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
459 struct dma_fence *f);
460int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
461 struct amdgpu_ib *ibs, struct amdgpu_job *job,
462 struct dma_fence **f);
463int amdgpu_ib_pool_init(struct amdgpu_device *adev);
464void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
465int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
466
467/*
468 * CS.
469 */
470struct amdgpu_cs_chunk {
471 uint32_t chunk_id;
472 uint32_t length_dw;
473 void *kdata;
474};
475
476struct amdgpu_cs_post_dep {
477 struct drm_syncobj *syncobj;
478 struct dma_fence_chain *chain;
479 u64 point;
480};
481
482struct amdgpu_cs_parser {
483 struct amdgpu_device *adev;
484 struct drm_file *filp;
485 struct amdgpu_ctx *ctx;
486
487 /* chunks */
488 unsigned nchunks;
489 struct amdgpu_cs_chunk *chunks;
490
491 /* scheduler job object */
492 struct amdgpu_job *job;
493 struct drm_sched_entity *entity;
494
495 /* buffer objects */
496 struct ww_acquire_ctx ticket;
497 struct amdgpu_bo_list *bo_list;
498 struct amdgpu_mn *mn;
499 struct amdgpu_bo_list_entry vm_pd;
500 struct list_head validated;
501 struct dma_fence *fence;
502 uint64_t bytes_moved_threshold;
503 uint64_t bytes_moved_vis_threshold;
504 uint64_t bytes_moved;
505 uint64_t bytes_moved_vis;
506
507 /* user fence */
508 struct amdgpu_bo_list_entry uf_entry;
509
510 unsigned num_post_deps;
511 struct amdgpu_cs_post_dep *post_deps;
512};
513
514static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
515 uint32_t ib_idx, int idx)
516{
517 return p->job->ibs[ib_idx].ptr[idx];
518}
519
520static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
521 uint32_t ib_idx, int idx,
522 uint32_t value)
523{
524 p->job->ibs[ib_idx].ptr[idx] = value;
525}
526
527/*
528 * Writeback
529 */
530#define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */
531
532struct amdgpu_wb {
533 struct amdgpu_bo *wb_obj;
534 volatile uint32_t *wb;
535 uint64_t gpu_addr;
536 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
537 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
538};
539
540int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
541void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
542
543/*
544 * Benchmarking
545 */
546void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
547
548
549/*
550 * Testing
551 */
552void amdgpu_test_moves(struct amdgpu_device *adev);
553
554/*
555 * ASIC specific register table accessible by UMD
556 */
557struct amdgpu_allowed_register_entry {
558 uint32_t reg_offset;
559 bool grbm_indexed;
560};
561
562enum amd_reset_method {
563 AMD_RESET_METHOD_LEGACY = 0,
564 AMD_RESET_METHOD_MODE0,
565 AMD_RESET_METHOD_MODE1,
566 AMD_RESET_METHOD_MODE2,
567 AMD_RESET_METHOD_BACO
568};
569
570/*
571 * ASIC specific functions.
572 */
573struct amdgpu_asic_funcs {
574 bool (*read_disabled_bios)(struct amdgpu_device *adev);
575 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
576 u8 *bios, u32 length_bytes);
577 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
578 u32 sh_num, u32 reg_offset, u32 *value);
579 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
580 int (*reset)(struct amdgpu_device *adev);
581 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
582 /* get the reference clock */
583 u32 (*get_xclk)(struct amdgpu_device *adev);
584 /* MM block clocks */
585 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
586 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
587 /* static power management */
588 int (*get_pcie_lanes)(struct amdgpu_device *adev);
589 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
590 /* get config memsize register */
591 u32 (*get_config_memsize)(struct amdgpu_device *adev);
592 /* flush hdp write queue */
593 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
594 /* invalidate hdp read cache */
595 void (*invalidate_hdp)(struct amdgpu_device *adev,
596 struct amdgpu_ring *ring);
597 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev);
598 /* check if the asic needs a full reset of if soft reset will work */
599 bool (*need_full_reset)(struct amdgpu_device *adev);
600 /* initialize doorbell layout for specific asic*/
601 void (*init_doorbell_index)(struct amdgpu_device *adev);
602 /* PCIe bandwidth usage */
603 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
604 uint64_t *count1);
605 /* do we need to reset the asic at init time (e.g., kexec) */
606 bool (*need_reset_on_init)(struct amdgpu_device *adev);
607 /* PCIe replay counter */
608 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
609 /* device supports BACO */
610 bool (*supports_baco)(struct amdgpu_device *adev);
611};
612
613/*
614 * IOCTL.
615 */
616int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
617 struct drm_file *filp);
618
619int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
620int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
621 struct drm_file *filp);
622int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
623int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
624 struct drm_file *filp);
625
626/* VRAM scratch page for HDP bug, default vram page */
627struct amdgpu_vram_scratch {
628 struct amdgpu_bo *robj;
629 volatile uint32_t *ptr;
630 u64 gpu_addr;
631};
632
633/*
634 * ACPI
635 */
636struct amdgpu_atcs_functions {
637 bool get_ext_state;
638 bool pcie_perf_req;
639 bool pcie_dev_rdy;
640 bool pcie_bus_width;
641};
642
643struct amdgpu_atcs {
644 struct amdgpu_atcs_functions functions;
645};
646
647/*
648 * Firmware VRAM reservation
649 */
650struct amdgpu_fw_vram_usage {
651 u64 start_offset;
652 u64 size;
653 struct amdgpu_bo *reserved_bo;
654 void *va;
655
656 /* GDDR6 training support flag.
657 */
658 bool mem_train_support;
659};
660
661/*
662 * CGS
663 */
664struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
665void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
666
667/*
668 * Core structure, functions and helpers.
669 */
670typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
671typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
672
673typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
674typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
675
676typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
677typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
678
679struct amdgpu_mmio_remap {
680 u32 reg_offset;
681 resource_size_t bus_addr;
682};
683
684/* Define the HW IP blocks will be used in driver , add more if necessary */
685enum amd_hw_ip_block_type {
686 GC_HWIP = 1,
687 HDP_HWIP,
688 SDMA0_HWIP,
689 SDMA1_HWIP,
690 SDMA2_HWIP,
691 SDMA3_HWIP,
692 SDMA4_HWIP,
693 SDMA5_HWIP,
694 SDMA6_HWIP,
695 SDMA7_HWIP,
696 MMHUB_HWIP,
697 ATHUB_HWIP,
698 NBIO_HWIP,
699 MP0_HWIP,
700 MP1_HWIP,
701 UVD_HWIP,
702 VCN_HWIP = UVD_HWIP,
703 JPEG_HWIP = VCN_HWIP,
704 VCE_HWIP,
705 DF_HWIP,
706 DCE_HWIP,
707 OSSSYS_HWIP,
708 SMUIO_HWIP,
709 PWR_HWIP,
710 NBIF_HWIP,
711 THM_HWIP,
712 CLK_HWIP,
713 UMC_HWIP,
714 RSMU_HWIP,
715 MAX_HWIP
716};
717
718#define HWIP_MAX_INSTANCE 8
719
720struct amd_powerplay {
721 void *pp_handle;
722 const struct amd_pm_funcs *pp_funcs;
723};
724
725#define AMDGPU_RESET_MAGIC_NUM 64
726#define AMDGPU_MAX_DF_PERFMONS 4
727struct amdgpu_device {
728 struct device *dev;
729 struct drm_device *ddev;
730 struct pci_dev *pdev;
731
732#ifdef CONFIG_DRM_AMD_ACP
733 struct amdgpu_acp acp;
734#endif
735
736 /* ASIC */
737 enum amd_asic_type asic_type;
738 uint32_t family;
739 uint32_t rev_id;
740 uint32_t external_rev_id;
741 unsigned long flags;
742 unsigned long apu_flags;
743 int usec_timeout;
744 const struct amdgpu_asic_funcs *asic_funcs;
745 bool shutdown;
746 bool need_swiotlb;
747 bool accel_working;
748 struct notifier_block acpi_nb;
749 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
750 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
751 unsigned debugfs_count;
752#if defined(CONFIG_DEBUG_FS)
753 struct dentry *debugfs_preempt;
754 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
755#endif
756 struct amdgpu_atif *atif;
757 struct amdgpu_atcs atcs;
758 struct mutex srbm_mutex;
759 /* GRBM index mutex. Protects concurrent access to GRBM index */
760 struct mutex grbm_idx_mutex;
761 struct dev_pm_domain vga_pm_domain;
762 bool have_disp_power_ref;
763 bool have_atomics_support;
764
765 /* BIOS */
766 bool is_atom_fw;
767 uint8_t *bios;
768 uint32_t bios_size;
769 struct amdgpu_bo *stolen_vga_memory;
770 uint32_t bios_scratch_reg_offset;
771 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
772
773 /* Register/doorbell mmio */
774 resource_size_t rmmio_base;
775 resource_size_t rmmio_size;
776 void __iomem *rmmio;
777 /* protects concurrent MM_INDEX/DATA based register access */
778 spinlock_t mmio_idx_lock;
779 struct amdgpu_mmio_remap rmmio_remap;
780 /* protects concurrent SMC based register access */
781 spinlock_t smc_idx_lock;
782 amdgpu_rreg_t smc_rreg;
783 amdgpu_wreg_t smc_wreg;
784 /* protects concurrent PCIE register access */
785 spinlock_t pcie_idx_lock;
786 amdgpu_rreg_t pcie_rreg;
787 amdgpu_wreg_t pcie_wreg;
788 amdgpu_rreg_t pciep_rreg;
789 amdgpu_wreg_t pciep_wreg;
790 amdgpu_rreg64_t pcie_rreg64;
791 amdgpu_wreg64_t pcie_wreg64;
792 /* protects concurrent UVD register access */
793 spinlock_t uvd_ctx_idx_lock;
794 amdgpu_rreg_t uvd_ctx_rreg;
795 amdgpu_wreg_t uvd_ctx_wreg;
796 /* protects concurrent DIDT register access */
797 spinlock_t didt_idx_lock;
798 amdgpu_rreg_t didt_rreg;
799 amdgpu_wreg_t didt_wreg;
800 /* protects concurrent gc_cac register access */
801 spinlock_t gc_cac_idx_lock;
802 amdgpu_rreg_t gc_cac_rreg;
803 amdgpu_wreg_t gc_cac_wreg;
804 /* protects concurrent se_cac register access */
805 spinlock_t se_cac_idx_lock;
806 amdgpu_rreg_t se_cac_rreg;
807 amdgpu_wreg_t se_cac_wreg;
808 /* protects concurrent ENDPOINT (audio) register access */
809 spinlock_t audio_endpt_idx_lock;
810 amdgpu_block_rreg_t audio_endpt_rreg;
811 amdgpu_block_wreg_t audio_endpt_wreg;
812 void __iomem *rio_mem;
813 resource_size_t rio_mem_size;
814 struct amdgpu_doorbell doorbell;
815
816 /* clock/pll info */
817 struct amdgpu_clock clock;
818
819 /* MC */
820 struct amdgpu_gmc gmc;
821 struct amdgpu_gart gart;
822 dma_addr_t dummy_page_addr;
823 struct amdgpu_vm_manager vm_manager;
824 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
825 unsigned num_vmhubs;
826
827 /* memory management */
828 struct amdgpu_mman mman;
829 struct amdgpu_vram_scratch vram_scratch;
830 struct amdgpu_wb wb;
831 atomic64_t num_bytes_moved;
832 atomic64_t num_evictions;
833 atomic64_t num_vram_cpu_page_faults;
834 atomic_t gpu_reset_counter;
835 atomic_t vram_lost_counter;
836
837 /* data for buffer migration throttling */
838 struct {
839 spinlock_t lock;
840 s64 last_update_us;
841 s64 accum_us; /* accumulated microseconds */
842 s64 accum_us_vis; /* for visible VRAM */
843 u32 log2_max_MBps;
844 } mm_stats;
845
846 /* display */
847 bool enable_virtual_display;
848 struct amdgpu_mode_info mode_info;
849 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
850 struct work_struct hotplug_work;
851 struct amdgpu_irq_src crtc_irq;
852 struct amdgpu_irq_src vupdate_irq;
853 struct amdgpu_irq_src pageflip_irq;
854 struct amdgpu_irq_src hpd_irq;
855
856 /* rings */
857 u64 fence_context;
858 unsigned num_rings;
859 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
860 bool ib_pool_ready;
861 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
862 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
863
864 /* interrupts */
865 struct amdgpu_irq irq;
866
867 /* powerplay */
868 struct amd_powerplay powerplay;
869 bool pp_force_state_enabled;
870
871 /* smu */
872 struct smu_context smu;
873
874 /* dpm */
875 struct amdgpu_pm pm;
876 u32 cg_flags;
877 u32 pg_flags;
878
879 /* nbio */
880 struct amdgpu_nbio nbio;
881
882 /* mmhub */
883 struct amdgpu_mmhub mmhub;
884
885 /* gfx */
886 struct amdgpu_gfx gfx;
887
888 /* sdma */
889 struct amdgpu_sdma sdma;
890
891 /* uvd */
892 struct amdgpu_uvd uvd;
893
894 /* vce */
895 struct amdgpu_vce vce;
896
897 /* vcn */
898 struct amdgpu_vcn vcn;
899
900 /* jpeg */
901 struct amdgpu_jpeg jpeg;
902
903 /* firmwares */
904 struct amdgpu_firmware firmware;
905
906 /* PSP */
907 struct psp_context psp;
908
909 /* GDS */
910 struct amdgpu_gds gds;
911
912 /* KFD */
913 struct amdgpu_kfd_dev kfd;
914
915 /* UMC */
916 struct amdgpu_umc umc;
917
918 /* display related functionality */
919 struct amdgpu_display_manager dm;
920
921 /* discovery */
922 uint8_t *discovery_bin;
923 uint32_t discovery_tmr_size;
924 struct amdgpu_bo *discovery_memory;
925
926 /* mes */
927 bool enable_mes;
928 struct amdgpu_mes mes;
929
930 /* df */
931 struct amdgpu_df df;
932
933 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
934 int num_ip_blocks;
935 struct mutex mn_lock;
936 DECLARE_HASHTABLE(mn_hash, 7);
937
938 /* tracking pinned memory */
939 atomic64_t vram_pin_size;
940 atomic64_t visible_pin_size;
941 atomic64_t gart_pin_size;
942
943 /* soc15 register offset based on ip, instance and segment */
944 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
945
946 /* delayed work_func for deferring clockgating during resume */
947 struct delayed_work delayed_init_work;
948
949 struct amdgpu_virt virt;
950 /* firmware VRAM reservation */
951 struct amdgpu_fw_vram_usage fw_vram_usage;
952
953 /* link all shadow bo */
954 struct list_head shadow_list;
955 struct mutex shadow_list_lock;
956
957 /* record hw reset is performed */
958 bool has_hw_reset;
959 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
960
961 /* s3/s4 mask */
962 bool in_suspend;
963 bool in_hibernate;
964
965 bool in_gpu_reset;
966 enum pp_mp1_state mp1_state;
967 struct mutex lock_reset;
968 struct amdgpu_doorbell_index doorbell_index;
969
970 struct mutex notifier_lock;
971
972 int asic_reset_res;
973 struct work_struct xgmi_reset_work;
974
975 long gfx_timeout;
976 long sdma_timeout;
977 long video_timeout;
978 long compute_timeout;
979
980 uint64_t unique_id;
981 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
982
983 /* enable runtime pm on the device */
984 bool runpm;
985 bool in_runpm;
986
987 bool pm_sysfs_en;
988 bool ucode_sysfs_en;
989
990 /* Chip product information */
991 char product_number[16];
992 char product_name[32];
993 char serial[16];
994
995 struct amdgpu_autodump autodump;
996};
997
998static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
999{
1000 return container_of(bdev, struct amdgpu_device, mman.bdev);
1001}
1002
1003int amdgpu_device_init(struct amdgpu_device *adev,
1004 struct drm_device *ddev,
1005 struct pci_dev *pdev,
1006 uint32_t flags);
1007void amdgpu_device_fini(struct amdgpu_device *adev);
1008int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1009
1010void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1011 uint32_t *buf, size_t size, bool write);
1012uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,
1013 uint32_t acc_flags);
1014void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1015 uint32_t acc_flags);
1016void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1017 uint32_t acc_flags);
1018void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1019uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1020
1021u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1022void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1023
1024bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1025bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1026
1027int emu_soc_asic_init(struct amdgpu_device *adev);
1028
1029/*
1030 * Registers read & write functions.
1031 */
1032#define AMDGPU_REGS_NO_KIQ (1<<1)
1033
1034#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1035#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1036
1037#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1038#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1039
1040#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1041#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1042
1043#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1044#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1045#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1046#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1047#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1048#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1049#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1050#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1051#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1052#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1053#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1054#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1055#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1056#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1057#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1058#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1059#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1060#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1061#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1062#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1063#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1064#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1065#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1066#define WREG32_P(reg, val, mask) \
1067 do { \
1068 uint32_t tmp_ = RREG32(reg); \
1069 tmp_ &= (mask); \
1070 tmp_ |= ((val) & ~(mask)); \
1071 WREG32(reg, tmp_); \
1072 } while (0)
1073#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1074#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1075#define WREG32_PLL_P(reg, val, mask) \
1076 do { \
1077 uint32_t tmp_ = RREG32_PLL(reg); \
1078 tmp_ &= (mask); \
1079 tmp_ |= ((val) & ~(mask)); \
1080 WREG32_PLL(reg, tmp_); \
1081 } while (0)
1082#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1083#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1084#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1085
1086#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1087#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1088
1089#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1090 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1091 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1092
1093#define REG_GET_FIELD(value, reg, field) \
1094 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1095
1096#define WREG32_FIELD(reg, field, val) \
1097 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1098
1099#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1100 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1101
1102/*
1103 * BIOS helpers.
1104 */
1105#define RBIOS8(i) (adev->bios[i])
1106#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1107#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1108
1109/*
1110 * ASICs macro.
1111 */
1112#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1113#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1114#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1115#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1116#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1117#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1118#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1119#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1120#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1121#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1122#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1123#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1124#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1125#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1126#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
1127#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1128#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1129#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1130#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1131#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1132#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1133
1134#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1135
1136/* Common functions */
1137bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1138int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1139 struct amdgpu_job* job);
1140void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1141bool amdgpu_device_need_post(struct amdgpu_device *adev);
1142
1143void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1144 u64 num_vis_bytes);
1145int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1146void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1147 const u32 *registers,
1148 const u32 array_size);
1149
1150bool amdgpu_device_supports_boco(struct drm_device *dev);
1151bool amdgpu_device_supports_baco(struct drm_device *dev);
1152bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1153 struct amdgpu_device *peer_adev);
1154int amdgpu_device_baco_enter(struct drm_device *dev);
1155int amdgpu_device_baco_exit(struct drm_device *dev);
1156
1157/* atpx handler */
1158#if defined(CONFIG_VGA_SWITCHEROO)
1159void amdgpu_register_atpx_handler(void);
1160void amdgpu_unregister_atpx_handler(void);
1161bool amdgpu_has_atpx_dgpu_power_cntl(void);
1162bool amdgpu_is_atpx_hybrid(void);
1163bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1164bool amdgpu_has_atpx(void);
1165#else
1166static inline void amdgpu_register_atpx_handler(void) {}
1167static inline void amdgpu_unregister_atpx_handler(void) {}
1168static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1169static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1170static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1171static inline bool amdgpu_has_atpx(void) { return false; }
1172#endif
1173
1174#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1175void *amdgpu_atpx_get_dhandle(void);
1176#else
1177static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1178#endif
1179
1180/*
1181 * KMS
1182 */
1183extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1184extern const int amdgpu_max_kms_ioctl;
1185
1186int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
1187void amdgpu_driver_unload_kms(struct drm_device *dev);
1188void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1189int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1190void amdgpu_driver_postclose_kms(struct drm_device *dev,
1191 struct drm_file *file_priv);
1192int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1193int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1194int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1195u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1196int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1197void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1198long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1199 unsigned long arg);
1200
1201/*
1202 * functions used by amdgpu_encoder.c
1203 */
1204struct amdgpu_afmt_acr {
1205 u32 clock;
1206
1207 int n_32khz;
1208 int cts_32khz;
1209
1210 int n_44_1khz;
1211 int cts_44_1khz;
1212
1213 int n_48khz;
1214 int cts_48khz;
1215
1216};
1217
1218struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1219
1220/* amdgpu_acpi.c */
1221#if defined(CONFIG_ACPI)
1222int amdgpu_acpi_init(struct amdgpu_device *adev);
1223void amdgpu_acpi_fini(struct amdgpu_device *adev);
1224bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1225int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1226 u8 perf_req, bool advertise);
1227int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1228
1229void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1230 struct amdgpu_dm_backlight_caps *caps);
1231#else
1232static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1233static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1234#endif
1235
1236int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1237 uint64_t addr, struct amdgpu_bo **bo,
1238 struct amdgpu_bo_va_mapping **mapping);
1239
1240#if defined(CONFIG_DRM_AMD_DC)
1241int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1242#else
1243static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1244#endif
1245
1246
1247void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1248void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1249
1250#include "amdgpu_object.h"
1251
1252/* used by df_v3_6.c and amdgpu_pmu.c */
1253#define AMDGPU_PMU_ATTR(_name, _object) \
1254static ssize_t \
1255_name##_show(struct device *dev, \
1256 struct device_attribute *attr, \
1257 char *page) \
1258{ \
1259 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \
1260 return sprintf(page, _object "\n"); \
1261} \
1262 \
1263static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
1264
1265static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1266{
1267 return adev->gmc.tmz_enabled;
1268}
1269
1270#endif