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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Contains register definitions common to the Book E PowerPC
4 * specification. Notice that while the IBM-40x series of CPUs
5 * are not true Book E PowerPCs, they borrowed a number of features
6 * before Book E was finalized, and are included here as well. Unfortunately,
7 * they sometimes used different locations than true Book E CPUs did.
8 *
9 * Copyright 2009-2010 Freescale Semiconductor, Inc.
10 */
11#ifdef __KERNEL__
12#ifndef __ASM_POWERPC_REG_BOOKE_H__
13#define __ASM_POWERPC_REG_BOOKE_H__
14
15#include <asm/ppc-opcode.h>
16
17/* Machine State Register (MSR) Fields */
18#define MSR_GS_LG 28 /* Guest state */
19#define MSR_UCLE_LG 26 /* User-mode cache lock enable */
20#define MSR_SPE_LG 25 /* Enable SPE */
21#define MSR_DWE_LG 10 /* Debug Wait Enable */
22#define MSR_UBLE_LG 10 /* BTB lock enable (e500) */
23#define MSR_IS_LG MSR_IR_LG /* Instruction Space */
24#define MSR_DS_LG MSR_DR_LG /* Data Space */
25#define MSR_PMM_LG 2 /* Performance monitor mark bit */
26#define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
27
28#define MSR_GS __MASK(MSR_GS_LG)
29#define MSR_UCLE __MASK(MSR_UCLE_LG)
30#define MSR_SPE __MASK(MSR_SPE_LG)
31#define MSR_DWE __MASK(MSR_DWE_LG)
32#define MSR_UBLE __MASK(MSR_UBLE_LG)
33#define MSR_IS __MASK(MSR_IS_LG)
34#define MSR_DS __MASK(MSR_DS_LG)
35#define MSR_PMM __MASK(MSR_PMM_LG)
36#define MSR_CM __MASK(MSR_CM_LG)
37
38#if defined(CONFIG_PPC_BOOK3E_64)
39#define MSR_64BIT MSR_CM
40
41#define MSR_ (MSR_ME | MSR_RI | MSR_CE)
42#define MSR_KERNEL (MSR_ | MSR_64BIT)
43#define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
44#define MSR_USER64 (MSR_USER32 | MSR_64BIT)
45#elif defined (CONFIG_40x)
46#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
47#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
48#else
49#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE)
50#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
51#endif
52
53/* Special Purpose Registers (SPRNs)*/
54#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
55#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
56#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
57#define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */
58#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
59#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
60#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
61#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
62#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
63#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
64#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
65#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
66#define SPRN_EPCR 0x133 /* Embedded Processor Control Register */
67#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
68#define SPRN_DBCR4 0x233 /* Debug Control Register 4 */
69#define SPRN_MSRP 0x137 /* MSR Protect Register */
70#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
71#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
72#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
73#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
74#define SPRN_LPID 0x152 /* Logical Partition ID */
75#define SPRN_MAS8 0x155 /* MMU Assist Register 8 */
76#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */
77#define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */
78#define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */
79#define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */
80#define SPRN_EPTCFG 0x15e /* Embedded Page Table Config */
81#define SPRN_GSPRG0 0x170 /* Guest SPRG0 */
82#define SPRN_GSPRG1 0x171 /* Guest SPRG1 */
83#define SPRN_GSPRG2 0x172 /* Guest SPRG2 */
84#define SPRN_GSPRG3 0x173 /* Guest SPRG3 */
85#define SPRN_MAS7_MAS3 0x174 /* MMU Assist Register 7 || 3 */
86#define SPRN_MAS0_MAS1 0x175 /* MMU Assist Register 0 || 1 */
87#define SPRN_GSRR0 0x17A /* Guest SRR0 */
88#define SPRN_GSRR1 0x17B /* Guest SRR1 */
89#define SPRN_GEPR 0x17C /* Guest EPR */
90#define SPRN_GDEAR 0x17D /* Guest DEAR */
91#define SPRN_GPIR 0x17E /* Guest PIR */
92#define SPRN_GESR 0x17F /* Guest Exception Syndrome Register */
93#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
94#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
95#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
96#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
97#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
98#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
99#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
100#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
101#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
102#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
103#define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */
104#define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */
105#define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */
106#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
107#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
108#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
109#define SPRN_IVOR38 0x1B0 /* Interrupt Vector Offset Register 38 */
110#define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 */
111#define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 */
112#define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 */
113#define SPRN_IVOR42 0x1B4 /* Interrupt Vector Offset Register 42 */
114#define SPRN_GIVOR2 0x1B8 /* Guest IVOR2 */
115#define SPRN_GIVOR3 0x1B9 /* Guest IVOR3 */
116#define SPRN_GIVOR4 0x1BA /* Guest IVOR4 */
117#define SPRN_GIVOR8 0x1BB /* Guest IVOR8 */
118#define SPRN_GIVOR13 0x1BC /* Guest IVOR13 */
119#define SPRN_GIVOR14 0x1BD /* Guest IVOR14 */
120#define SPRN_GIVPR 0x1BF /* Guest IVPR */
121#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
122#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
123#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
124#define SPRN_L1CFG0 0x203 /* L1 Cache Configure Register 0 */
125#define SPRN_L1CFG1 0x204 /* L1 Cache Configure Register 1 */
126#define SPRN_ATB 0x20E /* Alternate Time Base */
127#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
128#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
129#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
130#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
131#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
132#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
133#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
134#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
135#define SPRN_MCARU 0x239 /* Machine Check Address Register Upper */
136#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
137#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
138#define SPRN_MCSR 0x23C /* Machine Check Status Register */
139#define SPRN_MCAR 0x23D /* Machine Check Address Register */
140#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
141#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
142#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
143#define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */
144#define SPRN_L1CSR2 0x25E /* L1 Cache Control and Status Register 2 */
145#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
146#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
147#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
148#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
149#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
150#define SPRN_MAS5 0x153 /* MMU Assist Register 5 */
151#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
152#define SPRN_PID1 0x279 /* Process ID Register 1 */
153#define SPRN_PID2 0x27A /* Process ID Register 2 */
154#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
155#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
156#define SPRN_TLB2CFG 0x2B2 /* TLB 2 Config Register */
157#define SPRN_TLB3CFG 0x2B3 /* TLB 3 Config Register */
158#define SPRN_EPR 0x2BE /* External Proxy Register */
159#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
160#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
161#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
162#define SPRN_MMUCR 0x3B2 /* MMU Control Register */
163#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
164#define SPRN_EPLC 0x3B3 /* External Process ID Load Context */
165#define SPRN_EPSC 0x3B4 /* External Process ID Store Context */
166#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
167#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
168#define SPRN_SLER 0x3BB /* Little-endian real mode */
169#define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */
170#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
171#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
172#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
173#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
174#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
175#define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */
176#define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */
177#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
178#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
179#define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */
180#define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */
181#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
182#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
183#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */
184#define SPRN_SVR 0x3FF /* System Version Register */
185
186/*
187 * SPRs which have conflicting definitions on true Book E versus classic,
188 * or IBM 40x.
189 */
190#ifdef CONFIG_BOOKE
191#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */
192#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */
193#define SPRN_DEAR 0x03D /* Data Error Address Register */
194#define SPRN_ESR 0x03E /* Exception Syndrome Register */
195#define SPRN_PIR 0x11E /* Processor Identification Register */
196#define SPRN_DBSR 0x130 /* Debug Status Register */
197#define SPRN_DBCR0 0x134 /* Debug Control Register 0 */
198#define SPRN_DBCR1 0x135 /* Debug Control Register 1 */
199#define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */
200#define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */
201#define SPRN_DAC1 0x13C /* Data Address Compare 1 */
202#define SPRN_DAC2 0x13D /* Data Address Compare 2 */
203#define SPRN_TSR 0x150 /* Timer Status Register */
204#define SPRN_TCR 0x154 /* Timer Control Register */
205#endif /* Book E */
206#ifdef CONFIG_40x
207#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
208#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
209#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
210#define SPRN_TSR 0x3D8 /* Timer Status Register */
211#define SPRN_TCR 0x3DA /* Timer Control Register */
212#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
213#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
214#define SPRN_DBSR 0x3F0 /* Debug Status Register */
215#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
216#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
217#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
218#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */
219#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
220#endif
221#define SPRN_HACOP 0x15F /* Hypervisor Available Coprocessor Register */
222
223/* Bit definitions for CCR1. */
224#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
225#define CCR1_TCS 0x00000080 /* Timer Clock Select */
226
227/* Bit definitions for PWRMGTCR0. */
228#define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */
229#define PWRMGTCR0_PW20_ENT_SHIFT 8
230#define PWRMGTCR0_PW20_ENT 0x3F00
231#define PWRMGTCR0_AV_IDLE_PD_EN (1 << 22) /* Altivec idle enable */
232#define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16
233#define PWRMGTCR0_AV_IDLE_CNT 0x3F0000
234
235/* Bit definitions for the MCSR. */
236#define MCSR_MCS 0x80000000 /* Machine Check Summary */
237#define MCSR_IB 0x40000000 /* Instruction PLB Error */
238#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
239#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
240#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
241#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
242#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
243#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
244#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
245
246#define PPC47x_MCSR_GPR 0x01000000 /* GPR parity error */
247#define PPC47x_MCSR_FPR 0x00800000 /* FPR parity error */
248#define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */
249
250#ifdef CONFIG_E500
251/* All e500 */
252#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
253#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
254
255/* e500v1/v2 */
256#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
257#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
258#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */
259#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */
260#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */
261#define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */
262#define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */
263#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */
264#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
265#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
266
267/* e500mc */
268#define MCSR_DCPERR_MC 0x20000000UL /* D-Cache Parity Error */
269#define MCSR_L2MMU_MHIT 0x08000000UL /* Hit on multiple TLB entries */
270#define MCSR_NMI 0x00100000UL /* Non-Maskable Interrupt */
271#define MCSR_MAV 0x00080000UL /* MCAR address valid */
272#define MCSR_MEA 0x00040000UL /* MCAR is effective address */
273#define MCSR_IF 0x00010000UL /* Instruction Fetch */
274#define MCSR_LD 0x00008000UL /* Load */
275#define MCSR_ST 0x00004000UL /* Store */
276#define MCSR_LDG 0x00002000UL /* Guarded Load */
277#define MCSR_TLBSYNC 0x00000002UL /* Multiple tlbsyncs detected */
278#define MCSR_BSL2_ERR 0x00000001UL /* Backside L2 cache error */
279
280#define MSRP_UCLEP 0x04000000 /* Protect MSR[UCLE] */
281#define MSRP_DEP 0x00000200 /* Protect MSR[DE] */
282#define MSRP_PMMP 0x00000004 /* Protect MSR[PMM] */
283#endif
284
285#ifdef CONFIG_E200
286#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
287#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */
288#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */
289#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
290 fetch for an exception handler */
291#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/
292#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
293#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
294 store or cache line push */
295#endif
296
297/* Bit definitions for the HID1 */
298#ifdef CONFIG_E500
299/* e500v1/v2 */
300#define HID1_PLL_CFG_MASK 0xfc000000 /* PLL_CFG input pins */
301#define HID1_RFXE 0x00020000 /* Read fault exception enable */
302#define HID1_R1DPE 0x00008000 /* R1 data bus parity enable */
303#define HID1_R2DPE 0x00004000 /* R2 data bus parity enable */
304#define HID1_ASTME 0x00002000 /* Address bus streaming mode enable */
305#define HID1_ABE 0x00001000 /* Address broadcast enable */
306#define HID1_MPXTT 0x00000400 /* MPX re-map transfer type */
307#define HID1_ATS 0x00000080 /* Atomic status */
308#define HID1_MID_MASK 0x0000000f /* MID input pins */
309#endif
310
311/* Bit definitions for the DBSR. */
312/*
313 * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
314 */
315#ifdef CONFIG_BOOKE
316#define DBSR_IDE 0x80000000 /* Imprecise Debug Event */
317#define DBSR_MRR 0x30000000 /* Most Recent Reset */
318#define DBSR_IC 0x08000000 /* Instruction Completion */
319#define DBSR_BT 0x04000000 /* Branch Taken */
320#define DBSR_IRPT 0x02000000 /* Exception Debug Event */
321#define DBSR_TIE 0x01000000 /* Trap Instruction Event */
322#define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */
323#define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */
324#define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */
325#define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */
326#define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */
327#define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */
328#define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */
329#define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */
330#define DBSR_RET 0x00008000 /* Return Debug Event */
331#define DBSR_CIRPT 0x00000040 /* Critical Interrupt Taken Event */
332#define DBSR_CRET 0x00000020 /* Critical Return Debug Event */
333#define DBSR_IAC12ATS 0x00000002 /* Instr Address Compare 1/2 Toggle */
334#define DBSR_IAC34ATS 0x00000001 /* Instr Address Compare 3/4 Toggle */
335#endif
336#ifdef CONFIG_40x
337#define DBSR_IC 0x80000000 /* Instruction Completion */
338#define DBSR_BT 0x40000000 /* Branch taken */
339#define DBSR_IRPT 0x20000000 /* Exception Debug Event */
340#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */
341#define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */
342#define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */
343#define DBSR_IAC3 0x00080000 /* Instruction Address Compare 3 Event */
344#define DBSR_IAC4 0x00040000 /* Instruction Address Compare 4 Event */
345#define DBSR_DAC1R 0x01000000 /* Data Address Compare 1 Read Event */
346#define DBSR_DAC1W 0x00800000 /* Data Address Compare 1 Write Event */
347#define DBSR_DAC2R 0x00400000 /* Data Address Compare 2 Read Event */
348#define DBSR_DAC2W 0x00200000 /* Data Address Compare 2 Write Event */
349#endif
350
351/* Bit definitions related to the ESR. */
352#define ESR_MCI 0x80000000 /* Machine Check - Instruction */
353#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
354#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
355#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
356#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
357#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
358#define ESR_PPR 0x04000000 /* Program Exception - Privileged */
359#define ESR_PTR 0x02000000 /* Program Exception - Trap */
360#define ESR_FP 0x01000000 /* Floating Point Operation */
361#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
362#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
363#define ESR_ST 0x00800000 /* Store Operation */
364#define ESR_DLK 0x00200000 /* Data Cache Locking */
365#define ESR_ILK 0x00100000 /* Instr. Cache Locking */
366#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */
367#define ESR_BO 0x00020000 /* Byte Ordering */
368#define ESR_SPV 0x00000080 /* Signal Processing operation */
369
370/* Bit definitions related to the DBCR0. */
371#if defined(CONFIG_40x)
372#define DBCR0_EDM 0x80000000 /* External Debug Mode */
373#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
374#define DBCR0_RST 0x30000000 /* all the bits in the RST field */
375#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
376#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
377#define DBCR0_RST_CORE 0x10000000 /* Core Reset */
378#define DBCR0_RST_NONE 0x00000000 /* No Reset */
379#define DBCR0_IC 0x08000000 /* Instruction Completion */
380#define DBCR0_ICMP DBCR0_IC
381#define DBCR0_BT 0x04000000 /* Branch Taken */
382#define DBCR0_BRT DBCR0_BT
383#define DBCR0_EDE 0x02000000 /* Exception Debug Event */
384#define DBCR0_IRPT DBCR0_EDE
385#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */
386#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */
387#define DBCR0_IAC1 DBCR0_IA1
388#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */
389#define DBCR0_IAC2 DBCR0_IA2
390#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */
391#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */
392#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */
393#define DBCR0_IAC3 DBCR0_IA3
394#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */
395#define DBCR0_IAC4 DBCR0_IA4
396#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */
397#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */
398#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */
399#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
400#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
401
402#define dbcr_iac_range(task) ((task)->thread.debug.dbcr0)
403#define DBCR_IAC12I DBCR0_IA12 /* Range Inclusive */
404#define DBCR_IAC12X (DBCR0_IA12 | DBCR0_IA12X) /* Range Exclusive */
405#define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X) /* IAC 1-2 Mode Bits */
406#define DBCR_IAC34I DBCR0_IA34 /* Range Inclusive */
407#define DBCR_IAC34X (DBCR0_IA34 | DBCR0_IA34X) /* Range Exclusive */
408#define DBCR_IAC34MODE (DBCR0_IA34 | DBCR0_IA34X) /* IAC 3-4 Mode Bits */
409
410/* Bit definitions related to the DBCR1. */
411#define DBCR1_DAC1R 0x80000000 /* DAC1 Read Debug Event */
412#define DBCR1_DAC2R 0x40000000 /* DAC2 Read Debug Event */
413#define DBCR1_DAC1W 0x20000000 /* DAC1 Write Debug Event */
414#define DBCR1_DAC2W 0x10000000 /* DAC2 Write Debug Event */
415
416#define dbcr_dac(task) ((task)->thread.debug.dbcr1)
417#define DBCR_DAC1R DBCR1_DAC1R
418#define DBCR_DAC1W DBCR1_DAC1W
419#define DBCR_DAC2R DBCR1_DAC2R
420#define DBCR_DAC2W DBCR1_DAC2W
421
422/*
423 * Are there any active Debug Events represented in the
424 * Debug Control Registers?
425 */
426#define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
427 DBCR0_IAC3 | DBCR0_IAC4)
428#define DBCR1_ACTIVE_EVENTS (DBCR1_DAC1R | DBCR1_DAC2R | \
429 DBCR1_DAC1W | DBCR1_DAC2W)
430#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
431 ((dbcr1) & DBCR1_ACTIVE_EVENTS))
432
433#elif defined(CONFIG_BOOKE)
434#define DBCR0_EDM 0x80000000 /* External Debug Mode */
435#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
436#define DBCR0_RST 0x30000000 /* all the bits in the RST field */
437/* DBCR0_RST_* is 44x specific and not followed in fsl booke */
438#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
439#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
440#define DBCR0_RST_CORE 0x10000000 /* Core Reset */
441#define DBCR0_RST_NONE 0x00000000 /* No Reset */
442#define DBCR0_ICMP 0x08000000 /* Instruction Completion */
443#define DBCR0_IC DBCR0_ICMP
444#define DBCR0_BRT 0x04000000 /* Branch Taken */
445#define DBCR0_BT DBCR0_BRT
446#define DBCR0_IRPT 0x02000000 /* Exception Debug Event */
447#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */
448#define DBCR0_TIE DBCR0_TDE
449#define DBCR0_IAC1 0x00800000 /* Instr Addr compare 1 enable */
450#define DBCR0_IAC2 0x00400000 /* Instr Addr compare 2 enable */
451#define DBCR0_IAC3 0x00200000 /* Instr Addr compare 3 enable */
452#define DBCR0_IAC4 0x00100000 /* Instr Addr compare 4 enable */
453#define DBCR0_DAC1R 0x00080000 /* DAC 1 Read enable */
454#define DBCR0_DAC1W 0x00040000 /* DAC 1 Write enable */
455#define DBCR0_DAC2R 0x00020000 /* DAC 2 Read enable */
456#define DBCR0_DAC2W 0x00010000 /* DAC 2 Write enable */
457#define DBCR0_RET 0x00008000 /* Return Debug Event */
458#define DBCR0_CIRPT 0x00000040 /* Critical Interrupt Taken Event */
459#define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */
460#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
461
462#define dbcr_dac(task) ((task)->thread.debug.dbcr0)
463#define DBCR_DAC1R DBCR0_DAC1R
464#define DBCR_DAC1W DBCR0_DAC1W
465#define DBCR_DAC2R DBCR0_DAC2R
466#define DBCR_DAC2W DBCR0_DAC2W
467
468/* Bit definitions related to the DBCR1. */
469#define DBCR1_IAC1US 0xC0000000 /* Instr Addr Cmp 1 Sup/User */
470#define DBCR1_IAC1ER 0x30000000 /* Instr Addr Cmp 1 Eff/Real */
471#define DBCR1_IAC1ER_01 0x10000000 /* reserved */
472#define DBCR1_IAC1ER_10 0x20000000 /* Instr Addr Cmp 1 Eff/Real MSR[IS]=0 */
473#define DBCR1_IAC1ER_11 0x30000000 /* Instr Addr Cmp 1 Eff/Real MSR[IS]=1 */
474#define DBCR1_IAC2US 0x0C000000 /* Instr Addr Cmp 2 Sup/User */
475#define DBCR1_IAC2ER 0x03000000 /* Instr Addr Cmp 2 Eff/Real */
476#define DBCR1_IAC2ER_01 0x01000000 /* reserved */
477#define DBCR1_IAC2ER_10 0x02000000 /* Instr Addr Cmp 2 Eff/Real MSR[IS]=0 */
478#define DBCR1_IAC2ER_11 0x03000000 /* Instr Addr Cmp 2 Eff/Real MSR[IS]=1 */
479#define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */
480#define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */
481#define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */
482#define DBCR1_IAC3US 0x0000C000 /* Instr Addr Cmp 3 Sup/User */
483#define DBCR1_IAC3ER 0x00003000 /* Instr Addr Cmp 3 Eff/Real */
484#define DBCR1_IAC3ER_01 0x00001000 /* reserved */
485#define DBCR1_IAC3ER_10 0x00002000 /* Instr Addr Cmp 3 Eff/Real MSR[IS]=0 */
486#define DBCR1_IAC3ER_11 0x00003000 /* Instr Addr Cmp 3 Eff/Real MSR[IS]=1 */
487#define DBCR1_IAC4US 0x00000C00 /* Instr Addr Cmp 4 Sup/User */
488#define DBCR1_IAC4ER 0x00000300 /* Instr Addr Cmp 4 Eff/Real */
489#define DBCR1_IAC4ER_01 0x00000100 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
490#define DBCR1_IAC4ER_10 0x00000200 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
491#define DBCR1_IAC4ER_11 0x00000300 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=1 */
492#define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */
493#define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */
494#define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */
495
496#define dbcr_iac_range(task) ((task)->thread.debug.dbcr1)
497#define DBCR_IAC12I DBCR1_IAC12M /* Range Inclusive */
498#define DBCR_IAC12X DBCR1_IAC12MX /* Range Exclusive */
499#define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */
500#define DBCR_IAC34I DBCR1_IAC34M /* Range Inclusive */
501#define DBCR_IAC34X DBCR1_IAC34MX /* Range Exclusive */
502#define DBCR_IAC34MODE DBCR1_IAC34MX /* IAC 3-4 Mode Bits */
503
504/* Bit definitions related to the DBCR2. */
505#define DBCR2_DAC1US 0xC0000000 /* Data Addr Cmp 1 Sup/User */
506#define DBCR2_DAC1ER 0x30000000 /* Data Addr Cmp 1 Eff/Real */
507#define DBCR2_DAC2US 0x0C000000 /* Data Addr Cmp 2 Sup/User */
508#define DBCR2_DAC2ER 0x03000000 /* Data Addr Cmp 2 Eff/Real */
509#define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */
510#define DBCR2_DAC12MM 0x00400000 /* DAC 1-2 Mask mode*/
511#define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */
512#define DBCR2_DAC12MODE 0x00C00000 /* DAC 1-2 Mode Bits */
513#define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */
514#define DBCR2_DVC1M 0x000C0000 /* Data Value Comp 1 Mode */
515#define DBCR2_DVC1M_SHIFT 18 /* # of bits to shift DBCR2_DVC1M */
516#define DBCR2_DVC2M 0x00030000 /* Data Value Comp 2 Mode */
517#define DBCR2_DVC2M_SHIFT 16 /* # of bits to shift DBCR2_DVC2M */
518#define DBCR2_DVC1BE 0x00000F00 /* Data Value Comp 1 Byte */
519#define DBCR2_DVC1BE_SHIFT 8 /* # of bits to shift DBCR2_DVC1BE */
520#define DBCR2_DVC2BE 0x0000000F /* Data Value Comp 2 Byte */
521#define DBCR2_DVC2BE_SHIFT 0 /* # of bits to shift DBCR2_DVC2BE */
522
523/*
524 * Are there any active Debug Events represented in the
525 * Debug Control Registers?
526 */
527#define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
528 DBCR0_IAC3 | DBCR0_IAC4 | DBCR0_DAC1R | \
529 DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)
530#define DBCR1_ACTIVE_EVENTS 0
531
532#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
533 ((dbcr1) & DBCR1_ACTIVE_EVENTS))
534#endif /* #elif defined(CONFIG_BOOKE) */
535
536/* Bit definitions related to the TCR. */
537#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
538#define TCR_WP_MASK TCR_WP(3)
539#define WP_2_17 0 /* 2^17 clocks */
540#define WP_2_21 1 /* 2^21 clocks */
541#define WP_2_25 2 /* 2^25 clocks */
542#define WP_2_29 3 /* 2^29 clocks */
543#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
544#define TCR_WRC_MASK TCR_WRC(3)
545#define WRC_NONE 0 /* No reset will occur */
546#define WRC_CORE 1 /* Core reset will occur */
547#define WRC_CHIP 2 /* Chip reset will occur */
548#define WRC_SYSTEM 3 /* System reset will occur */
549#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
550#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
551#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */
552#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
553#define TCR_FP_MASK TCR_FP(3)
554#define FP_2_9 0 /* 2^9 clocks */
555#define FP_2_13 1 /* 2^13 clocks */
556#define FP_2_17 2 /* 2^17 clocks */
557#define FP_2_21 3 /* 2^21 clocks */
558#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
559#define TCR_ARE 0x00400000 /* Auto Reload Enable */
560
561#ifdef CONFIG_E500
562#define TCR_GET_WP(tcr) ((((tcr) & 0xC0000000) >> 30) | \
563 (((tcr) & 0x1E0000) >> 15))
564#else
565#define TCR_GET_WP(tcr) (((tcr) & 0xC0000000) >> 30)
566#endif
567
568/* Bit definitions for the TSR. */
569#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
570#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
571#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
572#define WRS_NONE 0 /* No WDT reset occurred */
573#define WRS_CORE 1 /* WDT forced core reset */
574#define WRS_CHIP 2 /* WDT forced chip reset */
575#define WRS_SYSTEM 3 /* WDT forced system reset */
576#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
577#define TSR_DIS TSR_PIS /* DEC Interrupt Status */
578#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
579
580/* Bit definitions for the DCCR. */
581#define DCCR_NOCACHE 0 /* Noncacheable */
582#define DCCR_CACHE 1 /* Cacheable */
583
584/* Bit definitions for DCWR. */
585#define DCWR_COPY 0 /* Copy-back */
586#define DCWR_WRITE 1 /* Write-through */
587
588/* Bit definitions for ICCR. */
589#define ICCR_NOCACHE 0 /* Noncacheable */
590#define ICCR_CACHE 1 /* Cacheable */
591
592/* Bit definitions for L1CSR0. */
593#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
594#define L1CSR0_CUL 0x00000400 /* Data Cache Unable to Lock */
595#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */
596#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
597#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */
598#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
599
600/* Bit definitions for L1CSR1. */
601#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
602#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
603#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
604#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
605
606/* Bit definitions for L1CSR2. */
607#define L1CSR2_DCWS 0x40000000 /* Data Cache write shadow */
608
609/* Bit definitions for BUCSR. */
610#define BUCSR_STAC_EN 0x01000000 /* Segment Target Address Cache */
611#define BUCSR_LS_EN 0x00400000 /* Link Stack */
612#define BUCSR_BBFI 0x00000200 /* Branch Buffer flash invalidate */
613#define BUCSR_BPEN 0x00000001 /* Branch prediction enable */
614#define BUCSR_INIT (BUCSR_STAC_EN | BUCSR_LS_EN | BUCSR_BBFI | BUCSR_BPEN)
615
616/* Bit definitions for L2CSR0. */
617#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
618#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
619#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
620#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
621#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
622#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
623#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
624#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
625#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
626#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
627#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
628#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
629
630/* Bit definitions for SGR. */
631#define SGR_NORMAL 0 /* Speculative fetching allowed. */
632#define SGR_GUARDED 1 /* Speculative fetching disallowed. */
633
634/* Bit definitions for EPCR */
635#define SPRN_EPCR_EXTGS 0x80000000 /* External Input interrupt
636 * directed to Guest state */
637#define SPRN_EPCR_DTLBGS 0x40000000 /* Data TLB Error interrupt
638 * directed to guest state */
639#define SPRN_EPCR_ITLBGS 0x20000000 /* Instr. TLB error interrupt
640 * directed to guest state */
641#define SPRN_EPCR_DSIGS 0x10000000 /* Data Storage interrupt
642 * directed to guest state */
643#define SPRN_EPCR_ISIGS 0x08000000 /* Instr. Storage interrupt
644 * directed to guest state */
645#define SPRN_EPCR_DUVD 0x04000000 /* Disable Hypervisor Debug */
646#define SPRN_EPCR_ICM 0x02000000 /* Interrupt computation mode
647 * (copied to MSR:CM on intr) */
648#define SPRN_EPCR_GICM 0x01000000 /* Guest Interrupt Comp. mode */
649#define SPRN_EPCR_DGTMI 0x00800000 /* Disable TLB Guest Management
650 * instructions */
651#define SPRN_EPCR_DMIUH 0x00400000 /* Disable MAS Interrupt updates
652 * for hypervisor */
653
654/* Bit definitions for EPLC/EPSC */
655#define EPC_EPR 0x80000000 /* 1 = user, 0 = kernel */
656#define EPC_EPR_SHIFT 31
657#define EPC_EAS 0x40000000 /* Address Space */
658#define EPC_EAS_SHIFT 30
659#define EPC_EGS 0x20000000 /* 1 = guest, 0 = hypervisor */
660#define EPC_EGS_SHIFT 29
661#define EPC_ELPID 0x00ff0000
662#define EPC_ELPID_SHIFT 16
663#define EPC_EPID 0x00003fff
664#define EPC_EPID_SHIFT 0
665
666/* Some 476 specific registers */
667#define SPRN_SSPCR 830
668#define SPRN_USPCR 831
669#define SPRN_ISPCR 829
670#define SPRN_MMUBE0 820
671#define MMUBE0_IBE0_SHIFT 24
672#define MMUBE0_IBE1_SHIFT 16
673#define MMUBE0_IBE2_SHIFT 8
674#define MMUBE0_VBE0 0x00000004
675#define MMUBE0_VBE1 0x00000002
676#define MMUBE0_VBE2 0x00000001
677#define SPRN_MMUBE1 821
678#define MMUBE1_IBE3_SHIFT 24
679#define MMUBE1_IBE4_SHIFT 16
680#define MMUBE1_IBE5_SHIFT 8
681#define MMUBE1_VBE3 0x00000004
682#define MMUBE1_VBE4 0x00000002
683#define MMUBE1_VBE5 0x00000001
684
685#define TMRN_TMCFG0 16 /* Thread Management Configuration Register 0 */
686#define TMRN_TMCFG0_NPRIBITS 0x003f0000 /* Bits of thread priority */
687#define TMRN_TMCFG0_NPRIBITS_SHIFT 16
688#define TMRN_TMCFG0_NATHRD 0x00003f00 /* Number of active threads */
689#define TMRN_TMCFG0_NATHRD_SHIFT 8
690#define TMRN_TMCFG0_NTHRD 0x0000003f /* Number of threads */
691#define TMRN_IMSR0 0x120 /* Initial MSR Register 0 (e6500) */
692#define TMRN_IMSR1 0x121 /* Initial MSR Register 1 (e6500) */
693#define TMRN_INIA0 0x140 /* Next Instruction Address Register 0 */
694#define TMRN_INIA1 0x141 /* Next Instruction Address Register 1 */
695#define SPRN_TENSR 0x1b5 /* Thread Enable Status Register */
696#define SPRN_TENS 0x1b6 /* Thread Enable Set Register */
697#define SPRN_TENC 0x1b7 /* Thread Enable Clear Register */
698
699#define TEN_THREAD(x) (1 << (x))
700
701#ifndef __ASSEMBLY__
702#define mftmr(rn) ({unsigned long rval; \
703 asm volatile(MFTMR(rn, %0) : "=r" (rval)); rval;})
704#define mttmr(rn, v) asm volatile(MTTMR(rn, %0) : \
705 : "r" ((unsigned long)(v)) \
706 : "memory")
707#endif /* !__ASSEMBLY__ */
708
709#endif /* __ASM_POWERPC_REG_BOOKE_H__ */
710#endif /* __KERNEL__ */