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Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos SoC SROM Controller driver
8
9maintainers:
10 - Krzysztof Kozlowski <krzk@kernel.org>
11
12description: |+
13 The SROM controller can be used to attach external peripherals. In this case
14 extra properties, describing the bus behind it, should be specified.
15
16properties:
17 compatible:
18 items:
19 - const: samsung,exynos4210-srom
20
21 reg:
22 maxItems: 1
23
24 "#address-cells":
25 const: 2
26
27 "#size-cells":
28 const: 1
29
30 ranges:
31 description: |
32 Reflects the memory layout with four integer values per bank. Format:
33 <bank-number> 0 <parent address of bank> <size>
34 Up to four banks are supported.
35
36patternProperties:
37 "^.*@[0-3],[a-f0-9]+$":
38 type: object
39 description:
40 The actual device nodes should be added as subnodes to the SROMc node.
41 These subnodes, in addition to regular device specification, should
42 contain the following properties, describing configuration
43 of the relevant SROM bank.
44
45 properties:
46 reg:
47 description:
48 Bank number, base address (relative to start of the bank) and size
49 of the memory mapped for the device. Note that base address will be
50 typically 0 as this is the start of the bank.
51 maxItems: 1
52
53 reg-io-width:
54 enum: [1, 2]
55 description:
56 Data width in bytes (1 or 2). If omitted, default of 1 is used.
57
58 samsung,srom-page-mode:
59 description:
60 If page mode is set, 4 data page mode will be configured,
61 else normal (1 data) page mode will be set.
62 type: boolean
63
64 samsung,srom-timing:
65 $ref: /schemas/types.yaml#/definitions/uint32-array
66 items:
67 minItems: 6
68 maxItems: 6
69 description: |
70 Array of 6 integers, specifying bank timings in the following order:
71 Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
72 Each value is specified in cycles and has the following meaning
73 and valid range:
74 Tacp: Page mode access cycle at Page mode (0 - 15)
75 Tcah: Address holding time after CSn (0 - 15)
76 Tcoh: Chip selection hold on OEn (0 - 15)
77 Tacc: Access cycle (0 - 31, the actual time is N + 1)
78 Tcos: Chip selection set-up before OEn (0 - 15)
79 Tacs: Address set-up before CSn (0 - 15)
80
81 required:
82 - reg
83 - samsung,srom-timing
84
85required:
86 - compatible
87 - reg
88
89additionalProperties: false
90
91examples:
92 - |
93 // Example: basic definition, no banks are configured
94 memory-controller@12560000 {
95 compatible = "samsung,exynos4210-srom";
96 reg = <0x12560000 0x14>;
97 };
98
99 - |
100 // Example: SROMc with SMSC911x ethernet chip on bank 3
101 memory-controller@12570000 {
102 #address-cells = <2>;
103 #size-cells = <1>;
104 ranges = <0 0 0x04000000 0x20000 // Bank0
105 1 0 0x05000000 0x20000 // Bank1
106 2 0 0x06000000 0x20000 // Bank2
107 3 0 0x07000000 0x20000>; // Bank3
108
109 compatible = "samsung,exynos4210-srom";
110 reg = <0x12570000 0x14>;
111
112 ethernet@3,0 {
113 compatible = "smsc,lan9115";
114 reg = <3 0 0x10000>; // Bank 3, offset = 0
115 phy-mode = "mii";
116 interrupt-parent = <&gpx0>;
117 interrupts = <5 8>;
118 reg-io-width = <2>;
119 smsc,irq-push-pull;
120 smsc,force-internal-phy;
121
122 samsung,srom-page-mode;
123 samsung,srom-timing = <9 12 1 9 1 1>;
124 };
125 };