tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/allwinner,sun9i-a80-deu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner A80 Detail Enhancement Unit Device Tree Bindings
8
9maintainers:
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
12
13description: |
14 The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC,
15 can sharpen the display content in both luma and chroma channels.
16
17properties:
18 compatible:
19 const: allwinner,sun9i-a80-deu
20
21 reg:
22 maxItems: 1
23
24 interrupts:
25 maxItems: 1
26
27 clocks:
28 items:
29 - description: The DEU interface clock
30 - description: The DEU module clock
31 - description: The DEU DRAM clock
32
33 clock-names:
34 items:
35 - const: ahb
36 - const: mod
37 - const: ram
38
39 resets:
40 maxItems: 1
41
42 ports:
43 type: object
44 description: |
45 A ports node with endpoint definitions as defined in
46 Documentation/devicetree/bindings/media/video-interfaces.txt.
47
48 properties:
49 "#address-cells":
50 const: 1
51
52 "#size-cells":
53 const: 0
54
55 port@0:
56 type: object
57 description: |
58 Input endpoints of the controller.
59
60 port@1:
61 type: object
62 description: |
63 Output endpoints of the controller.
64
65 required:
66 - "#address-cells"
67 - "#size-cells"
68 - port@0
69 - port@1
70
71 additionalProperties: false
72
73required:
74 - compatible
75 - reg
76 - interrupts
77 - clocks
78 - clock-names
79 - resets
80 - ports
81
82additionalProperties: false
83
84examples:
85 - |
86 #include <dt-bindings/interrupt-controller/arm-gic.h>
87
88 #include <dt-bindings/clock/sun9i-a80-de.h>
89 #include <dt-bindings/reset/sun9i-a80-de.h>
90
91 deu0: deu@3300000 {
92 compatible = "allwinner,sun9i-a80-deu";
93 reg = <0x03300000 0x40000>;
94 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&de_clocks CLK_BUS_DEU0>,
96 <&de_clocks CLK_IEP_DEU0>,
97 <&de_clocks CLK_DRAM_DEU0>;
98 clock-names = "ahb",
99 "mod",
100 "ram";
101 resets = <&de_clocks RST_DEU0>;
102
103 ports {
104 #address-cells = <1>;
105 #size-cells = <0>;
106
107 deu0_in: port@0 {
108 reg = <0>;
109
110 deu0_in_fe0: endpoint {
111 remote-endpoint = <&fe0_out_deu0>;
112 };
113 };
114
115 deu0_out: port@1 {
116 #address-cells = <1>;
117 #size-cells = <0>;
118 reg = <1>;
119
120 deu0_out_be0: endpoint@0 {
121 reg = <0>;
122 remote-endpoint = <&be0_in_deu0>;
123 };
124
125 deu0_out_be1: endpoint@1 {
126 reg = <1>;
127 remote-endpoint = <&be1_in_deu0>;
128 };
129 };
130 };
131 };
132
133...