tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef __AMDGPU_UMC_H__
22#define __AMDGPU_UMC_H__
23
24struct amdgpu_umc_funcs {
25 void (*err_cnt_init)(struct amdgpu_device *adev);
26 int (*ras_late_init)(struct amdgpu_device *adev);
27 void (*query_ras_error_count)(struct amdgpu_device *adev,
28 void *ras_error_status);
29 void (*query_ras_error_address)(struct amdgpu_device *adev,
30 void *ras_error_status);
31 void (*init_registers)(struct amdgpu_device *adev);
32};
33
34struct amdgpu_umc {
35 /* max error count in one ras query call */
36 uint32_t max_ras_err_cnt_per_query;
37 /* number of umc channel instance with memory map register access */
38 uint32_t channel_inst_num;
39 /* number of umc instance with memory map register access */
40 uint32_t umc_inst_num;
41 /* UMC regiser per channel offset */
42 uint32_t channel_offs;
43 /* channel index table of interleaved memory */
44 const uint32_t *channel_idx_tbl;
45 struct ras_common_if *ras_if;
46
47 const struct amdgpu_umc_funcs *funcs;
48};
49
50int amdgpu_umc_ras_late_init(struct amdgpu_device *adev);
51void amdgpu_umc_ras_fini(struct amdgpu_device *adev);
52int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
53 void *ras_error_status,
54 struct amdgpu_iv_entry *entry);
55int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
56 struct amdgpu_irq_src *source,
57 struct amdgpu_iv_entry *entry);
58#endif