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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * MPC8xx Communication Processor Module.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 *
6 * This file contains structures and information for the communication
7 * processor channels. Some CPM control and status is available
8 * through the MPC8xx internal memory map. See immap.h for details.
9 * This file only contains what I need for the moment, not the total
10 * CPM capabilities. I (or someone else) will add definitions as they
11 * are needed. -- Dan
12 *
13 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
14 * bytes of the DP RAM and relocates the I2C parameter area to the
15 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
16 * or other use.
17 */
18#ifndef __CPM1__
19#define __CPM1__
20
21#include <linux/init.h>
22#include <asm/8xx_immap.h>
23#include <asm/ptrace.h>
24#include <asm/cpm.h>
25
26/* CPM Command register.
27*/
28#define CPM_CR_RST ((ushort)0x8000)
29#define CPM_CR_OPCODE ((ushort)0x0f00)
30#define CPM_CR_CHAN ((ushort)0x00f0)
31#define CPM_CR_FLG ((ushort)0x0001)
32
33/* Channel numbers.
34*/
35#define CPM_CR_CH_SCC1 ((ushort)0x0000)
36#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
37#define CPM_CR_CH_SCC2 ((ushort)0x0004)
38#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
39#define CPM_CR_CH_TIMER CPM_CR_CH_SPI
40#define CPM_CR_CH_SCC3 ((ushort)0x0008)
41#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
42#define CPM_CR_CH_SCC4 ((ushort)0x000c)
43#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
44
45#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
46
47/* Export the base address of the communication processor registers
48 * and dual port ram.
49 */
50extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */
51
52#define cpm_dpalloc cpm_muram_alloc
53#define cpm_dpfree cpm_muram_free
54#define cpm_dpram_addr cpm_muram_addr
55#define cpm_dpram_phys cpm_muram_dma
56
57extern void cpm_setbrg(uint brg, uint rate);
58
59extern void __init cpm_load_patch(cpm8xx_t *cp);
60
61extern void cpm_reset(void);
62
63/* Parameter RAM offsets.
64*/
65#define PROFF_SCC1 ((uint)0x0000)
66#define PROFF_IIC ((uint)0x0080)
67#define PROFF_SCC2 ((uint)0x0100)
68#define PROFF_SPI ((uint)0x0180)
69#define PROFF_SCC3 ((uint)0x0200)
70#define PROFF_SMC1 ((uint)0x0280)
71#define PROFF_SCC4 ((uint)0x0300)
72#define PROFF_SMC2 ((uint)0x0380)
73
74/* Define enough so I can at least use the serial port as a UART.
75 * The MBX uses SMC1 as the host serial port.
76 */
77typedef struct smc_uart {
78 ushort smc_rbase; /* Rx Buffer descriptor base address */
79 ushort smc_tbase; /* Tx Buffer descriptor base address */
80 u_char smc_rfcr; /* Rx function code */
81 u_char smc_tfcr; /* Tx function code */
82 ushort smc_mrblr; /* Max receive buffer length */
83 uint smc_rstate; /* Internal */
84 uint smc_idp; /* Internal */
85 ushort smc_rbptr; /* Internal */
86 ushort smc_ibc; /* Internal */
87 uint smc_rxtmp; /* Internal */
88 uint smc_tstate; /* Internal */
89 uint smc_tdp; /* Internal */
90 ushort smc_tbptr; /* Internal */
91 ushort smc_tbc; /* Internal */
92 uint smc_txtmp; /* Internal */
93 ushort smc_maxidl; /* Maximum idle characters */
94 ushort smc_tmpidl; /* Temporary idle counter */
95 ushort smc_brklen; /* Last received break length */
96 ushort smc_brkec; /* rcv'd break condition counter */
97 ushort smc_brkcr; /* xmt break count register */
98 ushort smc_rmask; /* Temporary bit mask */
99 char res1[8]; /* Reserved */
100 ushort smc_rpbase; /* Relocation pointer */
101} smc_uart_t;
102
103/* Function code bits.
104*/
105#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
106
107/* SMC uart mode register.
108*/
109#define SMCMR_REN ((ushort)0x0001)
110#define SMCMR_TEN ((ushort)0x0002)
111#define SMCMR_DM ((ushort)0x000c)
112#define SMCMR_SM_GCI ((ushort)0x0000)
113#define SMCMR_SM_UART ((ushort)0x0020)
114#define SMCMR_SM_TRANS ((ushort)0x0030)
115#define SMCMR_SM_MASK ((ushort)0x0030)
116#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
117#define SMCMR_REVD SMCMR_PM_EVEN
118#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
119#define SMCMR_BS SMCMR_PEN
120#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
121#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
122#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
123
124/* SMC2 as Centronics parallel printer. It is half duplex, in that
125 * it can only receive or transmit. The parameter ram values for
126 * each direction are either unique or properly overlap, so we can
127 * include them in one structure.
128 */
129typedef struct smc_centronics {
130 ushort scent_rbase;
131 ushort scent_tbase;
132 u_char scent_cfcr;
133 u_char scent_smask;
134 ushort scent_mrblr;
135 uint scent_rstate;
136 uint scent_r_ptr;
137 ushort scent_rbptr;
138 ushort scent_r_cnt;
139 uint scent_rtemp;
140 uint scent_tstate;
141 uint scent_t_ptr;
142 ushort scent_tbptr;
143 ushort scent_t_cnt;
144 uint scent_ttemp;
145 ushort scent_max_sl;
146 ushort scent_sl_cnt;
147 ushort scent_character1;
148 ushort scent_character2;
149 ushort scent_character3;
150 ushort scent_character4;
151 ushort scent_character5;
152 ushort scent_character6;
153 ushort scent_character7;
154 ushort scent_character8;
155 ushort scent_rccm;
156 ushort scent_rccr;
157} smc_cent_t;
158
159/* Centronics Status Mask Register.
160*/
161#define SMC_CENT_F ((u_char)0x08)
162#define SMC_CENT_PE ((u_char)0x04)
163#define SMC_CENT_S ((u_char)0x02)
164
165/* SMC Event and Mask register.
166*/
167#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
168#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
169#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
170#define SMCM_BSY ((unsigned char)0x04)
171#define SMCM_TX ((unsigned char)0x02)
172#define SMCM_RX ((unsigned char)0x01)
173
174/* Baud rate generators.
175*/
176#define CPM_BRG_RST ((uint)0x00020000)
177#define CPM_BRG_EN ((uint)0x00010000)
178#define CPM_BRG_EXTC_INT ((uint)0x00000000)
179#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
180#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
181#define CPM_BRG_ATB ((uint)0x00002000)
182#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
183#define CPM_BRG_DIV16 ((uint)0x00000001)
184
185/* SI Clock Route Register
186*/
187#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
188#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
189#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
190#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
191#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
192#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
193#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
194#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
195
196/* SCCs.
197*/
198#define SCC_GSMRH_IRP ((uint)0x00040000)
199#define SCC_GSMRH_GDE ((uint)0x00010000)
200#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
201#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
202#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
203#define SCC_GSMRH_REVD ((uint)0x00002000)
204#define SCC_GSMRH_TRX ((uint)0x00001000)
205#define SCC_GSMRH_TTX ((uint)0x00000800)
206#define SCC_GSMRH_CDP ((uint)0x00000400)
207#define SCC_GSMRH_CTSP ((uint)0x00000200)
208#define SCC_GSMRH_CDS ((uint)0x00000100)
209#define SCC_GSMRH_CTSS ((uint)0x00000080)
210#define SCC_GSMRH_TFL ((uint)0x00000040)
211#define SCC_GSMRH_RFW ((uint)0x00000020)
212#define SCC_GSMRH_TXSY ((uint)0x00000010)
213#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
214#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
215#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
216#define SCC_GSMRH_RTSM ((uint)0x00000002)
217#define SCC_GSMRH_RSYN ((uint)0x00000001)
218
219#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
220#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
221#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
222#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
223#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
224#define SCC_GSMRL_TCI ((uint)0x10000000)
225#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
226#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
227#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
228#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
229#define SCC_GSMRL_RINV ((uint)0x02000000)
230#define SCC_GSMRL_TINV ((uint)0x01000000)
231#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
232#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
233#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
234#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
235#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
236#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
237#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
238#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
239#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
240#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
241#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
242#define SCC_GSMRL_TEND ((uint)0x00040000)
243#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
244#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
245#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
246#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
247#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
248#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
249#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
250#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
251#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
252#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
253#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
254#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
255#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
256#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
257#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
258#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
259#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
260#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
261#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
262#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
263#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
264#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
265#define SCC_GSMRL_ENR ((uint)0x00000020)
266#define SCC_GSMRL_ENT ((uint)0x00000010)
267#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
268#define SCC_GSMRL_MODE_QMC ((uint)0x0000000a)
269#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
270#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
271#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
272#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
273#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
274#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
275#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
276#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
277#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
278
279#define SCC_TODR_TOD ((ushort)0x8000)
280
281/* SCC Event and Mask register.
282*/
283#define SCCM_TXE ((unsigned char)0x10)
284#define SCCM_BSY ((unsigned char)0x04)
285#define SCCM_TX ((unsigned char)0x02)
286#define SCCM_RX ((unsigned char)0x01)
287
288typedef struct scc_param {
289 ushort scc_rbase; /* Rx Buffer descriptor base address */
290 ushort scc_tbase; /* Tx Buffer descriptor base address */
291 u_char scc_rfcr; /* Rx function code */
292 u_char scc_tfcr; /* Tx function code */
293 ushort scc_mrblr; /* Max receive buffer length */
294 uint scc_rstate; /* Internal */
295 uint scc_idp; /* Internal */
296 ushort scc_rbptr; /* Internal */
297 ushort scc_ibc; /* Internal */
298 uint scc_rxtmp; /* Internal */
299 uint scc_tstate; /* Internal */
300 uint scc_tdp; /* Internal */
301 ushort scc_tbptr; /* Internal */
302 ushort scc_tbc; /* Internal */
303 uint scc_txtmp; /* Internal */
304 uint scc_rcrc; /* Internal */
305 uint scc_tcrc; /* Internal */
306} sccp_t;
307
308/* Function code bits.
309*/
310#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
311
312/* CPM Ethernet through SCCx.
313 */
314typedef struct scc_enet {
315 sccp_t sen_genscc;
316 uint sen_cpres; /* Preset CRC */
317 uint sen_cmask; /* Constant mask for CRC */
318 uint sen_crcec; /* CRC Error counter */
319 uint sen_alec; /* alignment error counter */
320 uint sen_disfc; /* discard frame counter */
321 ushort sen_pads; /* Tx short frame pad character */
322 ushort sen_retlim; /* Retry limit threshold */
323 ushort sen_retcnt; /* Retry limit counter */
324 ushort sen_maxflr; /* maximum frame length register */
325 ushort sen_minflr; /* minimum frame length register */
326 ushort sen_maxd1; /* maximum DMA1 length */
327 ushort sen_maxd2; /* maximum DMA2 length */
328 ushort sen_maxd; /* Rx max DMA */
329 ushort sen_dmacnt; /* Rx DMA counter */
330 ushort sen_maxb; /* Max BD byte count */
331 ushort sen_gaddr1; /* Group address filter */
332 ushort sen_gaddr2;
333 ushort sen_gaddr3;
334 ushort sen_gaddr4;
335 uint sen_tbuf0data0; /* Save area 0 - current frame */
336 uint sen_tbuf0data1; /* Save area 1 - current frame */
337 uint sen_tbuf0rba; /* Internal */
338 uint sen_tbuf0crc; /* Internal */
339 ushort sen_tbuf0bcnt; /* Internal */
340 ushort sen_paddrh; /* physical address (MSB) */
341 ushort sen_paddrm;
342 ushort sen_paddrl; /* physical address (LSB) */
343 ushort sen_pper; /* persistence */
344 ushort sen_rfbdptr; /* Rx first BD pointer */
345 ushort sen_tfbdptr; /* Tx first BD pointer */
346 ushort sen_tlbdptr; /* Tx last BD pointer */
347 uint sen_tbuf1data0; /* Save area 0 - current frame */
348 uint sen_tbuf1data1; /* Save area 1 - current frame */
349 uint sen_tbuf1rba; /* Internal */
350 uint sen_tbuf1crc; /* Internal */
351 ushort sen_tbuf1bcnt; /* Internal */
352 ushort sen_txlen; /* Tx Frame length counter */
353 ushort sen_iaddr1; /* Individual address filter */
354 ushort sen_iaddr2;
355 ushort sen_iaddr3;
356 ushort sen_iaddr4;
357 ushort sen_boffcnt; /* Backoff counter */
358
359 /* NOTE: Some versions of the manual have the following items
360 * incorrectly documented. Below is the proper order.
361 */
362 ushort sen_taddrh; /* temp address (MSB) */
363 ushort sen_taddrm;
364 ushort sen_taddrl; /* temp address (LSB) */
365} scc_enet_t;
366
367/* SCC Event register as used by Ethernet.
368*/
369#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
370#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
371#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
372#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
373#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
374#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
375
376/* SCC Mode Register (PMSR) as used by Ethernet.
377*/
378#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
379#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
380#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
381#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
382#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
383#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
384#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
385#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
386#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
387#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
388#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
389#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
390#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
391
392/* SCC as UART
393*/
394typedef struct scc_uart {
395 sccp_t scc_genscc;
396 char res1[8]; /* Reserved */
397 ushort scc_maxidl; /* Maximum idle chars */
398 ushort scc_idlc; /* temp idle counter */
399 ushort scc_brkcr; /* Break count register */
400 ushort scc_parec; /* receive parity error counter */
401 ushort scc_frmec; /* receive framing error counter */
402 ushort scc_nosec; /* receive noise counter */
403 ushort scc_brkec; /* receive break condition counter */
404 ushort scc_brkln; /* last received break length */
405 ushort scc_uaddr1; /* UART address character 1 */
406 ushort scc_uaddr2; /* UART address character 2 */
407 ushort scc_rtemp; /* Temp storage */
408 ushort scc_toseq; /* Transmit out of sequence char */
409 ushort scc_char1; /* control character 1 */
410 ushort scc_char2; /* control character 2 */
411 ushort scc_char3; /* control character 3 */
412 ushort scc_char4; /* control character 4 */
413 ushort scc_char5; /* control character 5 */
414 ushort scc_char6; /* control character 6 */
415 ushort scc_char7; /* control character 7 */
416 ushort scc_char8; /* control character 8 */
417 ushort scc_rccm; /* receive control character mask */
418 ushort scc_rccr; /* receive control character register */
419 ushort scc_rlbc; /* receive last break character */
420} scc_uart_t;
421
422/* SCC Event and Mask registers when it is used as a UART.
423*/
424#define UART_SCCM_GLR ((ushort)0x1000)
425#define UART_SCCM_GLT ((ushort)0x0800)
426#define UART_SCCM_AB ((ushort)0x0200)
427#define UART_SCCM_IDL ((ushort)0x0100)
428#define UART_SCCM_GRA ((ushort)0x0080)
429#define UART_SCCM_BRKE ((ushort)0x0040)
430#define UART_SCCM_BRKS ((ushort)0x0020)
431#define UART_SCCM_CCR ((ushort)0x0008)
432#define UART_SCCM_BSY ((ushort)0x0004)
433#define UART_SCCM_TX ((ushort)0x0002)
434#define UART_SCCM_RX ((ushort)0x0001)
435
436/* The SCC PMSR when used as a UART.
437*/
438#define SCU_PSMR_FLC ((ushort)0x8000)
439#define SCU_PSMR_SL ((ushort)0x4000)
440#define SCU_PSMR_CL ((ushort)0x3000)
441#define SCU_PSMR_UM ((ushort)0x0c00)
442#define SCU_PSMR_FRZ ((ushort)0x0200)
443#define SCU_PSMR_RZS ((ushort)0x0100)
444#define SCU_PSMR_SYN ((ushort)0x0080)
445#define SCU_PSMR_DRT ((ushort)0x0040)
446#define SCU_PSMR_PEN ((ushort)0x0010)
447#define SCU_PSMR_RPM ((ushort)0x000c)
448#define SCU_PSMR_REVP ((ushort)0x0008)
449#define SCU_PSMR_TPM ((ushort)0x0003)
450#define SCU_PSMR_TEVP ((ushort)0x0002)
451
452/* CPM Transparent mode SCC.
453 */
454typedef struct scc_trans {
455 sccp_t st_genscc;
456 uint st_cpres; /* Preset CRC */
457 uint st_cmask; /* Constant mask for CRC */
458} scc_trans_t;
459
460/* IIC parameter RAM.
461*/
462typedef struct iic {
463 ushort iic_rbase; /* Rx Buffer descriptor base address */
464 ushort iic_tbase; /* Tx Buffer descriptor base address */
465 u_char iic_rfcr; /* Rx function code */
466 u_char iic_tfcr; /* Tx function code */
467 ushort iic_mrblr; /* Max receive buffer length */
468 uint iic_rstate; /* Internal */
469 uint iic_rdp; /* Internal */
470 ushort iic_rbptr; /* Internal */
471 ushort iic_rbc; /* Internal */
472 uint iic_rxtmp; /* Internal */
473 uint iic_tstate; /* Internal */
474 uint iic_tdp; /* Internal */
475 ushort iic_tbptr; /* Internal */
476 ushort iic_tbc; /* Internal */
477 uint iic_txtmp; /* Internal */
478 char res1[4]; /* Reserved */
479 ushort iic_rpbase; /* Relocation pointer */
480 char res2[2]; /* Reserved */
481} iic_t;
482
483/*
484 * RISC Controller Configuration Register definitons
485 */
486#define RCCR_TIME 0x8000 /* RISC Timer Enable */
487#define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */
488#define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */
489
490/* RISC Timer Parameter RAM offset */
491#define PROFF_RTMR ((uint)0x01B0)
492
493typedef struct risc_timer_pram {
494 unsigned short tm_base; /* RISC Timer Table Base Address */
495 unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */
496 unsigned short r_tmr; /* RISC Timer Mode Register */
497 unsigned short r_tmv; /* RISC Timer Valid Register */
498 unsigned long tm_cmd; /* RISC Timer Command Register */
499 unsigned long tm_cnt; /* RISC Timer Internal Count */
500} rt_pram_t;
501
502/* Bits in RISC Timer Command Register */
503#define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */
504#define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */
505#define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */
506#define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */
507#define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */
508
509/* CPM interrupts. There are nearly 32 interrupts generated by CPM
510 * channels or devices. All of these are presented to the PPC core
511 * as a single interrupt. The CPM interrupt handler dispatches its
512 * own handlers, in a similar fashion to the PPC core handler. We
513 * use the table as defined in the manuals (i.e. no special high
514 * priority and SCC1 == SCCa, etc...).
515 */
516#define CPMVEC_NR 32
517#define CPMVEC_PIO_PC15 ((ushort)0x1f)
518#define CPMVEC_SCC1 ((ushort)0x1e)
519#define CPMVEC_SCC2 ((ushort)0x1d)
520#define CPMVEC_SCC3 ((ushort)0x1c)
521#define CPMVEC_SCC4 ((ushort)0x1b)
522#define CPMVEC_PIO_PC14 ((ushort)0x1a)
523#define CPMVEC_TIMER1 ((ushort)0x19)
524#define CPMVEC_PIO_PC13 ((ushort)0x18)
525#define CPMVEC_PIO_PC12 ((ushort)0x17)
526#define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
527#define CPMVEC_IDMA1 ((ushort)0x15)
528#define CPMVEC_IDMA2 ((ushort)0x14)
529#define CPMVEC_TIMER2 ((ushort)0x12)
530#define CPMVEC_RISCTIMER ((ushort)0x11)
531#define CPMVEC_I2C ((ushort)0x10)
532#define CPMVEC_PIO_PC11 ((ushort)0x0f)
533#define CPMVEC_PIO_PC10 ((ushort)0x0e)
534#define CPMVEC_TIMER3 ((ushort)0x0c)
535#define CPMVEC_PIO_PC9 ((ushort)0x0b)
536#define CPMVEC_PIO_PC8 ((ushort)0x0a)
537#define CPMVEC_PIO_PC7 ((ushort)0x09)
538#define CPMVEC_TIMER4 ((ushort)0x07)
539#define CPMVEC_PIO_PC6 ((ushort)0x06)
540#define CPMVEC_SPI ((ushort)0x05)
541#define CPMVEC_SMC1 ((ushort)0x04)
542#define CPMVEC_SMC2 ((ushort)0x03)
543#define CPMVEC_PIO_PC5 ((ushort)0x02)
544#define CPMVEC_PIO_PC4 ((ushort)0x01)
545#define CPMVEC_ERROR ((ushort)0x00)
546
547/* CPM interrupt configuration vector.
548*/
549#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
550#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
551#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
552#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
553#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
554#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
555#define CICR_IEN ((uint)0x00000080) /* Int. enable */
556#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
557
558#define CPM_PIN_INPUT 0
559#define CPM_PIN_OUTPUT 1
560#define CPM_PIN_PRIMARY 0
561#define CPM_PIN_SECONDARY 2
562#define CPM_PIN_GPIO 4
563#define CPM_PIN_OPENDRAIN 8
564#define CPM_PIN_FALLEDGE 16
565#define CPM_PIN_ANYEDGE 0
566
567enum cpm_port {
568 CPM_PORTA,
569 CPM_PORTB,
570 CPM_PORTC,
571 CPM_PORTD,
572 CPM_PORTE,
573};
574
575void cpm1_set_pin(enum cpm_port port, int pin, int flags);
576
577enum cpm_clk_dir {
578 CPM_CLK_RX,
579 CPM_CLK_TX,
580 CPM_CLK_RTX
581};
582
583enum cpm_clk_target {
584 CPM_CLK_SCC1,
585 CPM_CLK_SCC2,
586 CPM_CLK_SCC3,
587 CPM_CLK_SCC4,
588 CPM_CLK_SMC1,
589 CPM_CLK_SMC2,
590};
591
592enum cpm_clk {
593 CPM_BRG1, /* Baud Rate Generator 1 */
594 CPM_BRG2, /* Baud Rate Generator 2 */
595 CPM_BRG3, /* Baud Rate Generator 3 */
596 CPM_BRG4, /* Baud Rate Generator 4 */
597 CPM_CLK1, /* Clock 1 */
598 CPM_CLK2, /* Clock 2 */
599 CPM_CLK3, /* Clock 3 */
600 CPM_CLK4, /* Clock 4 */
601 CPM_CLK5, /* Clock 5 */
602 CPM_CLK6, /* Clock 6 */
603 CPM_CLK7, /* Clock 7 */
604 CPM_CLK8, /* Clock 8 */
605};
606
607int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode);
608int cpm1_gpiochip_add16(struct device *dev);
609int cpm1_gpiochip_add32(struct device *dev);
610
611#endif /* __CPM1__ */