tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/pinctrl/stm32-pinfunc.h>
7
8&pinctrl {
9 adc1_in6_pins_a: adc1-in6 {
10 pins {
11 pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
12 };
13 };
14
15 adc12_ain_pins_a: adc12-ain-0 {
16 pins {
17 pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
18 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
19 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
20 <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
21 };
22 };
23
24 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
25 pins {
26 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
27 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
28 };
29 };
30
31 cec_pins_a: cec-0 {
32 pins {
33 pinmux = <STM32_PINMUX('A', 15, AF4)>;
34 bias-disable;
35 drive-open-drain;
36 slew-rate = <0>;
37 };
38 };
39
40 cec_pins_sleep_a: cec-sleep-0 {
41 pins {
42 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
43 };
44 };
45
46 cec_pins_b: cec-1 {
47 pins {
48 pinmux = <STM32_PINMUX('B', 6, AF5)>;
49 bias-disable;
50 drive-open-drain;
51 slew-rate = <0>;
52 };
53 };
54
55 cec_pins_sleep_b: cec-sleep-1 {
56 pins {
57 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
58 };
59 };
60
61 dac_ch1_pins_a: dac-ch1 {
62 pins {
63 pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
64 };
65 };
66
67 dac_ch2_pins_a: dac-ch2 {
68 pins {
69 pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
70 };
71 };
72
73 dcmi_pins_a: dcmi-0 {
74 pins {
75 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
76 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
77 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
78 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
79 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
80 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
81 <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
82 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
83 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
84 <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
85 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
86 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
87 <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
88 <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
89 <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
90 bias-disable;
91 };
92 };
93
94 dcmi_sleep_pins_a: dcmi-sleep-0 {
95 pins {
96 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
97 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
98 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
99 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
100 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
101 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
102 <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
103 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
104 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
105 <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
106 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
107 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
108 <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
109 <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
110 <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
111 };
112 };
113
114 ethernet0_rgmii_pins_a: rgmii-0 {
115 pins1 {
116 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
117 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
118 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
119 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
120 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
121 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
122 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
123 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
124 bias-disable;
125 drive-push-pull;
126 slew-rate = <2>;
127 };
128 pins2 {
129 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
130 bias-disable;
131 drive-push-pull;
132 slew-rate = <0>;
133 };
134 pins3 {
135 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
136 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
137 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
138 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
139 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
140 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
141 bias-disable;
142 };
143 };
144
145 ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
146 pins1 {
147 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
148 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
149 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
150 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
151 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
152 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
153 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
154 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
155 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
156 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
157 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
158 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
159 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
160 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
161 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
162 };
163 };
164
165 ethernet0_rmii_pins_a: rmii-0 {
166 pins1 {
167 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
168 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
169 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
170 <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
171 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
172 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
173 bias-disable;
174 drive-push-pull;
175 slew-rate = <2>;
176 };
177 pins2 {
178 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
179 <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
180 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
181 bias-disable;
182 };
183 };
184
185 ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
186 pins1 {
187 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
188 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
189 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
190 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
191 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
192 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
193 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
194 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
195 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
196 };
197 };
198
199 fmc_pins_a: fmc-0 {
200 pins1 {
201 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
202 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
203 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
204 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
205 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
206 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
207 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
208 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
209 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
210 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
211 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
212 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
213 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
214 bias-disable;
215 drive-push-pull;
216 slew-rate = <1>;
217 };
218 pins2 {
219 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
220 bias-pull-up;
221 };
222 };
223
224 fmc_sleep_pins_a: fmc-sleep-0 {
225 pins {
226 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
227 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
228 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
229 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
230 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
231 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
232 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
233 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
234 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
235 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
236 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
237 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
238 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
239 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
240 };
241 };
242
243 i2c1_pins_a: i2c1-0 {
244 pins {
245 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
246 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
247 bias-disable;
248 drive-open-drain;
249 slew-rate = <0>;
250 };
251 };
252
253 i2c1_pins_sleep_a: i2c1-1 {
254 pins {
255 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
256 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
257 };
258 };
259
260 i2c1_pins_b: i2c1-2 {
261 pins {
262 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
263 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
264 bias-disable;
265 drive-open-drain;
266 slew-rate = <0>;
267 };
268 };
269
270 i2c1_pins_sleep_b: i2c1-3 {
271 pins {
272 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
273 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
274 };
275 };
276
277 i2c2_pins_a: i2c2-0 {
278 pins {
279 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
280 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
281 bias-disable;
282 drive-open-drain;
283 slew-rate = <0>;
284 };
285 };
286
287 i2c2_pins_sleep_a: i2c2-1 {
288 pins {
289 pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
290 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
291 };
292 };
293
294 i2c2_pins_b1: i2c2-2 {
295 pins {
296 pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
297 bias-disable;
298 drive-open-drain;
299 slew-rate = <0>;
300 };
301 };
302
303 i2c2_pins_sleep_b1: i2c2-3 {
304 pins {
305 pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
306 };
307 };
308
309 i2c5_pins_a: i2c5-0 {
310 pins {
311 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
312 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
313 bias-disable;
314 drive-open-drain;
315 slew-rate = <0>;
316 };
317 };
318
319 i2c5_pins_sleep_a: i2c5-1 {
320 pins {
321 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
322 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
323
324 };
325 };
326
327 i2s2_pins_a: i2s2-0 {
328 pins {
329 pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
330 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
331 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
332 slew-rate = <1>;
333 drive-push-pull;
334 bias-disable;
335 };
336 };
337
338 i2s2_pins_sleep_a: i2s2-1 {
339 pins {
340 pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
341 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
342 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
343 };
344 };
345
346 ltdc_pins_a: ltdc-a-0 {
347 pins {
348 pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
349 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
350 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
351 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
352 <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
353 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
354 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
355 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
356 <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
357 <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
358 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
359 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
360 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
361 <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
362 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
363 <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
364 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
365 <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
366 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
367 <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
368 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
369 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
370 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
371 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
372 <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
373 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
374 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
375 <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
376 bias-disable;
377 drive-push-pull;
378 slew-rate = <1>;
379 };
380 };
381
382 ltdc_pins_sleep_a: ltdc-a-1 {
383 pins {
384 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
385 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
386 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
387 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
388 <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
389 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
390 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
391 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
392 <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
393 <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
394 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
395 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
396 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
397 <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
398 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
399 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
400 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
401 <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
402 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
403 <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
404 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
405 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
406 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
407 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
408 <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
409 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
410 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
411 <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
412 };
413 };
414
415 ltdc_pins_b: ltdc-b-0 {
416 pins {
417 pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
418 <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
419 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
420 <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
421 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
422 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
423 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
424 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
425 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
426 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
427 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
428 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
429 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
430 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
431 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
432 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
433 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
434 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
435 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
436 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
437 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
438 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
439 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
440 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
441 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
442 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
443 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
444 <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
445 bias-disable;
446 drive-push-pull;
447 slew-rate = <1>;
448 };
449 };
450
451 ltdc_pins_sleep_b: ltdc-b-1 {
452 pins {
453 pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
454 <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
455 <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
456 <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
457 <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
458 <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
459 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
460 <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
461 <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
462 <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
463 <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
464 <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
465 <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
466 <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
467 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
468 <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
469 <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
470 <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
471 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
472 <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
473 <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
474 <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
475 <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
476 <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
477 <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
478 <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
479 <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
480 <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
481 };
482 };
483
484 m_can1_pins_a: m-can1-0 {
485 pins1 {
486 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
487 slew-rate = <1>;
488 drive-push-pull;
489 bias-disable;
490 };
491 pins2 {
492 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
493 bias-disable;
494 };
495 };
496
497 m_can1_sleep_pins_a: m_can1-sleep-0 {
498 pins {
499 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
500 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
501 };
502 };
503
504 pwm1_pins_a: pwm1-0 {
505 pins {
506 pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
507 <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
508 <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */
509 bias-pull-down;
510 drive-push-pull;
511 slew-rate = <0>;
512 };
513 };
514
515 pwm1_sleep_pins_a: pwm1-sleep-0 {
516 pins {
517 pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
518 <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */
519 <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */
520 };
521 };
522
523 pwm2_pins_a: pwm2-0 {
524 pins {
525 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
526 bias-pull-down;
527 drive-push-pull;
528 slew-rate = <0>;
529 };
530 };
531
532 pwm2_sleep_pins_a: pwm2-sleep-0 {
533 pins {
534 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
535 };
536 };
537
538 pwm3_pins_a: pwm3-0 {
539 pins {
540 pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */
541 bias-pull-down;
542 drive-push-pull;
543 slew-rate = <0>;
544 };
545 };
546
547 pwm3_sleep_pins_a: pwm3-sleep-0 {
548 pins {
549 pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */
550 };
551 };
552
553 pwm4_pins_a: pwm4-0 {
554 pins {
555 pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
556 <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
557 bias-pull-down;
558 drive-push-pull;
559 slew-rate = <0>;
560 };
561 };
562
563 pwm4_sleep_pins_a: pwm4-sleep-0 {
564 pins {
565 pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
566 <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
567 };
568 };
569
570 pwm4_pins_b: pwm4-1 {
571 pins {
572 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
573 bias-pull-down;
574 drive-push-pull;
575 slew-rate = <0>;
576 };
577 };
578
579 pwm4_sleep_pins_b: pwm4-sleep-1 {
580 pins {
581 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
582 };
583 };
584
585 pwm5_pins_a: pwm5-0 {
586 pins {
587 pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */
588 bias-pull-down;
589 drive-push-pull;
590 slew-rate = <0>;
591 };
592 };
593
594 pwm5_sleep_pins_a: pwm5-sleep-0 {
595 pins {
596 pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */
597 };
598 };
599
600 pwm8_pins_a: pwm8-0 {
601 pins {
602 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
603 bias-pull-down;
604 drive-push-pull;
605 slew-rate = <0>;
606 };
607 };
608
609 pwm8_sleep_pins_a: pwm8-sleep-0 {
610 pins {
611 pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */
612 };
613 };
614
615 pwm12_pins_a: pwm12-0 {
616 pins {
617 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
618 bias-pull-down;
619 drive-push-pull;
620 slew-rate = <0>;
621 };
622 };
623
624 pwm12_sleep_pins_a: pwm12-sleep-0 {
625 pins {
626 pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */
627 };
628 };
629
630 qspi_clk_pins_a: qspi-clk-0 {
631 pins {
632 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
633 bias-disable;
634 drive-push-pull;
635 slew-rate = <3>;
636 };
637 };
638
639 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
640 pins {
641 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
642 };
643 };
644
645 qspi_bk1_pins_a: qspi-bk1-0 {
646 pins1 {
647 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
648 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
649 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
650 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
651 bias-disable;
652 drive-push-pull;
653 slew-rate = <1>;
654 };
655 pins2 {
656 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
657 bias-pull-up;
658 drive-push-pull;
659 slew-rate = <1>;
660 };
661 };
662
663 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
664 pins {
665 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
666 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
667 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
668 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
669 <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
670 };
671 };
672
673 qspi_bk2_pins_a: qspi-bk2-0 {
674 pins1 {
675 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
676 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
677 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
678 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
679 bias-disable;
680 drive-push-pull;
681 slew-rate = <1>;
682 };
683 pins2 {
684 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
685 bias-pull-up;
686 drive-push-pull;
687 slew-rate = <1>;
688 };
689 };
690
691 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
692 pins {
693 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
694 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
695 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
696 <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
697 <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
698 };
699 };
700
701 sai2a_pins_a: sai2a-0 {
702 pins {
703 pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
704 <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
705 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
706 <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
707 slew-rate = <0>;
708 drive-push-pull;
709 bias-disable;
710 };
711 };
712
713 sai2a_sleep_pins_a: sai2a-1 {
714 pins {
715 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
716 <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
717 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
718 <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
719 };
720 };
721
722
723 sai2a_pins_b: sai2a-2 {
724 pins1 {
725 pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
726 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
727 <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */
728 slew-rate = <0>;
729 drive-push-pull;
730 bias-disable;
731 };
732 };
733
734 sai2a_sleep_pins_b: sai2a-sleep-3 {
735 pins {
736 pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
737 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
738 <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */
739 };
740 };
741
742 sai2b_pins_a: sai2b-0 {
743 pins1 {
744 pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
745 <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
746 <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
747 slew-rate = <0>;
748 drive-push-pull;
749 bias-disable;
750 };
751 pins2 {
752 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
753 bias-disable;
754 };
755 };
756
757 sai2b_sleep_pins_a: sai2b-1 {
758 pins {
759 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
760 <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
761 <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
762 <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
763 };
764 };
765
766 sai2b_pins_b: sai2b-2 {
767 pins {
768 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
769 bias-disable;
770 };
771 };
772
773 sai2b_sleep_pins_b: sai2b-3 {
774 pins {
775 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
776 };
777 };
778
779 sai4a_pins_a: sai4a-0 {
780 pins {
781 pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
782 slew-rate = <0>;
783 drive-push-pull;
784 bias-disable;
785 };
786 };
787
788 sai4a_sleep_pins_a: sai4a-1 {
789 pins {
790 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
791 };
792 };
793
794 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
795 pins1 {
796 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
797 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
798 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
799 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
800 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
801 slew-rate = <1>;
802 drive-push-pull;
803 bias-disable;
804 };
805 pins2 {
806 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
807 slew-rate = <2>;
808 drive-push-pull;
809 bias-disable;
810 };
811 };
812
813 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
814 pins1 {
815 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
816 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
817 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
818 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
819 slew-rate = <1>;
820 drive-push-pull;
821 bias-disable;
822 };
823 pins2 {
824 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
825 slew-rate = <2>;
826 drive-push-pull;
827 bias-disable;
828 };
829 pins3 {
830 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
831 slew-rate = <1>;
832 drive-open-drain;
833 bias-disable;
834 };
835 };
836
837 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
838 pins {
839 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
840 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
841 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
842 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
843 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
844 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
845 };
846 };
847
848 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
849 pins1 {
850 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
851 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
852 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
853 slew-rate = <1>;
854 drive-push-pull;
855 bias-pull-up;
856 };
857 pins2{
858 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
859 bias-pull-up;
860 };
861 };
862
863 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
864 pins {
865 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
866 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
867 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
868 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
869 };
870 };
871
872 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
873 pins1 {
874 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
875 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
876 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
877 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
878 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
879 slew-rate = <1>;
880 drive-push-pull;
881 bias-pull-up;
882 };
883 pins2 {
884 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
885 slew-rate = <2>;
886 drive-push-pull;
887 bias-pull-up;
888 };
889 };
890
891 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
892 pins1 {
893 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
894 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
895 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
896 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
897 slew-rate = <1>;
898 drive-push-pull;
899 bias-pull-up;
900 };
901 pins2 {
902 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
903 slew-rate = <2>;
904 drive-push-pull;
905 bias-pull-up;
906 };
907 pins3 {
908 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
909 slew-rate = <1>;
910 drive-open-drain;
911 bias-pull-up;
912 };
913 };
914
915 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
916 pins {
917 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
918 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
919 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
920 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
921 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
922 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
923 };
924 };
925
926 sdmmc2_b4_pins_b: sdmmc2-b4-1 {
927 pins1 {
928 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
929 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
930 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
931 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
932 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
933 slew-rate = <1>;
934 drive-push-pull;
935 bias-disable;
936 };
937 pins2 {
938 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
939 slew-rate = <2>;
940 drive-push-pull;
941 bias-disable;
942 };
943 };
944
945 sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
946 pins1 {
947 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
948 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
949 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
950 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
951 slew-rate = <1>;
952 drive-push-pull;
953 bias-disable;
954 };
955 pins2 {
956 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
957 slew-rate = <2>;
958 drive-push-pull;
959 bias-disable;
960 };
961 pins3 {
962 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
963 slew-rate = <1>;
964 drive-open-drain;
965 bias-disable;
966 };
967 };
968
969 sdmmc2_d47_pins_a: sdmmc2-d47-0 {
970 pins {
971 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
972 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
973 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
974 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
975 slew-rate = <1>;
976 drive-push-pull;
977 bias-pull-up;
978 };
979 };
980
981 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
982 pins {
983 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
984 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
985 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
986 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
987 };
988 };
989
990 sdmmc3_b4_pins_a: sdmmc3-b4-0 {
991 pins1 {
992 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
993 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
994 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
995 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
996 <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
997 slew-rate = <1>;
998 drive-push-pull;
999 bias-pull-up;
1000 };
1001 pins2 {
1002 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
1003 slew-rate = <2>;
1004 drive-push-pull;
1005 bias-pull-up;
1006 };
1007 };
1008
1009 sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
1010 pins1 {
1011 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1012 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1013 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
1014 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
1015 slew-rate = <1>;
1016 drive-push-pull;
1017 bias-pull-up;
1018 };
1019 pins2 {
1020 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
1021 slew-rate = <2>;
1022 drive-push-pull;
1023 bias-pull-up;
1024 };
1025 pins3 {
1026 pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
1027 slew-rate = <1>;
1028 drive-open-drain;
1029 bias-pull-up;
1030 };
1031 };
1032
1033 sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
1034 pins {
1035 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
1036 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
1037 <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
1038 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
1039 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
1040 <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
1041 };
1042 };
1043
1044 spdifrx_pins_a: spdifrx-0 {
1045 pins {
1046 pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
1047 bias-disable;
1048 };
1049 };
1050
1051 spdifrx_sleep_pins_a: spdifrx-1 {
1052 pins {
1053 pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
1054 };
1055 };
1056
1057 usart3_pins_a: usart3-0 {
1058 pins1 {
1059 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
1060 bias-disable;
1061 drive-push-pull;
1062 slew-rate = <0>;
1063 };
1064 pins2 {
1065 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
1066 bias-disable;
1067 };
1068 };
1069
1070 uart4_pins_a: uart4-0 {
1071 pins1 {
1072 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
1073 bias-disable;
1074 drive-push-pull;
1075 slew-rate = <0>;
1076 };
1077 pins2 {
1078 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
1079 bias-disable;
1080 };
1081 };
1082
1083 uart4_pins_b: uart4-1 {
1084 pins1 {
1085 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
1086 bias-disable;
1087 drive-push-pull;
1088 slew-rate = <0>;
1089 };
1090 pins2 {
1091 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
1092 bias-disable;
1093 };
1094 };
1095
1096 uart7_pins_a: uart7-0 {
1097 pins1 {
1098 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
1099 bias-disable;
1100 drive-push-pull;
1101 slew-rate = <0>;
1102 };
1103 pins2 {
1104 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
1105 <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
1106 <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
1107 bias-disable;
1108 };
1109 };
1110
1111 uart8_pins_a: uart8-0 {
1112 pins1 {
1113 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
1114 bias-disable;
1115 drive-push-pull;
1116 slew-rate = <0>;
1117 };
1118 pins2 {
1119 pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
1120 bias-disable;
1121 };
1122 };
1123
1124 usbotg_hs_pins_a: usbotg-hs-0 {
1125 pins {
1126 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
1127 };
1128 };
1129
1130 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
1131 pins {
1132 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
1133 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
1134 };
1135 };
1136};
1137
1138&pinctrl_z {
1139 i2c2_pins_b2: i2c2-0 {
1140 pins {
1141 pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
1142 bias-disable;
1143 drive-open-drain;
1144 slew-rate = <0>;
1145 };
1146 };
1147
1148 i2c2_pins_sleep_b2: i2c2-1 {
1149 pins {
1150 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
1151 };
1152 };
1153
1154 i2c4_pins_a: i2c4-0 {
1155 pins {
1156 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
1157 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
1158 bias-disable;
1159 drive-open-drain;
1160 slew-rate = <0>;
1161 };
1162 };
1163
1164 i2c4_pins_sleep_a: i2c4-1 {
1165 pins {
1166 pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
1167 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
1168 };
1169 };
1170
1171 spi1_pins_a: spi1-0 {
1172 pins1 {
1173 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
1174 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
1175 bias-disable;
1176 drive-push-pull;
1177 slew-rate = <1>;
1178 };
1179
1180 pins2 {
1181 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
1182 bias-disable;
1183 };
1184 };
1185};