tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_SDMA_H__
25#define __AMDGPU_SDMA_H__
26
27/* max number of IP instances */
28#define AMDGPU_MAX_SDMA_INSTANCES 8
29
30enum amdgpu_sdma_irq {
31 AMDGPU_SDMA_IRQ_INSTANCE0 = 0,
32 AMDGPU_SDMA_IRQ_INSTANCE1,
33 AMDGPU_SDMA_IRQ_INSTANCE2,
34 AMDGPU_SDMA_IRQ_INSTANCE3,
35 AMDGPU_SDMA_IRQ_INSTANCE4,
36 AMDGPU_SDMA_IRQ_INSTANCE5,
37 AMDGPU_SDMA_IRQ_INSTANCE6,
38 AMDGPU_SDMA_IRQ_INSTANCE7,
39 AMDGPU_SDMA_IRQ_LAST
40};
41
42struct amdgpu_sdma_instance {
43 /* SDMA firmware */
44 const struct firmware *fw;
45 uint32_t fw_version;
46 uint32_t feature_version;
47
48 struct amdgpu_ring ring;
49 struct amdgpu_ring page;
50 bool burst_nop;
51};
52
53struct amdgpu_sdma_ras_funcs {
54 int (*ras_late_init)(struct amdgpu_device *adev,
55 void *ras_ih_info);
56 void (*ras_fini)(struct amdgpu_device *adev);
57 int (*query_ras_error_count)(struct amdgpu_device *adev,
58 uint32_t instance, void *ras_error_status);
59 void (*reset_ras_error_count)(struct amdgpu_device *adev);
60};
61
62struct amdgpu_sdma {
63 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
64 struct drm_gpu_scheduler *sdma_sched[AMDGPU_MAX_SDMA_INSTANCES];
65 uint32_t num_sdma_sched;
66 struct amdgpu_irq_src trap_irq;
67 struct amdgpu_irq_src illegal_inst_irq;
68 struct amdgpu_irq_src ecc_irq;
69 int num_instances;
70 uint32_t srbm_soft_reset;
71 bool has_page_queue;
72 struct ras_common_if *ras_if;
73 const struct amdgpu_sdma_ras_funcs *funcs;
74};
75
76/*
77 * Provided by hw blocks that can move/clear data. e.g., gfx or sdma
78 * But currently, we use sdma to move data.
79 */
80struct amdgpu_buffer_funcs {
81 /* maximum bytes in a single operation */
82 uint32_t copy_max_bytes;
83
84 /* number of dw to reserve per operation */
85 unsigned copy_num_dw;
86
87 /* used for buffer migration */
88 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
89 /* src addr in bytes */
90 uint64_t src_offset,
91 /* dst addr in bytes */
92 uint64_t dst_offset,
93 /* number of byte to transfer */
94 uint32_t byte_count);
95
96 /* maximum bytes in a single operation */
97 uint32_t fill_max_bytes;
98
99 /* number of dw to reserve per operation */
100 unsigned fill_num_dw;
101
102 /* used for buffer clearing */
103 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
104 /* value to write to memory */
105 uint32_t src_data,
106 /* dst addr in bytes */
107 uint64_t dst_offset,
108 /* number of byte to fill */
109 uint32_t byte_count);
110};
111
112#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
113#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
114
115struct amdgpu_sdma_instance *
116amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
117int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
118uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
119int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
120 void *ras_ih_info);
121void amdgpu_sdma_ras_fini(struct amdgpu_device *adev);
122int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
123 void *err_data,
124 struct amdgpu_iv_entry *entry);
125int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
126 struct amdgpu_irq_src *source,
127 struct amdgpu_iv_entry *entry);
128#endif