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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 */
4#ifndef _ASM_POWERPC_CACHEFLUSH_H
5#define _ASM_POWERPC_CACHEFLUSH_H
6
7#ifdef __KERNEL__
8
9#include <linux/mm.h>
10#include <asm/cputable.h>
11
12/*
13 * No cache flushing is required when address mappings are changed,
14 * because the caches on PowerPCs are physically addressed.
15 */
16#define flush_cache_all() do { } while (0)
17#define flush_cache_mm(mm) do { } while (0)
18#define flush_cache_dup_mm(mm) do { } while (0)
19#define flush_cache_range(vma, start, end) do { } while (0)
20#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
21#define flush_icache_page(vma, page) do { } while (0)
22#define flush_cache_vunmap(start, end) do { } while (0)
23
24#ifdef CONFIG_PPC_BOOK3S_64
25/*
26 * Book3s has no ptesync after setting a pte, so without this ptesync it's
27 * possible for a kernel virtual mapping access to return a spurious fault
28 * if it's accessed right after the pte is set. The page fault handler does
29 * not expect this type of fault. flush_cache_vmap is not exactly the right
30 * place to put this, but it seems to work well enough.
31 */
32static inline void flush_cache_vmap(unsigned long start, unsigned long end)
33{
34 asm volatile("ptesync" ::: "memory");
35}
36#else
37static inline void flush_cache_vmap(unsigned long start, unsigned long end) { }
38#endif
39
40#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
41extern void flush_dcache_page(struct page *page);
42#define flush_dcache_mmap_lock(mapping) do { } while (0)
43#define flush_dcache_mmap_unlock(mapping) do { } while (0)
44
45void flush_icache_range(unsigned long start, unsigned long stop);
46extern void flush_icache_user_range(struct vm_area_struct *vma,
47 struct page *page, unsigned long addr,
48 int len);
49extern void flush_dcache_icache_page(struct page *page);
50void __flush_dcache_icache(void *page);
51
52/**
53 * flush_dcache_range(): Write any modified data cache blocks out to memory and
54 * invalidate them. Does not invalidate the corresponding instruction cache
55 * blocks.
56 *
57 * @start: the start address
58 * @stop: the stop address (exclusive)
59 */
60static inline void flush_dcache_range(unsigned long start, unsigned long stop)
61{
62 unsigned long shift = l1_dcache_shift();
63 unsigned long bytes = l1_dcache_bytes();
64 void *addr = (void *)(start & ~(bytes - 1));
65 unsigned long size = stop - (unsigned long)addr + (bytes - 1);
66 unsigned long i;
67
68 if (IS_ENABLED(CONFIG_PPC64))
69 mb(); /* sync */
70
71 for (i = 0; i < size >> shift; i++, addr += bytes)
72 dcbf(addr);
73 mb(); /* sync */
74
75}
76
77/*
78 * Write any modified data cache blocks out to memory.
79 * Does not invalidate the corresponding cache lines (especially for
80 * any corresponding instruction cache).
81 */
82static inline void clean_dcache_range(unsigned long start, unsigned long stop)
83{
84 unsigned long shift = l1_dcache_shift();
85 unsigned long bytes = l1_dcache_bytes();
86 void *addr = (void *)(start & ~(bytes - 1));
87 unsigned long size = stop - (unsigned long)addr + (bytes - 1);
88 unsigned long i;
89
90 for (i = 0; i < size >> shift; i++, addr += bytes)
91 dcbst(addr);
92 mb(); /* sync */
93}
94
95/*
96 * Like above, but invalidate the D-cache. This is used by the 8xx
97 * to invalidate the cache so the PPC core doesn't get stale data
98 * from the CPM (no cache snooping here :-).
99 */
100static inline void invalidate_dcache_range(unsigned long start,
101 unsigned long stop)
102{
103 unsigned long shift = l1_dcache_shift();
104 unsigned long bytes = l1_dcache_bytes();
105 void *addr = (void *)(start & ~(bytes - 1));
106 unsigned long size = stop - (unsigned long)addr + (bytes - 1);
107 unsigned long i;
108
109 for (i = 0; i < size >> shift; i++, addr += bytes)
110 dcbi(addr);
111 mb(); /* sync */
112}
113
114#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
115 do { \
116 memcpy(dst, src, len); \
117 flush_icache_user_range(vma, page, vaddr, len); \
118 } while (0)
119#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
120 memcpy(dst, src, len)
121
122#endif /* __KERNEL__ */
123
124#endif /* _ASM_POWERPC_CACHEFLUSH_H */