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1* Atmel Extensible Direct Memory Access Controller (XDMAC)
2
3* XDMA Controller
4Required properties:
5- compatible: Should be "atmel,sama5d4-dma" or "microchip,sam9x60-dma".
6- reg: Should contain DMA registers location and length.
7- interrupts: Should contain DMA interrupt.
8- #dma-cells: Must be <1>, used to represent the number of integer cells in
9the dmas property of client devices.
10 - The 1st cell specifies the channel configuration register:
11 - bit 13: SIF, source interface identifier, used to get the memory
12 interface identifier,
13 - bit 14: DIF, destination interface identifier, used to get the peripheral
14 interface identifier,
15 - bit 30-24: PERID, peripheral identifier.
16
17Example:
18
19dma1: dma-controller@f0004000 {
20 compatible = "atmel,sama5d4-dma";
21 reg = <0xf0004000 0x200>;
22 interrupts = <50 4 0>;
23 #dma-cells = <1>;
24};
25
26
27* DMA clients
28DMA clients connected to the Atmel XDMA controller must use the format
29described in the dma.txt file, using a one-cell specifier for each channel.
30The two cells in order are:
311. A phandle pointing to the DMA controller.
322. Channel configuration register. Configurable fields are:
33 - bit 13: SIF, source interface identifier, used to get the memory
34 interface identifier,
35 - bit 14: DIF, destination interface identifier, used to get the peripheral
36 interface identifier,
37 - bit 30-24: PERID, peripheral identifier.
38
39Example:
40
41i2c2: i2c@f8024000 {
42 compatible = "atmel,at91sam9x5-i2c";
43 reg = <0xf8024000 0x4000>;
44 interrupts = <34 4 6>;
45 dmas = <&dma1
46 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
47 | AT91_XDMAC_DT_PERID(6))>,
48 <&dma1
49 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
50 | AT91_XDMAC_DT_PERID(7))>;
51 dma-names = "tx", "rx";
52};