tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
3/*
4 * Device tree file for ZII's SPB4 board
5 *
6 * SPB - Seat Power Box
7 *
8 * Copyright (C) 2019 Zodiac Inflight Innovations
9 */
10
11/dts-v1/;
12#include "vf610.dtsi"
13
14/ {
15 model = "ZII VF610 SPB4 Board";
16 compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610";
17
18 chosen {
19 stdout-path = &uart0;
20 };
21
22 memory@80000000 {
23 device_type = "memory";
24 reg = <0x80000000 0x20000000>;
25 };
26
27 gpio-leds {
28 compatible = "gpio-leds";
29 pinctrl-0 = <&pinctrl_leds_debug>;
30 pinctrl-names = "default";
31
32 led-debug {
33 label = "zii:green:debug1";
34 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
35 linux,default-trigger = "heartbeat";
36 };
37 };
38
39 reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
40 compatible = "regulator-fixed";
41 regulator-name = "vcc_3v3_mcu";
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
44 };
45
46 supply-voltage-monitor {
47 compatible = "iio-hwmon";
48 io-channels = <&adc0 8>, /* 28V_SW */
49 <&adc0 9>, /* +3.3V */
50 <&adc1 8>, /* VCC_1V5 */
51 <&adc1 9>; /* VCC_1V2 */
52 };
53};
54
55&adc0 {
56 vref-supply = <®_vcc_3v3_mcu>;
57 status = "okay";
58};
59
60&adc1 {
61 vref-supply = <®_vcc_3v3_mcu>;
62 status = "okay";
63};
64
65&dspi1 {
66 bus-num = <1>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_dspi1>;
69 status = "okay";
70
71 flash@0 {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 compatible = "m25p128", "jedec,spi-nor";
75 reg = <0>;
76 spi-max-frequency = <50000000>;
77 };
78};
79
80&edma0 {
81 status = "okay";
82};
83
84&edma1 {
85 status = "okay";
86};
87
88&esdhc0 {
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_esdhc0>;
91 bus-width = <8>;
92 non-removable;
93 no-1-8-v;
94 keep-power-in-suspend;
95 no-sdio;
96 no-sd;
97 status = "okay";
98};
99
100&esdhc1 {
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_esdhc1>;
103 bus-width = <4>;
104 no-sdio;
105 status = "okay";
106};
107
108&fec1 {
109 phy-mode = "rmii";
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_fec1>;
112 status = "okay";
113
114 fixed-link {
115 speed = <100>;
116 full-duplex;
117 };
118
119 mdio1: mdio {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 status = "okay";
123
124 switch0: switch0@0 {
125 compatible = "marvell,mv88e6190";
126 pinctrl-0 = <&pinctrl_gpio_switch0>;
127 pinctrl-names = "default";
128 reg = <0>;
129 eeprom-length = <65536>;
130 reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
131 interrupt-parent = <&gpio3>;
132 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
133 interrupt-controller;
134 #interrupt-cells = <2>;
135
136 ports {
137 #address-cells = <1>;
138 #size-cells = <0>;
139
140 port@0 {
141 reg = <0>;
142 label = "cpu";
143 ethernet = <&fec1>;
144
145 fixed-link {
146 speed = <100>;
147 full-duplex;
148 };
149 };
150
151 port@1 {
152 reg = <1>;
153 label = "eth_cu_1000_1";
154 };
155
156 port@2 {
157 reg = <2>;
158 label = "eth_cu_1000_2";
159 };
160
161 port@3 {
162 reg = <3>;
163 label = "eth_cu_1000_3";
164 };
165
166 port@4 {
167 reg = <4>;
168 label = "eth_cu_1000_4";
169 };
170
171 port@5 {
172 reg = <5>;
173 label = "eth_cu_1000_5";
174 };
175
176 port@6 {
177 reg = <6>;
178 label = "eth_cu_1000_6";
179 };
180 };
181 };
182 };
183};
184
185&i2c0 {
186 clock-frequency = <100000>;
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_i2c0>;
189 status = "okay";
190
191 io-expander@22 {
192 compatible = "nxp,pca9554";
193 reg = <0x22>;
194 gpio-controller;
195 #gpio-cells = <2>;
196 };
197
198 eeprom@50 {
199 compatible = "atmel,24c04";
200 reg = <0x50>;
201 label = "nameplate";
202 };
203
204 eeprom@52 {
205 compatible = "atmel,24c04";
206 reg = <0x52>;
207 };
208};
209
210&snvsrtc {
211 status = "disabled";
212};
213
214&uart0 {
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_uart0>;
217 status = "okay";
218};
219
220&uart1 {
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_uart1>;
223 status = "okay";
224};
225
226&uart2 {
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_uart2>;
229 status = "okay";
230
231 rave-sp {
232 compatible = "zii,rave-sp-rdu2";
233 current-speed = <1000000>;
234 #address-cells = <1>;
235 #size-cells = <1>;
236
237 watchdog {
238 compatible = "zii,rave-sp-watchdog";
239 };
240
241 eeprom@a3 {
242 compatible = "zii,rave-sp-eeprom";
243 reg = <0xa3 0x4000>;
244 #address-cells = <1>;
245 #size-cells = <1>;
246 zii,eeprom-name = "main-eeprom";
247 };
248 };
249};
250
251&uart3 {
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_uart3>;
254 status = "okay";
255};
256
257&wdoga5 {
258 status = "disabled";
259};
260
261&iomuxc {
262 pinctrl_dspi1: dspi1grp {
263 fsl,pins = <
264 VF610_PAD_PTD5__DSPI1_CS0 0x1182
265 VF610_PAD_PTD4__DSPI1_CS1 0x1182
266 VF610_PAD_PTC6__DSPI1_SIN 0x1181
267 VF610_PAD_PTC7__DSPI1_SOUT 0x1182
268 VF610_PAD_PTC8__DSPI1_SCK 0x1182
269 >;
270 };
271
272 pinctrl_esdhc0: esdhc0grp {
273 fsl,pins = <
274 VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
275 VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
276 VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
277 VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
278 VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
279 VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
280 VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
281 VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
282 VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
283 VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
284 >;
285 };
286
287 pinctrl_esdhc1: esdhc1grp {
288 fsl,pins = <
289 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
290 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
291 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
292 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
293 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
294 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
295 >;
296 };
297
298 pinctrl_fec1: fec1grp {
299 fsl,pins = <
300 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
301 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
302 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
303 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
304 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
305 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
306 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
307 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
308 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
309 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
310 >;
311 };
312
313 pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
314 fsl,pins = <
315 VF610_PAD_PTE2__GPIO_107 0x31c2
316 VF610_PAD_PTB28__GPIO_98 0x219d
317 >;
318 };
319
320 pinctrl_i2c0: i2c0grp {
321 fsl,pins = <
322 VF610_PAD_PTB14__I2C0_SCL 0x37ff
323 VF610_PAD_PTB15__I2C0_SDA 0x37ff
324 >;
325 };
326
327 pinctrl_leds_debug: pinctrl-leds-debug {
328 fsl,pins = <
329 VF610_PAD_PTD3__GPIO_82 0x31c2
330 >;
331 };
332
333 pinctrl_uart0: uart0grp {
334 fsl,pins = <
335 VF610_PAD_PTB10__UART0_TX 0x21a2
336 VF610_PAD_PTB11__UART0_RX 0x21a1
337 >;
338 };
339
340 pinctrl_uart1: uart1grp {
341 fsl,pins = <
342 VF610_PAD_PTB23__UART1_TX 0x21a2
343 VF610_PAD_PTB24__UART1_RX 0x21a1
344 >;
345 };
346
347 pinctrl_uart2: uart2grp {
348 fsl,pins = <
349 VF610_PAD_PTD0__UART2_TX 0x21a2
350 VF610_PAD_PTD1__UART2_RX 0x21a1
351 >;
352 };
353
354 pinctrl_uart3: uart3grp {
355 fsl,pins = <
356 VF610_PAD_PTA30__UART3_TX 0x21a2
357 VF610_PAD_PTA31__UART3_RX 0x21a1
358 >;
359 };
360};