tjh.dev
Linux kernel mirror (for testing)
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1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
4 */
5
6#include <dt-bindings/clock/marvell,mmp2.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "marvell,mmp3-smp";
17
18 cpu@0 {
19 compatible = "marvell,pj4b";
20 device_type = "cpu";
21 next-level-cache = <&l2>;
22 reg = <0>;
23 };
24
25 cpu@1 {
26 compatible = "marvell,pj4b";
27 device_type = "cpu";
28 next-level-cache = <&l2>;
29 reg = <1>;
30 };
31 };
32
33 soc {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "simple-bus";
37 interrupt-parent = <&gic>;
38 ranges;
39
40 axi@d4200000 {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 reg = <0xd4200000 0x00200000>;
45 ranges;
46
47 interrupt-controller@d4282000 {
48 compatible = "marvell,mmp3-intc";
49 interrupt-controller;
50 #interrupt-cells = <1>;
51 reg = <0xd4282000 0x1000>,
52 <0xd4284000 0x100>;
53 mrvl,intc-nr-irqs = <64>;
54 };
55
56 pmic_mux: interrupt-controller@d4282150 {
57 compatible = "mrvl,mmp2-mux-intc";
58 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
59 interrupt-controller;
60 #interrupt-cells = <1>;
61 reg = <0x150 0x4>, <0x168 0x4>;
62 reg-names = "mux status", "mux mask";
63 mrvl,intc-nr-irqs = <4>;
64 };
65
66 rtc_mux: interrupt-controller@d4282154 {
67 compatible = "mrvl,mmp2-mux-intc";
68 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-controller;
70 #interrupt-cells = <1>;
71 reg = <0x154 0x4>, <0x16c 0x4>;
72 reg-names = "mux status", "mux mask";
73 mrvl,intc-nr-irqs = <2>;
74 };
75
76 hsi3_mux: interrupt-controller@d42821bc {
77 compatible = "mrvl,mmp2-mux-intc";
78 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
79 interrupt-controller;
80 #interrupt-cells = <1>;
81 reg = <0x1bc 0x4>, <0x1a4 0x4>;
82 reg-names = "mux status", "mux mask";
83 mrvl,intc-nr-irqs = <3>;
84 };
85
86 gpu_mux: interrupt-controller@d42821c0 {
87 compatible = "mrvl,mmp2-mux-intc";
88 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
89 interrupt-controller;
90 #interrupt-cells = <1>;
91 reg = <0x1c0 0x4>, <0x1a8 0x4>;
92 reg-names = "mux status", "mux mask";
93 mrvl,intc-nr-irqs = <3>;
94 };
95
96 twsi_mux: interrupt-controller@d4282158 {
97 compatible = "mrvl,mmp2-mux-intc";
98 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
99 interrupt-controller;
100 #interrupt-cells = <1>;
101 reg = <0x158 0x4>, <0x170 0x4>;
102 reg-names = "mux status", "mux mask";
103 mrvl,intc-nr-irqs = <5>;
104 };
105
106 hsi2_mux: interrupt-controller@d42821c4 {
107 compatible = "mrvl,mmp2-mux-intc";
108 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
109 interrupt-controller;
110 #interrupt-cells = <1>;
111 reg = <0x1c4 0x4>, <0x1ac 0x4>;
112 reg-names = "mux status", "mux mask";
113 mrvl,intc-nr-irqs = <2>;
114 };
115
116 dxo_mux: interrupt-controller@d42821c8 {
117 compatible = "mrvl,mmp2-mux-intc";
118 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
119 interrupt-controller;
120 #interrupt-cells = <1>;
121 reg = <0x1c8 0x4>, <0x1b0 0x4>;
122 reg-names = "mux status", "mux mask";
123 mrvl,intc-nr-irqs = <2>;
124 };
125
126 misc1_mux: interrupt-controller@d428215c {
127 compatible = "mrvl,mmp2-mux-intc";
128 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
129 interrupt-controller;
130 #interrupt-cells = <1>;
131 reg = <0x15c 0x4>, <0x174 0x4>;
132 reg-names = "mux status", "mux mask";
133 mrvl,intc-nr-irqs = <31>;
134 };
135
136 ci_mux: interrupt-controller@d42821cc {
137 compatible = "mrvl,mmp2-mux-intc";
138 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
139 interrupt-controller;
140 #interrupt-cells = <1>;
141 reg = <0x1cc 0x4>, <0x1b4 0x4>;
142 reg-names = "mux status", "mux mask";
143 mrvl,intc-nr-irqs = <2>;
144 };
145
146 ssp_mux: interrupt-controller@d4282160 {
147 compatible = "mrvl,mmp2-mux-intc";
148 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
149 interrupt-controller;
150 #interrupt-cells = <1>;
151 reg = <0x160 0x4>, <0x178 0x4>;
152 reg-names = "mux status", "mux mask";
153 mrvl,intc-nr-irqs = <2>;
154 };
155
156 hsi1_mux: interrupt-controller@d4282184 {
157 compatible = "mrvl,mmp2-mux-intc";
158 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
159 interrupt-controller;
160 #interrupt-cells = <1>;
161 reg = <0x184 0x4>, <0x17c 0x4>;
162 reg-names = "mux status", "mux mask";
163 mrvl,intc-nr-irqs = <4>;
164 };
165
166 misc2_mux: interrupt-controller@d4282188 {
167 compatible = "mrvl,mmp2-mux-intc";
168 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
169 interrupt-controller;
170 #interrupt-cells = <1>;
171 reg = <0x188 0x4>, <0x180 0x4>;
172 reg-names = "mux status", "mux mask";
173 mrvl,intc-nr-irqs = <20>;
174 };
175
176 hsi0_mux: interrupt-controller@d42821d0 {
177 compatible = "mrvl,mmp2-mux-intc";
178 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
179 interrupt-controller;
180 #interrupt-cells = <1>;
181 reg = <0x1d0 0x4>, <0x1b8 0x4>;
182 reg-names = "mux status", "mux mask";
183 mrvl,intc-nr-irqs = <5>;
184 };
185
186 usb_otg_phy0: usb-otg-phy@d4207000 {
187 compatible = "marvell,mmp3-usb-phy";
188 reg = <0xd4207000 0x40>;
189 #phy-cells = <0>;
190 status = "disabled";
191 };
192
193 usb_otg0: usb-otg@d4208000 {
194 compatible = "marvell,pxau2o-ehci";
195 reg = <0xd4208000 0x200>;
196 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&soc_clocks MMP2_CLK_USB>;
198 clock-names = "USBCLK";
199 phys = <&usb_otg_phy0>;
200 phy-names = "usb";
201 status = "disabled";
202 };
203
204 hsic_phy0: hsic-phy@f0001800 {
205 compatible = "marvell,mmp3-hsic-phy",
206 "usb-nop-xceiv";
207 reg = <0xf0001800 0x40>;
208 #phy-cells = <0>;
209 status = "disabled";
210 };
211
212 hsic0: hsic@f0001000 {
213 compatible = "marvell,pxau2o-ehci";
214 reg = <0xf0001000 0x200>;
215 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&soc_clocks MMP2_CLK_USBHSIC0>;
217 clock-names = "USBCLK";
218 phys = <&hsic_phy0>;
219 phy-names = "usb";
220 phy_type = "hsic";
221 #address-cells = <0x01>;
222 #size-cells = <0x00>;
223 status = "disabled";
224 };
225
226 hsic_phy1: hsic-phy@f0002800 {
227 compatible = "marvell,mmp3-hsic-phy",
228 "usb-nop-xceiv";
229 reg = <0xf0002800 0x40>;
230 #phy-cells = <0>;
231 status = "disabled";
232 };
233
234 hsic1: hsic@f0002000 {
235 compatible = "marvell,pxau2o-ehci";
236 reg = <0xf0002000 0x200>;
237 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&soc_clocks MMP2_CLK_USBHSIC1>;
239 clock-names = "USBCLK";
240 phys = <&hsic_phy1>;
241 phy-names = "usb";
242 phy_type = "hsic";
243 #address-cells = <0x01>;
244 #size-cells = <0x00>;
245 status = "disabled";
246 };
247
248 mmc1: mmc@d4280000 {
249 compatible = "mrvl,pxav3-mmc";
250 reg = <0xd4280000 0x120>;
251 clocks = <&soc_clocks MMP2_CLK_SDH0>;
252 clock-names = "io";
253 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
254 status = "disabled";
255 };
256
257 mmc2: mmc@d4280800 {
258 compatible = "mrvl,pxav3-mmc";
259 reg = <0xd4280800 0x120>;
260 clocks = <&soc_clocks MMP2_CLK_SDH1>;
261 clock-names = "io";
262 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
263 status = "disabled";
264 };
265
266 mmc3: mmc@d4281000 {
267 compatible = "mrvl,pxav3-mmc";
268 reg = <0xd4281000 0x120>;
269 clocks = <&soc_clocks MMP2_CLK_SDH2>;
270 clock-names = "io";
271 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
272 status = "disabled";
273 };
274
275 mmc4: mmc@d4281800 {
276 compatible = "mrvl,pxav3-mmc";
277 reg = <0xd4281800 0x120>;
278 clocks = <&soc_clocks MMP2_CLK_SDH3>;
279 clock-names = "io";
280 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
281 status = "disabled";
282 };
283
284 camera0: camera@d420a000 {
285 compatible = "marvell,mmp2-ccic";
286 reg = <0xd420a000 0x800>;
287 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&soc_clocks MMP2_CLK_CCIC0>;
289 clock-names = "axi";
290 #clock-cells = <0>;
291 clock-output-names = "mclk";
292 status = "disabled";
293 };
294
295 camera1: camera@d420a800 {
296 compatible = "marvell,mmp2-ccic";
297 reg = <0xd420a800 0x800>;
298 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&soc_clocks MMP2_CLK_CCIC1>;
300 clock-names = "axi";
301 #clock-cells = <0>;
302 clock-output-names = "mclk";
303 status = "disabled";
304 };
305 };
306
307 apb@d4000000 {
308 compatible = "simple-bus";
309 #address-cells = <1>;
310 #size-cells = <1>;
311 reg = <0xd4000000 0x00200000>;
312 ranges;
313
314 timer: timer@d4014000 {
315 compatible = "mrvl,mmp-timer";
316 reg = <0xd4014000 0x100>;
317 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&soc_clocks MMP2_CLK_TIMER>;
319 };
320
321 uart1: serial@d4030000 {
322 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
323 reg = <0xd4030000 0x1000>;
324 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&soc_clocks MMP2_CLK_UART0>;
326 resets = <&soc_clocks MMP2_CLK_UART0>;
327 reg-shift = <2>;
328 status = "disabled";
329 };
330
331 uart2: serial@d4017000 {
332 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
333 reg = <0xd4017000 0x1000>;
334 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&soc_clocks MMP2_CLK_UART1>;
336 resets = <&soc_clocks MMP2_CLK_UART1>;
337 reg-shift = <2>;
338 status = "disabled";
339 };
340
341 uart3: serial@d4018000 {
342 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
343 reg = <0xd4018000 0x1000>;
344 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&soc_clocks MMP2_CLK_UART2>;
346 resets = <&soc_clocks MMP2_CLK_UART2>;
347 reg-shift = <2>;
348 status = "disabled";
349 };
350
351 uart4: serial@d4016000 {
352 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
353 reg = <0xd4016000 0x1000>;
354 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&soc_clocks MMP2_CLK_UART3>;
356 resets = <&soc_clocks MMP2_CLK_UART3>;
357 reg-shift = <2>;
358 status = "disabled";
359 };
360
361 gpio: gpio@d4019000 {
362 compatible = "marvell,mmp2-gpio";
363 #address-cells = <1>;
364 #size-cells = <1>;
365 reg = <0xd4019000 0x1000>;
366 gpio-controller;
367 #gpio-cells = <2>;
368 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
369 interrupt-names = "gpio_mux";
370 clocks = <&soc_clocks MMP2_CLK_GPIO>;
371 resets = <&soc_clocks MMP2_CLK_GPIO>;
372 interrupt-controller;
373 #interrupt-cells = <2>;
374 ranges;
375
376 gcb0: gpio@d4019000 {
377 reg = <0xd4019000 0x4>;
378 };
379
380 gcb1: gpio@d4019004 {
381 reg = <0xd4019004 0x4>;
382 };
383
384 gcb2: gpio@d4019008 {
385 reg = <0xd4019008 0x4>;
386 };
387
388 gcb3: gpio@d4019100 {
389 reg = <0xd4019100 0x4>;
390 };
391
392 gcb4: gpio@d4019104 {
393 reg = <0xd4019104 0x4>;
394 };
395
396 gcb5: gpio@d4019108 {
397 reg = <0xd4019108 0x4>;
398 };
399 };
400
401 twsi1: i2c@d4011000 {
402 compatible = "mrvl,mmp-twsi";
403 reg = <0xd4011000 0x70>;
404 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
406 resets = <&soc_clocks MMP2_CLK_TWSI0>;
407 #address-cells = <1>;
408 #size-cells = <0>;
409 mrvl,i2c-fast-mode;
410 status = "disabled";
411 };
412
413 twsi2: i2c@d4031000 {
414 compatible = "mrvl,mmp-twsi";
415 reg = <0xd4031000 0x70>;
416 interrupt-parent = <&twsi_mux>;
417 interrupts = <0>;
418 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
419 resets = <&soc_clocks MMP2_CLK_TWSI1>;
420 #address-cells = <1>;
421 #size-cells = <0>;
422 status = "disabled";
423 };
424
425 twsi3: i2c@d4032000 {
426 compatible = "mrvl,mmp-twsi";
427 reg = <0xd4032000 0x70>;
428 interrupt-parent = <&twsi_mux>;
429 interrupts = <1>;
430 clocks = <&soc_clocks MMP2_CLK_TWSI2>;
431 resets = <&soc_clocks MMP2_CLK_TWSI2>;
432 #address-cells = <1>;
433 #size-cells = <0>;
434 status = "disabled";
435 };
436
437 twsi4: i2c@d4033000 {
438 compatible = "mrvl,mmp-twsi";
439 reg = <0xd4033000 0x70>;
440 interrupt-parent = <&twsi_mux>;
441 interrupts = <2>;
442 clocks = <&soc_clocks MMP2_CLK_TWSI3>;
443 resets = <&soc_clocks MMP2_CLK_TWSI3>;
444 #address-cells = <1>;
445 #size-cells = <0>;
446 status = "disabled";
447 };
448
449
450 twsi5: i2c@d4033800 {
451 compatible = "mrvl,mmp-twsi";
452 reg = <0xd4033800 0x70>;
453 interrupt-parent = <&twsi_mux>;
454 interrupts = <3>;
455 clocks = <&soc_clocks MMP2_CLK_TWSI4>;
456 resets = <&soc_clocks MMP2_CLK_TWSI4>;
457 #address-cells = <1>;
458 #size-cells = <0>;
459 status = "disabled";
460 };
461
462 twsi6: i2c@d4034000 {
463 compatible = "mrvl,mmp-twsi";
464 reg = <0xd4034000 0x70>;
465 interrupt-parent = <&twsi_mux>;
466 interrupts = <4>;
467 clocks = <&soc_clocks MMP2_CLK_TWSI5>;
468 resets = <&soc_clocks MMP2_CLK_TWSI5>;
469 #address-cells = <1>;
470 #size-cells = <0>;
471 status = "disabled";
472 };
473
474 rtc: rtc@d4010000 {
475 compatible = "mrvl,mmp-rtc";
476 reg = <0xd4010000 0x1000>;
477 interrupts = <1 0>;
478 interrupt-names = "rtc 1Hz", "rtc alarm";
479 interrupt-parent = <&rtc_mux>;
480 clocks = <&soc_clocks MMP2_CLK_RTC>;
481 resets = <&soc_clocks MMP2_CLK_RTC>;
482 status = "disabled";
483 };
484
485 ssp1: spi@d4035000 {
486 compatible = "marvell,mmp2-ssp";
487 reg = <0xd4035000 0x1000>;
488 clocks = <&soc_clocks MMP2_CLK_SSP0>;
489 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
490 #address-cells = <1>;
491 #size-cells = <0>;
492 status = "disabled";
493 };
494
495 ssp2: spi@d4036000 {
496 compatible = "marvell,mmp2-ssp";
497 reg = <0xd4036000 0x1000>;
498 clocks = <&soc_clocks MMP2_CLK_SSP1>;
499 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
500 #address-cells = <1>;
501 #size-cells = <0>;
502 status = "disabled";
503 };
504
505 ssp3: spi@d4037000 {
506 compatible = "marvell,mmp2-ssp";
507 reg = <0xd4037000 0x1000>;
508 clocks = <&soc_clocks MMP2_CLK_SSP2>;
509 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
510 #address-cells = <1>;
511 #size-cells = <0>;
512 status = "disabled";
513 };
514
515 ssp4: spi@d4039000 {
516 compatible = "marvell,mmp2-ssp";
517 reg = <0xd4039000 0x1000>;
518 clocks = <&soc_clocks MMP2_CLK_SSP3>;
519 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
520 #address-cells = <1>;
521 #size-cells = <0>;
522 status = "disabled";
523 };
524 };
525
526 l2: l2-cache-controller@d0020000 {
527 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
528 reg = <0xd0020000 0x1000>;
529 cache-unified;
530 cache-level = <2>;
531 };
532
533 soc_clocks: clocks@d4050000 {
534 compatible = "marvell,mmp2-clock";
535 reg = <0xd4050000 0x1000>,
536 <0xd4282800 0x400>,
537 <0xd4015000 0x1000>;
538 reg-names = "mpmu", "apmu", "apbc";
539 #clock-cells = <1>;
540 #reset-cells = <1>;
541 #power-domain-cells = <1>;
542 };
543
544 snoop-control-unit@e0000000 {
545 compatible = "arm,arm11mp-scu";
546 reg = <0xe0000000 0x100>;
547 };
548
549 gic: interrupt-controller@e0001000 {
550 compatible = "arm,arm11mp-gic";
551 interrupt-controller;
552 #interrupt-cells = <3>;
553 reg = <0xe0001000 0x1000>,
554 <0xe0000100 0x100>;
555 };
556
557 local-timer@e0000600 {
558 compatible = "arm,arm11mp-twd-timer";
559 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
560 IRQ_TYPE_EDGE_RISING)>;
561 reg = <0xe0000600 0x20>;
562 };
563
564 watchdog@e0000620 {
565 compatible = "arm,arm11mp-twd-wdt";
566 reg = <0xe0000620 0x20>;
567 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
568 IRQ_TYPE_EDGE_RISING)>;
569 };
570 };
571};