tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2016 Gateworks Corporation
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include <dt-bindings/gpio/gpio.h>
49
50/ {
51 /* these are used by bootloader for disabling nodes */
52 aliases {
53 led0 = &led0;
54 led1 = &led1;
55 nand = &gpmi;
56 usb0 = &usbh1;
57 usb1 = &usbotg;
58 };
59
60 chosen {
61 stdout-path = &uart2;
62 };
63
64 leds {
65 compatible = "gpio-leds";
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_gpio_leds>;
68
69 led0: user1 {
70 label = "user1";
71 gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
72 default-state = "on";
73 linux,default-trigger = "heartbeat";
74 };
75
76 led1: user2 {
77 label = "user2";
78 gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
79 default-state = "off";
80 };
81 };
82
83 memory@10000000 {
84 device_type = "memory";
85 reg = <0x10000000 0x20000000>;
86 };
87
88 pps {
89 compatible = "pps-gpio";
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_pps>;
92 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
93 status = "okay";
94 };
95
96 reg_5p0v: regulator-5p0v {
97 compatible = "regulator-fixed";
98 regulator-name = "5P0V";
99 regulator-min-microvolt = <5000000>;
100 regulator-max-microvolt = <5000000>;
101 regulator-always-on;
102 };
103
104 reg_usb_otg_vbus: regulator-usb-otg-vbus {
105 compatible = "regulator-fixed";
106 regulator-name = "usb_otg_vbus";
107 regulator-min-microvolt = <5000000>;
108 regulator-max-microvolt = <5000000>;
109 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
110 enable-active-high;
111 };
112};
113
114&gpmi {
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_gpmi_nand>;
117 status = "okay";
118};
119
120&hdmi {
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_hdmi>;
123 ddc-i2c-bus = <&i2c3>;
124 status = "okay";
125};
126
127&i2c1 {
128 clock-frequency = <100000>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_i2c1>;
131 status = "okay";
132
133 gpio: pca9555@23 {
134 compatible = "nxp,pca9555";
135 reg = <0x23>;
136 gpio-controller;
137 #gpio-cells = <2>;
138 };
139
140 eeprom1: eeprom@50 {
141 compatible = "atmel,24c02";
142 reg = <0x50>;
143 pagesize = <16>;
144 };
145
146 eeprom2: eeprom@51 {
147 compatible = "atmel,24c02";
148 reg = <0x51>;
149 pagesize = <16>;
150 };
151
152 eeprom3: eeprom@52 {
153 compatible = "atmel,24c02";
154 reg = <0x52>;
155 pagesize = <16>;
156 };
157
158 eeprom4: eeprom@53 {
159 compatible = "atmel,24c02";
160 reg = <0x53>;
161 pagesize = <16>;
162 };
163
164 rtc: ds1672@68 {
165 compatible = "dallas,ds1672";
166 reg = <0x68>;
167 };
168};
169
170&i2c2 {
171 clock-frequency = <100000>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_i2c2>;
174 status = "okay";
175
176 magn@1c {
177 compatible = "st,lsm9ds1-magn";
178 reg = <0x1c>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_mag>;
181 interrupt-parent = <&gpio1>;
182 interrupts = <2 IRQ_TYPE_EDGE_RISING>;
183 };
184
185 imu@6a {
186 compatible = "st,lsm9ds1-imu";
187 reg = <0x6a>;
188 st,drdy-int-pin = <1>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_imu>;
191 interrupt-parent = <&gpio7>;
192 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
193 };
194
195 ltc3676: pmic@3c {
196 compatible = "lltc,ltc3676";
197 reg = <0x3c>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_pmic>;
200 interrupt-parent = <&gpio1>;
201 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
202
203 regulators {
204 /* VDD_SOC (1+R1/R2 = 1.635) */
205 reg_vdd_soc: sw1 {
206 regulator-name = "vddsoc";
207 regulator-min-microvolt = <674400>;
208 regulator-max-microvolt = <1308000>;
209 lltc,fb-voltage-divider = <127000 200000>;
210 regulator-ramp-delay = <7000>;
211 regulator-boot-on;
212 regulator-always-on;
213 };
214
215 /* VDD_DDR (1+R1/R2 = 2.105) */
216 reg_vdd_ddr: sw2 {
217 regulator-name = "vddddr";
218 regulator-min-microvolt = <868310>;
219 regulator-max-microvolt = <1684000>;
220 lltc,fb-voltage-divider = <221000 200000>;
221 regulator-ramp-delay = <7000>;
222 regulator-boot-on;
223 regulator-always-on;
224 };
225
226 /* VDD_ARM (1+R1/R2 = 1.635) */
227 reg_vdd_arm: sw3 {
228 regulator-name = "vddarm";
229 regulator-min-microvolt = <674400>;
230 regulator-max-microvolt = <1308000>;
231 lltc,fb-voltage-divider = <127000 200000>;
232 regulator-ramp-delay = <7000>;
233 regulator-boot-on;
234 regulator-always-on;
235 };
236
237 /* VDD_3P3 (1+R1/R2 = 1.281) */
238 reg_3p3v: sw4 {
239 regulator-name = "vdd3p3";
240 regulator-min-microvolt = <1880000>;
241 regulator-max-microvolt = <3647000>;
242 lltc,fb-voltage-divider = <200000 56200>;
243 regulator-ramp-delay = <7000>;
244 regulator-boot-on;
245 regulator-always-on;
246 };
247
248 /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */
249 reg_1p8a: ldo2 {
250 regulator-name = "vdd1p8a";
251 regulator-min-microvolt = <1816125>;
252 regulator-max-microvolt = <1816125>;
253 lltc,fb-voltage-divider = <301000 200000>;
254 regulator-boot-on;
255 regulator-always-on;
256 };
257
258 /* VDD_1P8b: microSD VDD_1P8 */
259 reg_1p8b: ldo3 {
260 regulator-name = "vdd1p8b";
261 regulator-min-microvolt = <1800000>;
262 regulator-max-microvolt = <1800000>;
263 regulator-boot-on;
264 };
265
266 /* VDD_HIGH (1+R1/R2 = 4.17) */
267 reg_3p0v: ldo4 {
268 regulator-name = "vdd3p0";
269 regulator-min-microvolt = <3023250>;
270 regulator-max-microvolt = <3023250>;
271 lltc,fb-voltage-divider = <634000 200000>;
272 regulator-boot-on;
273 regulator-always-on;
274 };
275 };
276 };
277};
278
279&i2c3 {
280 clock-frequency = <100000>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_i2c3>;
283 status = "okay";
284
285 adv7180: camera@20 {
286 compatible = "adi,adv7180";
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_adv7180>;
289 reg = <0x20>;
290 powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
291 interrupt-parent = <&gpio5>;
292 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
293
294 port {
295 adv7180_to_ipu1_csi0_mux: endpoint {
296 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
297 bus-width = <8>;
298 };
299 };
300 };
301};
302
303&ipu1_csi0_from_ipu1_csi0_mux {
304 bus-width = <8>;
305};
306
307&ipu1_csi0_mux_from_parallel_sensor {
308 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
309 bus-width = <8>;
310};
311
312&ipu1_csi0 {
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_ipu1_csi0>;
315};
316
317&pcie {
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_pcie>;
320 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
321 status = "okay";
322};
323
324&pwm2 {
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
327 status = "disabled";
328};
329
330&pwm3 {
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
333 status = "disabled";
334};
335
336&pwm4 {
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
339 status = "disabled";
340};
341
342&uart2 {
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_uart2>;
345 status = "okay";
346};
347
348&uart3 {
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_uart3>;
351 status = "okay";
352};
353
354&uart4 {
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_uart4>;
357 status = "okay";
358};
359
360&uart5 {
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_uart5>;
363 status = "okay";
364};
365
366&usbh1 {
367 status = "okay";
368};
369
370&usbotg {
371 vbus-supply = <®_usb_otg_vbus>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_usbotg>;
374 disable-over-current;
375 status = "okay";
376};
377
378&usdhc3 {
379 pinctrl-names = "default", "state_100mhz", "state_200mhz";
380 pinctrl-0 = <&pinctrl_usdhc3>;
381 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
382 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
383 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
384 status = "okay";
385};
386
387&wdog1 {
388 pinctrl-names = "default";
389 pinctrl-0 = <&pinctrl_wdog>;
390 fsl,ext-reset-output;
391};
392
393&iomuxc {
394 pinctrl_adv7180: adv7180grp {
395 fsl,pins = <
396 MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
397 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
398 >;
399 };
400
401 pinctrl_gpmi_nand: gpminandgrp {
402 fsl,pins = <
403 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
404 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
405 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
406 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
407 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
408 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
409 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
410 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
411 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
412 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
413 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
414 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
415 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
416 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
417 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
418 >;
419 };
420
421 pinctrl_hdmi: hdmigrp {
422 fsl,pins = <
423 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
424 >;
425 };
426
427 pinctrl_i2c1: i2c1grp {
428 fsl,pins = <
429 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
430 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
431 >;
432 };
433
434 pinctrl_i2c2: i2c2grp {
435 fsl,pins = <
436 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
437 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
438 >;
439 };
440
441 pinctrl_i2c3: i2c3grp {
442 fsl,pins = <
443 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
444 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
445 >;
446 };
447
448 pinctrl_imu: imugrp {
449 fsl,pins = <
450 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
451 >;
452 };
453
454 pinctrl_ipu1_csi0: ipu1csi0grp {
455 fsl,pins = <
456 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
457 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
458 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
459 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
460 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
461 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
462 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
463 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
464 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
465 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
466 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
467 >;
468 };
469
470 pinctrl_gpio_leds: gpioledsgrp {
471 fsl,pins = <
472 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
473 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
474 >;
475 };
476
477 pinctrl_mag: maggrp {
478 fsl,pins = <
479 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
480 >;
481 };
482
483 pinctrl_pcie: pciegrp {
484 fsl,pins = <
485 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
486 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */
487 >;
488 };
489
490 pinctrl_pmic: pmicgrp {
491 fsl,pins = <
492 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
493 >;
494 };
495
496 pinctrl_pps: ppsgrp {
497 fsl,pins = <
498 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
499 >;
500 };
501
502 pinctrl_pwm2: pwm2grp {
503 fsl,pins = <
504 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
505 >;
506 };
507
508 pinctrl_pwm3: pwm3grp {
509 fsl,pins = <
510 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
511 >;
512 };
513
514 pinctrl_pwm4: pwm4grp {
515 fsl,pins = <
516 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
517 >;
518 };
519
520 pinctrl_uart2: uart2grp {
521 fsl,pins = <
522 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
523 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
524 >;
525 };
526
527 pinctrl_uart3: uart3grp {
528 fsl,pins = <
529 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
530 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
531 >;
532 };
533
534 pinctrl_uart4: uart4grp {
535 fsl,pins = <
536 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
537 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
538 >;
539 };
540
541 pinctrl_uart5: uart5grp {
542 fsl,pins = <
543 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
544 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
545 >;
546 };
547
548 pinctrl_usbotg: usbotggrp {
549 fsl,pins = <
550 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
551 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
552 >;
553 };
554
555 pinctrl_usdhc3: usdhc3grp {
556 fsl,pins = <
557 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
558 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
559 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
560 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
561 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
562 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
563 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
564 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
565 >;
566 };
567
568 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
569 fsl,pins = <
570 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
571 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
572 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
573 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
574 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
575 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
576 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
577 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
578 >;
579 };
580
581 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
582 fsl,pins = <
583 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
584 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
585 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
586 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
587 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
588 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
589 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
590 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
591 >;
592 };
593
594 pinctrl_wdog: wdoggrp {
595 fsl,pins = <
596 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
597 >;
598 };
599};