tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
4 *
5 * Copyright (c) 2017 Marek Szyprowski
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
7 * http://www.samsung.com
8 */
9
10#include <dt-bindings/clock/samsung,s2mps11.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/gpio/gpio.h>
13#include "exynos5800.dtsi"
14#include "exynos5422-cpus.dtsi"
15
16/ {
17 memory@40000000 {
18 device_type = "memory";
19 reg = <0x40000000 0x7EA00000>;
20 };
21
22 chosen {
23 stdout-path = "serial2:115200n8";
24 };
25
26 firmware@2073000 {
27 compatible = "samsung,secure-firmware";
28 reg = <0x02073000 0x1000>;
29 };
30
31 fixed-rate-clocks {
32 oscclk {
33 compatible = "samsung,exynos5420-oscclk";
34 clock-frequency = <24000000>;
35 };
36 };
37
38 bus_wcore_opp_table: opp_table2 {
39 compatible = "operating-points-v2";
40
41 /* derived from 532MHz MPLL */
42 opp00 {
43 opp-hz = /bits/ 64 <88700000>;
44 opp-microvolt = <925000 925000 1400000>;
45 };
46 opp01 {
47 opp-hz = /bits/ 64 <133000000>;
48 opp-microvolt = <950000 950000 1400000>;
49 };
50 opp02 {
51 opp-hz = /bits/ 64 <177400000>;
52 opp-microvolt = <950000 950000 1400000>;
53 };
54 opp03 {
55 opp-hz = /bits/ 64 <266000000>;
56 opp-microvolt = <950000 950000 1400000>;
57 };
58 opp04 {
59 opp-hz = /bits/ 64 <532000000>;
60 opp-microvolt = <1000000 1000000 1400000>;
61 };
62 };
63
64 bus_noc_opp_table: opp_table3 {
65 compatible = "operating-points-v2";
66
67 /* derived from 666MHz CPLL */
68 opp00 {
69 opp-hz = /bits/ 64 <66600000>;
70 };
71 opp01 {
72 opp-hz = /bits/ 64 <74000000>;
73 };
74 opp02 {
75 opp-hz = /bits/ 64 <83250000>;
76 };
77 opp03 {
78 opp-hz = /bits/ 64 <111000000>;
79 };
80 };
81
82 bus_fsys_apb_opp_table: opp_table4 {
83 compatible = "operating-points-v2";
84
85 /* derived from 666MHz CPLL */
86 opp00 {
87 opp-hz = /bits/ 64 <111000000>;
88 };
89 opp01 {
90 opp-hz = /bits/ 64 <222000000>;
91 };
92 };
93
94 bus_fsys2_opp_table: opp_table5 {
95 compatible = "operating-points-v2";
96
97 /* derived from 600MHz DPLL */
98 opp00 {
99 opp-hz = /bits/ 64 <75000000>;
100 };
101 opp01 {
102 opp-hz = /bits/ 64 <120000000>;
103 };
104 opp02 {
105 opp-hz = /bits/ 64 <200000000>;
106 };
107 };
108
109 bus_mfc_opp_table: opp_table6 {
110 compatible = "operating-points-v2";
111
112 /* derived from 666MHz CPLL */
113 opp00 {
114 opp-hz = /bits/ 64 <83250000>;
115 };
116 opp01 {
117 opp-hz = /bits/ 64 <111000000>;
118 };
119 opp02 {
120 opp-hz = /bits/ 64 <166500000>;
121 };
122 opp03 {
123 opp-hz = /bits/ 64 <222000000>;
124 };
125 opp04 {
126 opp-hz = /bits/ 64 <333000000>;
127 };
128 };
129
130 bus_gen_opp_table: opp_table7 {
131 compatible = "operating-points-v2";
132
133 /* derived from 532MHz MPLL */
134 opp00 {
135 opp-hz = /bits/ 64 <88700000>;
136 };
137 opp01 {
138 opp-hz = /bits/ 64 <133000000>;
139 };
140 opp02 {
141 opp-hz = /bits/ 64 <178000000>;
142 };
143 opp03 {
144 opp-hz = /bits/ 64 <266000000>;
145 };
146 };
147
148 bus_peri_opp_table: opp_table8 {
149 compatible = "operating-points-v2";
150
151 /* derived from 666MHz CPLL */
152 opp00 {
153 opp-hz = /bits/ 64 <66600000>;
154 };
155 };
156
157 bus_g2d_opp_table: opp_table9 {
158 compatible = "operating-points-v2";
159
160 /* derived from 666MHz CPLL */
161 opp00 {
162 opp-hz = /bits/ 64 <83250000>;
163 };
164 opp01 {
165 opp-hz = /bits/ 64 <111000000>;
166 };
167 opp02 {
168 opp-hz = /bits/ 64 <166500000>;
169 };
170 opp03 {
171 opp-hz = /bits/ 64 <222000000>;
172 };
173 opp04 {
174 opp-hz = /bits/ 64 <333000000>;
175 };
176 };
177
178 bus_g2d_acp_opp_table: opp_table10 {
179 compatible = "operating-points-v2";
180
181 /* derived from 532MHz MPLL */
182 opp00 {
183 opp-hz = /bits/ 64 <66500000>;
184 };
185 opp01 {
186 opp-hz = /bits/ 64 <133000000>;
187 };
188 opp02 {
189 opp-hz = /bits/ 64 <178000000>;
190 };
191 opp03 {
192 opp-hz = /bits/ 64 <266000000>;
193 };
194 };
195
196 bus_jpeg_opp_table: opp_table11 {
197 compatible = "operating-points-v2";
198
199 /* derived from 600MHz DPLL */
200 opp00 {
201 opp-hz = /bits/ 64 <75000000>;
202 };
203 opp01 {
204 opp-hz = /bits/ 64 <150000000>;
205 };
206 opp02 {
207 opp-hz = /bits/ 64 <200000000>;
208 };
209 opp03 {
210 opp-hz = /bits/ 64 <300000000>;
211 };
212 };
213
214 bus_jpeg_apb_opp_table: opp_table12 {
215 compatible = "operating-points-v2";
216
217 /* derived from 666MHz CPLL */
218 opp00 {
219 opp-hz = /bits/ 64 <83250000>;
220 };
221 opp01 {
222 opp-hz = /bits/ 64 <111000000>;
223 };
224 opp02 {
225 opp-hz = /bits/ 64 <133000000>;
226 };
227 opp03 {
228 opp-hz = /bits/ 64 <166500000>;
229 };
230 };
231
232 bus_disp1_fimd_opp_table: opp_table13 {
233 compatible = "operating-points-v2";
234
235 /* derived from 600MHz DPLL */
236 opp00 {
237 opp-hz = /bits/ 64 <120000000>;
238 };
239 opp01 {
240 opp-hz = /bits/ 64 <200000000>;
241 };
242 };
243
244 bus_disp1_opp_table: opp_table14 {
245 compatible = "operating-points-v2";
246
247 /* derived from 600MHz DPLL */
248 opp00 {
249 opp-hz = /bits/ 64 <120000000>;
250 };
251 opp01 {
252 opp-hz = /bits/ 64 <200000000>;
253 };
254 opp02 {
255 opp-hz = /bits/ 64 <300000000>;
256 };
257 };
258
259 bus_gscl_opp_table: opp_table15 {
260 compatible = "operating-points-v2";
261
262 /* derived from 600MHz DPLL */
263 opp00 {
264 opp-hz = /bits/ 64 <150000000>;
265 };
266 opp01 {
267 opp-hz = /bits/ 64 <200000000>;
268 };
269 opp02 {
270 opp-hz = /bits/ 64 <300000000>;
271 };
272 };
273
274 bus_mscl_opp_table: opp_table16 {
275 compatible = "operating-points-v2";
276
277 /* derived from 666MHz CPLL */
278 opp00 {
279 opp-hz = /bits/ 64 <84000000>;
280 };
281 opp01 {
282 opp-hz = /bits/ 64 <167000000>;
283 };
284 opp02 {
285 opp-hz = /bits/ 64 <222000000>;
286 };
287 opp03 {
288 opp-hz = /bits/ 64 <333000000>;
289 };
290 opp04 {
291 opp-hz = /bits/ 64 <666000000>;
292 };
293 };
294
295 dmc_opp_table: opp_table17 {
296 compatible = "operating-points-v2";
297
298 opp00 {
299 opp-hz = /bits/ 64 <165000000>;
300 opp-microvolt = <875000>;
301 };
302 opp01 {
303 opp-hz = /bits/ 64 <206000000>;
304 opp-microvolt = <875000>;
305 };
306 opp02 {
307 opp-hz = /bits/ 64 <275000000>;
308 opp-microvolt = <875000>;
309 };
310 opp03 {
311 opp-hz = /bits/ 64 <413000000>;
312 opp-microvolt = <887500>;
313 };
314 opp04 {
315 opp-hz = /bits/ 64 <543000000>;
316 opp-microvolt = <937500>;
317 };
318 opp05 {
319 opp-hz = /bits/ 64 <633000000>;
320 opp-microvolt = <1012500>;
321 };
322 opp06 {
323 opp-hz = /bits/ 64 <728000000>;
324 opp-microvolt = <1037500>;
325 };
326 opp07 {
327 opp-hz = /bits/ 64 <825000000>;
328 opp-microvolt = <1050000>;
329 };
330 };
331
332 samsung_K3QF2F20DB: lpddr3 {
333 compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
334 density = <16384>;
335 io-width = <32>;
336 #address-cells = <1>;
337 #size-cells = <0>;
338
339 tRFC-min-tck = <17>;
340 tRRD-min-tck = <2>;
341 tRPab-min-tck = <2>;
342 tRPpb-min-tck = <2>;
343 tRCD-min-tck = <3>;
344 tRC-min-tck = <6>;
345 tRAS-min-tck = <5>;
346 tWTR-min-tck = <2>;
347 tWR-min-tck = <7>;
348 tRTP-min-tck = <2>;
349 tW2W-C2C-min-tck = <0>;
350 tR2R-C2C-min-tck = <0>;
351 tWL-min-tck = <8>;
352 tDQSCK-min-tck = <5>;
353 tRL-min-tck = <14>;
354 tFAW-min-tck = <5>;
355 tXSR-min-tck = <12>;
356 tXP-min-tck = <2>;
357 tCKE-min-tck = <2>;
358 tCKESR-min-tck = <2>;
359 tMRD-min-tck = <5>;
360
361 timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
362 compatible = "jedec,lpddr3-timings";
363 /* workaround: 'reg' shows max-freq */
364 reg = <800000000>;
365 min-freq = <100000000>;
366 tRFC = <65000>;
367 tRRD = <6000>;
368 tRPab = <12000>;
369 tRPpb = <12000>;
370 tRCD = <10000>;
371 tRC = <33750>;
372 tRAS = <23000>;
373 tWTR = <3750>;
374 tWR = <7500>;
375 tRTP = <3750>;
376 tW2W-C2C = <0>;
377 tR2R-C2C = <0>;
378 tFAW = <25000>;
379 tXSR = <70000>;
380 tXP = <3750>;
381 tCKE = <3750>;
382 tCKESR = <3750>;
383 tMRD = <7000>;
384 };
385 };
386};
387
388&adc {
389 vdd-supply = <&ldo4_reg>;
390 status = "okay";
391};
392
393&bus_wcore {
394 operating-points-v2 = <&bus_wcore_opp_table>;
395 devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
396 <&nocp_mem1_0>, <&nocp_mem1_1>;
397 vdd-supply = <&buck3_reg>;
398 exynos,saturation-ratio = <100>;
399 status = "okay";
400};
401
402&bus_noc {
403 operating-points-v2 = <&bus_noc_opp_table>;
404 devfreq = <&bus_wcore>;
405 status = "okay";
406};
407
408&bus_fsys_apb {
409 operating-points-v2 = <&bus_fsys_apb_opp_table>;
410 devfreq = <&bus_wcore>;
411 status = "okay";
412};
413
414&bus_fsys {
415 operating-points-v2 = <&bus_fsys2_opp_table>;
416 devfreq = <&bus_wcore>;
417 status = "okay";
418};
419
420&bus_fsys2 {
421 operating-points-v2 = <&bus_fsys2_opp_table>;
422 devfreq = <&bus_wcore>;
423 status = "okay";
424};
425
426&bus_mfc {
427 operating-points-v2 = <&bus_mfc_opp_table>;
428 devfreq = <&bus_wcore>;
429 status = "okay";
430};
431
432&bus_gen {
433 operating-points-v2 = <&bus_gen_opp_table>;
434 devfreq = <&bus_wcore>;
435 status = "okay";
436};
437
438&bus_peri {
439 operating-points-v2 = <&bus_peri_opp_table>;
440 devfreq = <&bus_wcore>;
441 status = "okay";
442};
443
444&bus_g2d {
445 operating-points-v2 = <&bus_g2d_opp_table>;
446 devfreq = <&bus_wcore>;
447 status = "okay";
448};
449
450&bus_g2d_acp {
451 operating-points-v2 = <&bus_g2d_acp_opp_table>;
452 devfreq = <&bus_wcore>;
453 status = "okay";
454};
455
456&bus_jpeg {
457 operating-points-v2 = <&bus_jpeg_opp_table>;
458 devfreq = <&bus_wcore>;
459 status = "okay";
460};
461
462&bus_jpeg_apb {
463 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
464 devfreq = <&bus_wcore>;
465 status = "okay";
466};
467
468&bus_disp1_fimd {
469 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
470 devfreq = <&bus_wcore>;
471 status = "okay";
472};
473
474&bus_disp1 {
475 operating-points-v2 = <&bus_disp1_opp_table>;
476 devfreq = <&bus_wcore>;
477 status = "okay";
478};
479
480&bus_gscl_scaler {
481 operating-points-v2 = <&bus_gscl_opp_table>;
482 devfreq = <&bus_wcore>;
483 status = "okay";
484};
485
486&bus_mscl {
487 operating-points-v2 = <&bus_mscl_opp_table>;
488 devfreq = <&bus_wcore>;
489 status = "okay";
490};
491
492&cpu0 {
493 cpu-supply = <&buck6_reg>;
494};
495
496&cpu4 {
497 cpu-supply = <&buck2_reg>;
498};
499
500&dmc {
501 devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
502 <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
503 device-handle = <&samsung_K3QF2F20DB>;
504 operating-points-v2 = <&dmc_opp_table>;
505 vdd-supply = <&buck1_reg>;
506 status = "okay";
507};
508
509&hsi2c_4 {
510 status = "okay";
511
512 s2mps11_pmic@66 {
513 compatible = "samsung,s2mps11-pmic";
514 reg = <0x66>;
515 samsung,s2mps11-acokb-ground;
516
517 interrupt-parent = <&gpx0>;
518 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&s2mps11_irq>;
521
522 s2mps11_osc: clocks {
523 compatible = "samsung,s2mps11-clk";
524 #clock-cells = <1>;
525 clock-output-names = "s2mps11_ap",
526 "s2mps11_cp", "s2mps11_bt";
527 };
528
529 regulators {
530 ldo1_reg: LDO1 {
531 regulator-name = "vdd_ldo1";
532 regulator-min-microvolt = <1000000>;
533 regulator-max-microvolt = <1000000>;
534 regulator-always-on;
535 };
536
537 ldo2_reg: LDO2 {
538 regulator-name = "vdd_ldo2";
539 regulator-min-microvolt = <1800000>;
540 regulator-max-microvolt = <1800000>;
541 regulator-always-on;
542 };
543
544 ldo3_reg: LDO3 {
545 regulator-name = "vddq_mmc0";
546 regulator-min-microvolt = <1800000>;
547 regulator-max-microvolt = <1800000>;
548 };
549
550 ldo4_reg: LDO4 {
551 regulator-name = "vdd_adc";
552 regulator-min-microvolt = <1800000>;
553 regulator-max-microvolt = <1800000>;
554
555 regulator-state-mem {
556 regulator-off-in-suspend;
557 };
558 };
559
560 ldo5_reg: LDO5 {
561 regulator-name = "vdd_ldo5";
562 regulator-min-microvolt = <1800000>;
563 regulator-max-microvolt = <1800000>;
564 regulator-always-on;
565
566 regulator-state-mem {
567 regulator-off-in-suspend;
568 };
569 };
570
571 ldo6_reg: LDO6 {
572 regulator-name = "vdd_ldo6";
573 regulator-min-microvolt = <1000000>;
574 regulator-max-microvolt = <1000000>;
575 regulator-always-on;
576
577 regulator-state-mem {
578 regulator-off-in-suspend;
579 };
580 };
581
582 ldo7_reg: LDO7 {
583 regulator-name = "vdd_ldo7";
584 regulator-min-microvolt = <1800000>;
585 regulator-max-microvolt = <1800000>;
586 regulator-always-on;
587
588 regulator-state-mem {
589 regulator-off-in-suspend;
590 };
591 };
592
593 ldo8_reg: LDO8 {
594 regulator-name = "vdd_ldo8";
595 regulator-min-microvolt = <1800000>;
596 regulator-max-microvolt = <1800000>;
597 regulator-always-on;
598
599 regulator-state-mem {
600 regulator-off-in-suspend;
601 };
602 };
603
604 ldo9_reg: LDO9 {
605 regulator-name = "vdd_ldo9";
606 regulator-min-microvolt = <3000000>;
607 regulator-max-microvolt = <3000000>;
608 regulator-always-on;
609
610 regulator-state-mem {
611 regulator-off-in-suspend;
612 };
613 };
614
615 ldo10_reg: LDO10 {
616 regulator-name = "vdd_ldo10";
617 regulator-min-microvolt = <1800000>;
618 regulator-max-microvolt = <1800000>;
619 regulator-always-on;
620
621 regulator-state-mem {
622 regulator-off-in-suspend;
623 };
624 };
625
626 ldo11_reg: LDO11 {
627 regulator-name = "vdd_ldo11";
628 regulator-min-microvolt = <1000000>;
629 regulator-max-microvolt = <1000000>;
630 regulator-always-on;
631
632 regulator-state-mem {
633 regulator-off-in-suspend;
634 };
635 };
636
637 ldo12_reg: LDO12 {
638 /* Unused */
639 regulator-name = "vdd_ldo12";
640 regulator-min-microvolt = <800000>;
641 regulator-max-microvolt = <2375000>;
642 };
643
644 ldo13_reg: LDO13 {
645 regulator-name = "vddq_mmc2";
646 regulator-min-microvolt = <1800000>;
647 regulator-max-microvolt = <2800000>;
648
649 regulator-state-mem {
650 regulator-off-in-suspend;
651 };
652 };
653
654 ldo14_reg: LDO14 {
655 /* Unused */
656 regulator-name = "vdd_ldo14";
657 regulator-min-microvolt = <800000>;
658 regulator-max-microvolt = <3950000>;
659 };
660
661 ldo15_reg: LDO15 {
662 regulator-name = "vdd_ldo15";
663 regulator-min-microvolt = <3300000>;
664 regulator-max-microvolt = <3300000>;
665 regulator-always-on;
666
667 regulator-state-mem {
668 regulator-off-in-suspend;
669 };
670 };
671
672 ldo16_reg: LDO16 {
673 /* Unused */
674 regulator-name = "vdd_ldo16";
675 regulator-min-microvolt = <800000>;
676 regulator-max-microvolt = <3950000>;
677 };
678
679 ldo17_reg: LDO17 {
680 regulator-name = "vdd_ldo17";
681 regulator-min-microvolt = <3300000>;
682 regulator-max-microvolt = <3300000>;
683 regulator-always-on;
684
685 regulator-state-mem {
686 regulator-off-in-suspend;
687 };
688 };
689
690 ldo18_reg: LDO18 {
691 regulator-name = "vdd_emmc_1V8";
692 regulator-min-microvolt = <1800000>;
693 regulator-max-microvolt = <1800000>;
694
695 regulator-state-mem {
696 regulator-off-in-suspend;
697 };
698 };
699
700 ldo19_reg: LDO19 {
701 regulator-name = "vdd_sd";
702 regulator-min-microvolt = <2800000>;
703 regulator-max-microvolt = <2800000>;
704
705 regulator-state-mem {
706 regulator-off-in-suspend;
707 };
708 };
709
710 ldo20_reg: LDO20 {
711 /* Unused */
712 regulator-name = "vdd_ldo20";
713 regulator-min-microvolt = <800000>;
714 regulator-max-microvolt = <3950000>;
715 };
716
717 ldo21_reg: LDO21 {
718 /* Unused */
719 regulator-name = "vdd_ldo21";
720 regulator-min-microvolt = <800000>;
721 regulator-max-microvolt = <3950000>;
722 };
723
724 ldo22_reg: LDO22 {
725 /* Unused */
726 regulator-name = "vdd_ldo22";
727 regulator-min-microvolt = <800000>;
728 regulator-max-microvolt = <2375000>;
729 };
730
731 ldo23_reg: LDO23 {
732 regulator-name = "vdd_mifs";
733 regulator-min-microvolt = <1100000>;
734 regulator-max-microvolt = <1100000>;
735 regulator-always-on;
736
737 regulator-state-mem {
738 regulator-off-in-suspend;
739 };
740 };
741
742 ldo24_reg: LDO24 {
743 /* Unused */
744 regulator-name = "vdd_ldo24";
745 regulator-min-microvolt = <800000>;
746 regulator-max-microvolt = <3950000>;
747 };
748
749 ldo25_reg: LDO25 {
750 /* Unused */
751 regulator-name = "vdd_ldo25";
752 regulator-min-microvolt = <800000>;
753 regulator-max-microvolt = <3950000>;
754 };
755
756 ldo26_reg: LDO26 {
757 /* Used on XU3, XU3-Lite and XU4 */
758 regulator-name = "vdd_ldo26";
759 regulator-min-microvolt = <800000>;
760 regulator-max-microvolt = <3950000>;
761
762 regulator-state-mem {
763 regulator-off-in-suspend;
764 };
765 };
766
767 ldo27_reg: LDO27 {
768 regulator-name = "vdd_g3ds";
769 regulator-min-microvolt = <1000000>;
770 regulator-max-microvolt = <1000000>;
771 regulator-always-on;
772
773 regulator-state-mem {
774 regulator-off-in-suspend;
775 };
776 };
777
778 ldo28_reg: LDO28 {
779 /* Used on XU3 */
780 regulator-name = "vdd_ldo28";
781 regulator-min-microvolt = <800000>;
782 regulator-max-microvolt = <3950000>;
783
784 regulator-state-mem {
785 regulator-off-in-suspend;
786 };
787 };
788
789 ldo29_reg: LDO29 {
790 /* Unused */
791 regulator-name = "vdd_ldo29";
792 regulator-min-microvolt = <800000>;
793 regulator-max-microvolt = <3950000>;
794 };
795
796 ldo30_reg: LDO30 {
797 /* Unused */
798 regulator-name = "vdd_ldo30";
799 regulator-min-microvolt = <800000>;
800 regulator-max-microvolt = <3950000>;
801 };
802
803 ldo31_reg: LDO31 {
804 /* Unused */
805 regulator-name = "vdd_ldo31";
806 regulator-min-microvolt = <800000>;
807 regulator-max-microvolt = <3950000>;
808 };
809
810 ldo32_reg: LDO32 {
811 /* Unused */
812 regulator-name = "vdd_ldo32";
813 regulator-min-microvolt = <800000>;
814 regulator-max-microvolt = <3950000>;
815 };
816
817 ldo33_reg: LDO33 {
818 /* Unused */
819 regulator-name = "vdd_ldo33";
820 regulator-min-microvolt = <800000>;
821 regulator-max-microvolt = <3950000>;
822 };
823
824 ldo34_reg: LDO34 {
825 /* Unused */
826 regulator-name = "vdd_ldo34";
827 regulator-min-microvolt = <800000>;
828 regulator-max-microvolt = <3950000>;
829 };
830
831 ldo35_reg: LDO35 {
832 /* Unused */
833 regulator-name = "vdd_ldo35";
834 regulator-min-microvolt = <800000>;
835 regulator-max-microvolt = <2375000>;
836 };
837
838 ldo36_reg: LDO36 {
839 /* Unused */
840 regulator-name = "vdd_ldo36";
841 regulator-min-microvolt = <800000>;
842 regulator-max-microvolt = <3950000>;
843 };
844
845 ldo37_reg: LDO37 {
846 /* Unused */
847 regulator-name = "vdd_ldo37";
848 regulator-min-microvolt = <800000>;
849 regulator-max-microvolt = <3950000>;
850 };
851
852 ldo38_reg: LDO38 {
853 /* Unused */
854 regulator-name = "vdd_ldo38";
855 regulator-min-microvolt = <800000>;
856 regulator-max-microvolt = <3950000>;
857 };
858
859 buck1_reg: BUCK1 {
860 regulator-name = "vdd_mif";
861 regulator-min-microvolt = <800000>;
862 regulator-max-microvolt = <1300000>;
863 regulator-always-on;
864 regulator-boot-on;
865
866 regulator-state-mem {
867 regulator-off-in-suspend;
868 };
869 };
870
871 buck2_reg: BUCK2 {
872 regulator-name = "vdd_arm";
873 regulator-min-microvolt = <800000>;
874 regulator-max-microvolt = <1500000>;
875 regulator-always-on;
876 regulator-boot-on;
877 regulator-coupled-with = <&buck3_reg>;
878 regulator-coupled-max-spread = <300000>;
879
880 regulator-state-mem {
881 regulator-off-in-suspend;
882 };
883 };
884
885 buck3_reg: BUCK3 {
886 regulator-name = "vdd_int";
887 regulator-min-microvolt = <800000>;
888 regulator-max-microvolt = <1400000>;
889 regulator-always-on;
890 regulator-boot-on;
891 regulator-coupled-with = <&buck2_reg>;
892 regulator-coupled-max-spread = <300000>;
893
894 regulator-state-mem {
895 regulator-off-in-suspend;
896 };
897 };
898
899 buck4_reg: BUCK4 {
900 regulator-name = "vdd_g3d";
901 regulator-min-microvolt = <800000>;
902 regulator-max-microvolt = <1400000>;
903 regulator-boot-on;
904 regulator-always-on;
905
906 regulator-state-mem {
907 regulator-off-in-suspend;
908 };
909 };
910
911 buck5_reg: BUCK5 {
912 regulator-name = "vdd_mem";
913 regulator-min-microvolt = <800000>;
914 regulator-max-microvolt = <1400000>;
915 regulator-always-on;
916 regulator-boot-on;
917 };
918
919 buck6_reg: BUCK6 {
920 regulator-name = "vdd_kfc";
921 regulator-min-microvolt = <800000>;
922 regulator-max-microvolt = <1500000>;
923 regulator-always-on;
924 regulator-boot-on;
925
926 regulator-state-mem {
927 regulator-off-in-suspend;
928 };
929 };
930
931 buck7_reg: BUCK7 {
932 regulator-name = "vdd_1.35v_ldo";
933 regulator-min-microvolt = <1200000>;
934 regulator-max-microvolt = <1500000>;
935 regulator-always-on;
936 regulator-boot-on;
937 };
938
939 buck8_reg: BUCK8 {
940 regulator-name = "vdd_2.0v_ldo";
941 regulator-min-microvolt = <1800000>;
942 regulator-max-microvolt = <2100000>;
943 regulator-always-on;
944 regulator-boot-on;
945 };
946
947 buck9_reg: BUCK9 {
948 regulator-name = "vdd_2.8v_ldo";
949 regulator-min-microvolt = <3000000>;
950 regulator-max-microvolt = <3750000>;
951 regulator-always-on;
952 regulator-boot-on;
953
954 regulator-state-mem {
955 regulator-off-in-suspend;
956 };
957 };
958
959 buck10_reg: BUCK10 {
960 regulator-name = "vdd_vmem";
961 regulator-min-microvolt = <2850000>;
962 regulator-max-microvolt = <2850000>;
963
964 regulator-state-mem {
965 regulator-off-in-suspend;
966 };
967 };
968 };
969 };
970};
971
972&mmc_2 {
973 status = "okay";
974 card-detect-delay = <200>;
975 samsung,dw-mshc-ciu-div = <3>;
976 samsung,dw-mshc-sdr-timing = <0 4>;
977 samsung,dw-mshc-ddr-timing = <0 2>;
978 pinctrl-names = "default";
979 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
980 bus-width = <4>;
981 cap-sd-highspeed;
982 max-frequency = <200000000>;
983 vmmc-supply = <&ldo19_reg>;
984 vqmmc-supply = <&ldo13_reg>;
985 sd-uhs-sdr50;
986 sd-uhs-sdr104;
987 sd-uhs-ddr50;
988};
989
990&nocp_mem0_0 {
991 status = "okay";
992};
993
994&nocp_mem0_1 {
995 status = "okay";
996};
997
998&nocp_mem1_0 {
999 status = "okay";
1000};
1001
1002&nocp_mem1_1 {
1003 status = "okay";
1004};
1005
1006&pinctrl_0 {
1007 s2mps11_irq: s2mps11-irq {
1008 samsung,pins = "gpx0-4";
1009 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
1010 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1011 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1012 };
1013};
1014
1015&ppmu_dmc0_0 {
1016 status = "okay";
1017};
1018
1019&ppmu_dmc0_1 {
1020 status = "okay";
1021};
1022
1023&ppmu_dmc1_0 {
1024 status = "okay";
1025};
1026
1027&ppmu_dmc1_1 {
1028 status = "okay";
1029};
1030
1031&tmu_cpu0 {
1032 vtmu-supply = <&ldo7_reg>;
1033};
1034
1035&tmu_cpu1 {
1036 vtmu-supply = <&ldo7_reg>;
1037};
1038
1039&tmu_cpu2 {
1040 vtmu-supply = <&ldo7_reg>;
1041};
1042
1043&tmu_cpu3 {
1044 vtmu-supply = <&ldo7_reg>;
1045};
1046
1047&tmu_gpu {
1048 vtmu-supply = <&ldo7_reg>;
1049};
1050
1051&gpu {
1052 mali-supply = <&buck4_reg>;
1053 status = "okay";
1054};
1055
1056&rtc {
1057 status = "okay";
1058 clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
1059 clock-names = "rtc", "rtc_src";
1060};
1061
1062&usbdrd_dwc3_0 {
1063 dr_mode = "host";
1064};
1065
1066/* usbdrd_dwc3_1 mode customized in each board */
1067
1068&usbdrd3_0 {
1069 vdd33-supply = <&ldo9_reg>;
1070 vdd10-supply = <&ldo11_reg>;
1071};
1072
1073&usbdrd3_1 {
1074 vdd33-supply = <&ldo9_reg>;
1075 vdd10-supply = <&ldo11_reg>;
1076};