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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * Copyright (c) 2015, Google Inc.
5 */
6
7#ifndef __PHY_TEGRA_XUSB_H
8#define __PHY_TEGRA_XUSB_H
9
10#include <linux/io.h>
11#include <linux/mutex.h>
12#include <linux/workqueue.h>
13
14#include <linux/usb/otg.h>
15#include <linux/usb/role.h>
16
17/* legacy entry points for backwards-compatibility */
18int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev);
19int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev);
20
21struct phy;
22struct phy_provider;
23struct platform_device;
24struct regulator;
25
26/*
27 * lanes
28 */
29struct tegra_xusb_lane_soc {
30 const char *name;
31
32 unsigned int offset;
33 unsigned int shift;
34 unsigned int mask;
35
36 const char * const *funcs;
37 unsigned int num_funcs;
38};
39
40struct tegra_xusb_lane {
41 const struct tegra_xusb_lane_soc *soc;
42 struct tegra_xusb_pad *pad;
43 struct device_node *np;
44 struct list_head list;
45 unsigned int function;
46 unsigned int index;
47};
48
49int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
50 struct device_node *np);
51
52struct tegra_xusb_usb3_lane {
53 struct tegra_xusb_lane base;
54};
55
56static inline struct tegra_xusb_usb3_lane *
57to_usb3_lane(struct tegra_xusb_lane *lane)
58{
59 return container_of(lane, struct tegra_xusb_usb3_lane, base);
60}
61
62struct tegra_xusb_usb2_lane {
63 struct tegra_xusb_lane base;
64
65 u32 hs_curr_level_offset;
66 bool powered_on;
67};
68
69static inline struct tegra_xusb_usb2_lane *
70to_usb2_lane(struct tegra_xusb_lane *lane)
71{
72 return container_of(lane, struct tegra_xusb_usb2_lane, base);
73}
74
75struct tegra_xusb_ulpi_lane {
76 struct tegra_xusb_lane base;
77};
78
79static inline struct tegra_xusb_ulpi_lane *
80to_ulpi_lane(struct tegra_xusb_lane *lane)
81{
82 return container_of(lane, struct tegra_xusb_ulpi_lane, base);
83}
84
85struct tegra_xusb_hsic_lane {
86 struct tegra_xusb_lane base;
87
88 u32 strobe_trim;
89 u32 rx_strobe_trim;
90 u32 rx_data_trim;
91 u32 tx_rtune_n;
92 u32 tx_rtune_p;
93 u32 tx_rslew_n;
94 u32 tx_rslew_p;
95 bool auto_term;
96};
97
98static inline struct tegra_xusb_hsic_lane *
99to_hsic_lane(struct tegra_xusb_lane *lane)
100{
101 return container_of(lane, struct tegra_xusb_hsic_lane, base);
102}
103
104struct tegra_xusb_pcie_lane {
105 struct tegra_xusb_lane base;
106};
107
108static inline struct tegra_xusb_pcie_lane *
109to_pcie_lane(struct tegra_xusb_lane *lane)
110{
111 return container_of(lane, struct tegra_xusb_pcie_lane, base);
112}
113
114struct tegra_xusb_sata_lane {
115 struct tegra_xusb_lane base;
116};
117
118static inline struct tegra_xusb_sata_lane *
119to_sata_lane(struct tegra_xusb_lane *lane)
120{
121 return container_of(lane, struct tegra_xusb_sata_lane, base);
122}
123
124struct tegra_xusb_lane_ops {
125 struct tegra_xusb_lane *(*probe)(struct tegra_xusb_pad *pad,
126 struct device_node *np,
127 unsigned int index);
128 void (*remove)(struct tegra_xusb_lane *lane);
129};
130
131/*
132 * pads
133 */
134struct tegra_xusb_pad_soc;
135struct tegra_xusb_padctl;
136
137struct tegra_xusb_pad_ops {
138 struct tegra_xusb_pad *(*probe)(struct tegra_xusb_padctl *padctl,
139 const struct tegra_xusb_pad_soc *soc,
140 struct device_node *np);
141 void (*remove)(struct tegra_xusb_pad *pad);
142};
143
144struct tegra_xusb_pad_soc {
145 const char *name;
146
147 const struct tegra_xusb_lane_soc *lanes;
148 unsigned int num_lanes;
149
150 const struct tegra_xusb_pad_ops *ops;
151};
152
153struct tegra_xusb_pad {
154 const struct tegra_xusb_pad_soc *soc;
155 struct tegra_xusb_padctl *padctl;
156 struct phy_provider *provider;
157 struct phy **lanes;
158 struct device dev;
159
160 const struct tegra_xusb_lane_ops *ops;
161
162 struct list_head list;
163};
164
165static inline struct tegra_xusb_pad *to_tegra_xusb_pad(struct device *dev)
166{
167 return container_of(dev, struct tegra_xusb_pad, dev);
168}
169
170int tegra_xusb_pad_init(struct tegra_xusb_pad *pad,
171 struct tegra_xusb_padctl *padctl,
172 struct device_node *np);
173int tegra_xusb_pad_register(struct tegra_xusb_pad *pad,
174 const struct phy_ops *ops);
175void tegra_xusb_pad_unregister(struct tegra_xusb_pad *pad);
176
177struct tegra_xusb_usb3_pad {
178 struct tegra_xusb_pad base;
179
180 unsigned int enable;
181 struct mutex lock;
182};
183
184static inline struct tegra_xusb_usb3_pad *
185to_usb3_pad(struct tegra_xusb_pad *pad)
186{
187 return container_of(pad, struct tegra_xusb_usb3_pad, base);
188}
189
190struct tegra_xusb_usb2_pad {
191 struct tegra_xusb_pad base;
192
193 struct clk *clk;
194 unsigned int enable;
195 struct mutex lock;
196};
197
198static inline struct tegra_xusb_usb2_pad *
199to_usb2_pad(struct tegra_xusb_pad *pad)
200{
201 return container_of(pad, struct tegra_xusb_usb2_pad, base);
202}
203
204struct tegra_xusb_ulpi_pad {
205 struct tegra_xusb_pad base;
206};
207
208static inline struct tegra_xusb_ulpi_pad *
209to_ulpi_pad(struct tegra_xusb_pad *pad)
210{
211 return container_of(pad, struct tegra_xusb_ulpi_pad, base);
212}
213
214struct tegra_xusb_hsic_pad {
215 struct tegra_xusb_pad base;
216
217 struct regulator *supply;
218 struct clk *clk;
219};
220
221static inline struct tegra_xusb_hsic_pad *
222to_hsic_pad(struct tegra_xusb_pad *pad)
223{
224 return container_of(pad, struct tegra_xusb_hsic_pad, base);
225}
226
227struct tegra_xusb_pcie_pad {
228 struct tegra_xusb_pad base;
229
230 struct reset_control *rst;
231 struct clk *pll;
232
233 unsigned int enable;
234};
235
236static inline struct tegra_xusb_pcie_pad *
237to_pcie_pad(struct tegra_xusb_pad *pad)
238{
239 return container_of(pad, struct tegra_xusb_pcie_pad, base);
240}
241
242struct tegra_xusb_sata_pad {
243 struct tegra_xusb_pad base;
244
245 struct reset_control *rst;
246 struct clk *pll;
247
248 unsigned int enable;
249};
250
251static inline struct tegra_xusb_sata_pad *
252to_sata_pad(struct tegra_xusb_pad *pad)
253{
254 return container_of(pad, struct tegra_xusb_sata_pad, base);
255}
256
257/*
258 * ports
259 */
260struct tegra_xusb_port_ops;
261
262struct tegra_xusb_port {
263 struct tegra_xusb_padctl *padctl;
264 struct tegra_xusb_lane *lane;
265 unsigned int index;
266
267 struct list_head list;
268 struct device dev;
269
270 struct usb_role_switch *usb_role_sw;
271 struct work_struct usb_phy_work;
272 struct usb_phy usb_phy;
273
274 const struct tegra_xusb_port_ops *ops;
275};
276
277static inline struct tegra_xusb_port *to_tegra_xusb_port(struct device *dev)
278{
279 return container_of(dev, struct tegra_xusb_port, dev);
280}
281
282struct tegra_xusb_lane_map {
283 unsigned int port;
284 const char *type;
285 unsigned int index;
286 const char *func;
287};
288
289struct tegra_xusb_lane *
290tegra_xusb_port_find_lane(struct tegra_xusb_port *port,
291 const struct tegra_xusb_lane_map *map,
292 const char *function);
293
294struct tegra_xusb_port *
295tegra_xusb_find_port(struct tegra_xusb_padctl *padctl, const char *type,
296 unsigned int index);
297
298struct tegra_xusb_usb2_port {
299 struct tegra_xusb_port base;
300
301 struct regulator *supply;
302 enum usb_dr_mode mode;
303 bool internal;
304 int usb3_port_fake;
305};
306
307static inline struct tegra_xusb_usb2_port *
308to_usb2_port(struct tegra_xusb_port *port)
309{
310 return container_of(port, struct tegra_xusb_usb2_port, base);
311}
312
313struct tegra_xusb_usb2_port *
314tegra_xusb_find_usb2_port(struct tegra_xusb_padctl *padctl,
315 unsigned int index);
316void tegra_xusb_usb2_port_release(struct tegra_xusb_port *port);
317void tegra_xusb_usb2_port_remove(struct tegra_xusb_port *port);
318
319struct tegra_xusb_ulpi_port {
320 struct tegra_xusb_port base;
321
322 struct regulator *supply;
323 bool internal;
324};
325
326static inline struct tegra_xusb_ulpi_port *
327to_ulpi_port(struct tegra_xusb_port *port)
328{
329 return container_of(port, struct tegra_xusb_ulpi_port, base);
330}
331
332void tegra_xusb_ulpi_port_release(struct tegra_xusb_port *port);
333
334struct tegra_xusb_hsic_port {
335 struct tegra_xusb_port base;
336};
337
338static inline struct tegra_xusb_hsic_port *
339to_hsic_port(struct tegra_xusb_port *port)
340{
341 return container_of(port, struct tegra_xusb_hsic_port, base);
342}
343
344void tegra_xusb_hsic_port_release(struct tegra_xusb_port *port);
345
346struct tegra_xusb_usb3_port {
347 struct tegra_xusb_port base;
348 struct regulator *supply;
349 bool context_saved;
350 unsigned int port;
351 bool internal;
352 bool disable_gen2;
353
354 u32 tap1;
355 u32 amp;
356 u32 ctle_z;
357 u32 ctle_g;
358};
359
360static inline struct tegra_xusb_usb3_port *
361to_usb3_port(struct tegra_xusb_port *port)
362{
363 return container_of(port, struct tegra_xusb_usb3_port, base);
364}
365
366struct tegra_xusb_usb3_port *
367tegra_xusb_find_usb3_port(struct tegra_xusb_padctl *padctl,
368 unsigned int index);
369void tegra_xusb_usb3_port_release(struct tegra_xusb_port *port);
370void tegra_xusb_usb3_port_remove(struct tegra_xusb_port *port);
371
372struct tegra_xusb_port_ops {
373 void (*release)(struct tegra_xusb_port *port);
374 void (*remove)(struct tegra_xusb_port *port);
375 int (*enable)(struct tegra_xusb_port *port);
376 void (*disable)(struct tegra_xusb_port *port);
377 struct tegra_xusb_lane *(*map)(struct tegra_xusb_port *port);
378};
379
380/*
381 * pad controller
382 */
383struct tegra_xusb_padctl_soc;
384
385struct tegra_xusb_padctl_ops {
386 struct tegra_xusb_padctl *
387 (*probe)(struct device *dev,
388 const struct tegra_xusb_padctl_soc *soc);
389 void (*remove)(struct tegra_xusb_padctl *padctl);
390
391 int (*usb3_save_context)(struct tegra_xusb_padctl *padctl,
392 unsigned int index);
393 int (*hsic_set_idle)(struct tegra_xusb_padctl *padctl,
394 unsigned int index, bool idle);
395 int (*usb3_set_lfps_detect)(struct tegra_xusb_padctl *padctl,
396 unsigned int index, bool enable);
397 int (*vbus_override)(struct tegra_xusb_padctl *padctl, bool set);
398 int (*utmi_port_reset)(struct phy *phy);
399};
400
401struct tegra_xusb_padctl_soc {
402 const struct tegra_xusb_pad_soc * const *pads;
403 unsigned int num_pads;
404
405 struct {
406 struct {
407 const struct tegra_xusb_port_ops *ops;
408 unsigned int count;
409 } usb2, ulpi, hsic, usb3;
410 } ports;
411
412 const struct tegra_xusb_padctl_ops *ops;
413
414 const char * const *supply_names;
415 unsigned int num_supplies;
416 bool supports_gen2;
417 bool need_fake_usb3_port;
418};
419
420struct tegra_xusb_padctl {
421 struct device *dev;
422 void __iomem *regs;
423 struct mutex lock;
424 struct reset_control *rst;
425
426 const struct tegra_xusb_padctl_soc *soc;
427
428 struct tegra_xusb_pad *pcie;
429 struct tegra_xusb_pad *sata;
430 struct tegra_xusb_pad *ulpi;
431 struct tegra_xusb_pad *usb2;
432 struct tegra_xusb_pad *hsic;
433
434 struct list_head ports;
435 struct list_head lanes;
436 struct list_head pads;
437
438 unsigned int enable;
439
440 struct clk *clk;
441
442 struct regulator_bulk_data *supplies;
443};
444
445static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
446 unsigned long offset)
447{
448 dev_dbg(padctl->dev, "%08lx < %08x\n", offset, value);
449 writel(value, padctl->regs + offset);
450}
451
452static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
453 unsigned long offset)
454{
455 u32 value = readl(padctl->regs + offset);
456 dev_dbg(padctl->dev, "%08lx > %08x\n", offset, value);
457 return value;
458}
459
460struct tegra_xusb_lane *tegra_xusb_find_lane(struct tegra_xusb_padctl *padctl,
461 const char *name,
462 unsigned int index);
463
464#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
465extern const struct tegra_xusb_padctl_soc tegra124_xusb_padctl_soc;
466#endif
467#if defined(CONFIG_ARCH_TEGRA_210_SOC)
468extern const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc;
469#endif
470#if defined(CONFIG_ARCH_TEGRA_186_SOC)
471extern const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc;
472#endif
473#if defined(CONFIG_ARCH_TEGRA_194_SOC)
474extern const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc;
475#endif
476
477#endif /* __PHY_TEGRA_XUSB_H */