tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019-2020 Icenowy Zheng <icenowy@aosc.io>
4 */
5
6#include <linux/gpio/consumer.h>
7#include <linux/delay.h>
8#include <linux/mod_devicetable.h>
9#include <linux/module.h>
10#include <linux/of_device.h>
11#include <linux/regulator/consumer.h>
12
13#include <drm/drm_mipi_dsi.h>
14#include <drm/drm_modes.h>
15#include <drm/drm_panel.h>
16#include <drm/drm_print.h>
17
18#define K101_IM2BA02_INIT_CMD_LEN 2
19
20static const char * const regulator_names[] = {
21 "dvdd",
22 "avdd",
23 "cvdd"
24};
25
26struct k101_im2ba02 {
27 struct drm_panel panel;
28 struct mipi_dsi_device *dsi;
29
30 struct regulator_bulk_data supplies[ARRAY_SIZE(regulator_names)];
31 struct gpio_desc *reset;
32};
33
34static inline struct k101_im2ba02 *panel_to_k101_im2ba02(struct drm_panel *panel)
35{
36 return container_of(panel, struct k101_im2ba02, panel);
37}
38
39struct k101_im2ba02_init_cmd {
40 u8 data[K101_IM2BA02_INIT_CMD_LEN];
41};
42
43static const struct k101_im2ba02_init_cmd k101_im2ba02_init_cmds[] = {
44 /* Switch to page 0 */
45 { .data = { 0xE0, 0x00 } },
46
47 /* Seems to be some password */
48 { .data = { 0xE1, 0x93} },
49 { .data = { 0xE2, 0x65 } },
50 { .data = { 0xE3, 0xF8 } },
51
52 /* Lane number, 0x02 - 3 lanes, 0x03 - 4 lanes */
53 { .data = { 0x80, 0x03 } },
54
55 /* Sequence control */
56 { .data = { 0x70, 0x02 } },
57 { .data = { 0x71, 0x23 } },
58 { .data = { 0x72, 0x06 } },
59
60 /* Switch to page 1 */
61 { .data = { 0xE0, 0x01 } },
62
63 /* Set VCOM */
64 { .data = { 0x00, 0x00 } },
65 { .data = { 0x01, 0x66 } },
66 /* Set VCOM_Reverse */
67 { .data = { 0x03, 0x00 } },
68 { .data = { 0x04, 0x25 } },
69
70 /* Set Gamma Power, VG[MS][PN] */
71 { .data = { 0x17, 0x00 } },
72 { .data = { 0x18, 0x6D } },
73 { .data = { 0x19, 0x00 } },
74 { .data = { 0x1A, 0x00 } },
75 { .data = { 0x1B, 0xBF } }, /* VGMN = -4.5V */
76 { .data = { 0x1C, 0x00 } },
77
78 /* Set Gate Power */
79 { .data = { 0x1F, 0x3E } }, /* VGH_R = 15V */
80 { .data = { 0x20, 0x28 } }, /* VGL_R = -11V */
81 { .data = { 0x21, 0x28 } }, /* VGL_R2 = -11V */
82 { .data = { 0x22, 0x0E } }, /* PA[6:4] = 0, PA[0] = 0 */
83
84 /* Set Panel */
85 { .data = { 0x37, 0x09 } }, /* SS = 1, BGR = 1 */
86
87 /* Set RGBCYC */
88 { .data = { 0x38, 0x04 } }, /* JDT = 100 column inversion */
89 { .data = { 0x39, 0x08 } }, /* RGB_N_EQ1 */
90 { .data = { 0x3A, 0x12 } }, /* RGB_N_EQ2 */
91 { .data = { 0x3C, 0x78 } }, /* set EQ3 for TE_H */
92 { .data = { 0x3D, 0xFF } }, /* set CHGEN_ON */
93 { .data = { 0x3E, 0xFF } }, /* set CHGEN_OFF */
94 { .data = { 0x3F, 0x7F } }, /* set CHGEN_OFF2 */
95
96 /* Set TCON parameter */
97 { .data = { 0x40, 0x06 } }, /* RSO = 800 points */
98 { .data = { 0x41, 0xA0 } }, /* LN = 1280 lines */
99
100 /* Set power voltage */
101 { .data = { 0x55, 0x0F } }, /* DCDCM */
102 { .data = { 0x56, 0x01 } },
103 { .data = { 0x57, 0x69 } },
104 { .data = { 0x58, 0x0A } },
105 { .data = { 0x59, 0x0A } },
106 { .data = { 0x5A, 0x45 } },
107 { .data = { 0x5B, 0x15 } },
108
109 /* Set gamma */
110 { .data = { 0x5D, 0x7C } },
111 { .data = { 0x5E, 0x65 } },
112 { .data = { 0x5F, 0x55 } },
113 { .data = { 0x60, 0x49 } },
114 { .data = { 0x61, 0x44 } },
115 { .data = { 0x62, 0x35 } },
116 { .data = { 0x63, 0x3A } },
117 { .data = { 0x64, 0x23 } },
118 { .data = { 0x65, 0x3D } },
119 { .data = { 0x66, 0x3C } },
120 { .data = { 0x67, 0x3D } },
121 { .data = { 0x68, 0x5D } },
122 { .data = { 0x69, 0x4D } },
123 { .data = { 0x6A, 0x56 } },
124 { .data = { 0x6B, 0x48 } },
125 { .data = { 0x6C, 0x45 } },
126 { .data = { 0x6D, 0x38 } },
127 { .data = { 0x6E, 0x25 } },
128 { .data = { 0x6F, 0x00 } },
129 { .data = { 0x70, 0x7C } },
130 { .data = { 0x71, 0x65 } },
131 { .data = { 0x72, 0x55 } },
132 { .data = { 0x73, 0x49 } },
133 { .data = { 0x74, 0x44 } },
134 { .data = { 0x75, 0x35 } },
135 { .data = { 0x76, 0x3A } },
136 { .data = { 0x77, 0x23 } },
137 { .data = { 0x78, 0x3D } },
138 { .data = { 0x79, 0x3C } },
139 { .data = { 0x7A, 0x3D } },
140 { .data = { 0x7B, 0x5D } },
141 { .data = { 0x7C, 0x4D } },
142 { .data = { 0x7D, 0x56 } },
143 { .data = { 0x7E, 0x48 } },
144 { .data = { 0x7F, 0x45 } },
145 { .data = { 0x80, 0x38 } },
146 { .data = { 0x81, 0x25 } },
147 { .data = { 0x82, 0x00 } },
148
149 /* Switch to page 2, for GIP */
150 { .data = { 0xE0, 0x02 } },
151
152 { .data = { 0x00, 0x1E } },
153 { .data = { 0x01, 0x1E } },
154 { .data = { 0x02, 0x41 } },
155 { .data = { 0x03, 0x41 } },
156 { .data = { 0x04, 0x43 } },
157 { .data = { 0x05, 0x43 } },
158 { .data = { 0x06, 0x1F } },
159 { .data = { 0x07, 0x1F } },
160 { .data = { 0x08, 0x1F } },
161 { .data = { 0x09, 0x1F } },
162 { .data = { 0x0A, 0x1E } },
163 { .data = { 0x0B, 0x1E } },
164 { .data = { 0x0C, 0x1F } },
165 { .data = { 0x0D, 0x47 } },
166 { .data = { 0x0E, 0x47 } },
167 { .data = { 0x0F, 0x45 } },
168 { .data = { 0x10, 0x45 } },
169 { .data = { 0x11, 0x4B } },
170 { .data = { 0x12, 0x4B } },
171 { .data = { 0x13, 0x49 } },
172 { .data = { 0x14, 0x49 } },
173 { .data = { 0x15, 0x1F } },
174
175 { .data = { 0x16, 0x1E } },
176 { .data = { 0x17, 0x1E } },
177 { .data = { 0x18, 0x40 } },
178 { .data = { 0x19, 0x40 } },
179 { .data = { 0x1A, 0x42 } },
180 { .data = { 0x1B, 0x42 } },
181 { .data = { 0x1C, 0x1F } },
182 { .data = { 0x1D, 0x1F } },
183 { .data = { 0x1E, 0x1F } },
184 { .data = { 0x1F, 0x1f } },
185 { .data = { 0x20, 0x1E } },
186 { .data = { 0x21, 0x1E } },
187 { .data = { 0x22, 0x1f } },
188 { .data = { 0x23, 0x46 } },
189 { .data = { 0x24, 0x46 } },
190 { .data = { 0x25, 0x44 } },
191 { .data = { 0x26, 0x44 } },
192 { .data = { 0x27, 0x4A } },
193 { .data = { 0x28, 0x4A } },
194 { .data = { 0x29, 0x48 } },
195 { .data = { 0x2A, 0x48 } },
196 { .data = { 0x2B, 0x1f } },
197
198 { .data = { 0x2C, 0x1F } },
199 { .data = { 0x2D, 0x1F } },
200 { .data = { 0x2E, 0x42 } },
201 { .data = { 0x2F, 0x42 } },
202 { .data = { 0x30, 0x40 } },
203 { .data = { 0x31, 0x40 } },
204 { .data = { 0x32, 0x1E } },
205 { .data = { 0x33, 0x1E } },
206 { .data = { 0x34, 0x1F } },
207 { .data = { 0x35, 0x1F } },
208 { .data = { 0x36, 0x1E } },
209 { .data = { 0x37, 0x1E } },
210 { .data = { 0x38, 0x1F } },
211 { .data = { 0x39, 0x48 } },
212 { .data = { 0x3A, 0x48 } },
213 { .data = { 0x3B, 0x4A } },
214 { .data = { 0x3C, 0x4A } },
215 { .data = { 0x3D, 0x44 } },
216 { .data = { 0x3E, 0x44 } },
217 { .data = { 0x3F, 0x46 } },
218 { .data = { 0x40, 0x46 } },
219 { .data = { 0x41, 0x1F } },
220
221 { .data = { 0x42, 0x1F } },
222 { .data = { 0x43, 0x1F } },
223 { .data = { 0x44, 0x43 } },
224 { .data = { 0x45, 0x43 } },
225 { .data = { 0x46, 0x41 } },
226 { .data = { 0x47, 0x41 } },
227 { .data = { 0x48, 0x1E } },
228 { .data = { 0x49, 0x1E } },
229 { .data = { 0x4A, 0x1E } },
230 { .data = { 0x4B, 0x1F } },
231 { .data = { 0x4C, 0x1E } },
232 { .data = { 0x4D, 0x1E } },
233 { .data = { 0x4E, 0x1F } },
234 { .data = { 0x4F, 0x49 } },
235 { .data = { 0x50, 0x49 } },
236 { .data = { 0x51, 0x4B } },
237 { .data = { 0x52, 0x4B } },
238 { .data = { 0x53, 0x45 } },
239 { .data = { 0x54, 0x45 } },
240 { .data = { 0x55, 0x47 } },
241 { .data = { 0x56, 0x47 } },
242 { .data = { 0x57, 0x1F } },
243
244 { .data = { 0x58, 0x10 } },
245 { .data = { 0x59, 0x00 } },
246 { .data = { 0x5A, 0x00 } },
247 { .data = { 0x5B, 0x30 } },
248 { .data = { 0x5C, 0x02 } },
249 { .data = { 0x5D, 0x40 } },
250 { .data = { 0x5E, 0x01 } },
251 { .data = { 0x5F, 0x02 } },
252 { .data = { 0x60, 0x30 } },
253 { .data = { 0x61, 0x01 } },
254 { .data = { 0x62, 0x02 } },
255 { .data = { 0x63, 0x6A } },
256 { .data = { 0x64, 0x6A } },
257 { .data = { 0x65, 0x05 } },
258 { .data = { 0x66, 0x12 } },
259 { .data = { 0x67, 0x74 } },
260 { .data = { 0x68, 0x04 } },
261 { .data = { 0x69, 0x6A } },
262 { .data = { 0x6A, 0x6A } },
263 { .data = { 0x6B, 0x08 } },
264
265 { .data = { 0x6C, 0x00 } },
266 { .data = { 0x6D, 0x04 } },
267 { .data = { 0x6E, 0x04 } },
268 { .data = { 0x6F, 0x88 } },
269 { .data = { 0x70, 0x00 } },
270 { .data = { 0x71, 0x00 } },
271 { .data = { 0x72, 0x06 } },
272 { .data = { 0x73, 0x7B } },
273 { .data = { 0x74, 0x00 } },
274 { .data = { 0x75, 0x07 } },
275 { .data = { 0x76, 0x00 } },
276 { .data = { 0x77, 0x5D } },
277 { .data = { 0x78, 0x17 } },
278 { .data = { 0x79, 0x1F } },
279 { .data = { 0x7A, 0x00 } },
280 { .data = { 0x7B, 0x00 } },
281 { .data = { 0x7C, 0x00 } },
282 { .data = { 0x7D, 0x03 } },
283 { .data = { 0x7E, 0x7B } },
284
285 { .data = { 0xE0, 0x04 } },
286 { .data = { 0x2B, 0x2B } },
287 { .data = { 0x2E, 0x44 } },
288
289 { .data = { 0xE0, 0x01 } },
290 { .data = { 0x0E, 0x01 } },
291
292 { .data = { 0xE0, 0x03 } },
293 { .data = { 0x98, 0x2F } },
294
295 { .data = { 0xE0, 0x00 } },
296 { .data = { 0xE6, 0x02 } },
297 { .data = { 0xE7, 0x02 } },
298
299 { .data = { 0x11, 0x00 } },
300};
301
302static const struct k101_im2ba02_init_cmd timed_cmds[] = {
303 { .data = { 0x29, 0x00 } },
304 { .data = { 0x35, 0x00 } },
305};
306
307static int k101_im2ba02_prepare(struct drm_panel *panel)
308{
309 struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);
310 struct mipi_dsi_device *dsi = ctx->dsi;
311 unsigned int i;
312 int ret;
313
314 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
315 if (ret)
316 return ret;
317
318 msleep(30);
319
320 gpiod_set_value(ctx->reset, 1);
321 msleep(50);
322
323 gpiod_set_value(ctx->reset, 0);
324 msleep(50);
325
326 gpiod_set_value(ctx->reset, 1);
327 msleep(200);
328
329 for (i = 0; i < ARRAY_SIZE(k101_im2ba02_init_cmds); i++) {
330 const struct k101_im2ba02_init_cmd *cmd = &k101_im2ba02_init_cmds[i];
331
332 ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data, K101_IM2BA02_INIT_CMD_LEN);
333 if (ret < 0)
334 goto powerdown;
335 }
336
337 return 0;
338
339powerdown:
340 gpiod_set_value(ctx->reset, 0);
341 msleep(50);
342
343 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
344}
345
346static int k101_im2ba02_enable(struct drm_panel *panel)
347{
348 struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);
349 const struct k101_im2ba02_init_cmd *cmd = &timed_cmds[1];
350 int ret;
351
352 msleep(150);
353
354 ret = mipi_dsi_dcs_set_display_on(ctx->dsi);
355 if (ret < 0)
356 return ret;
357
358 msleep(50);
359
360 return mipi_dsi_dcs_write_buffer(ctx->dsi, cmd->data, K101_IM2BA02_INIT_CMD_LEN);
361}
362
363static int k101_im2ba02_disable(struct drm_panel *panel)
364{
365 struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);
366
367 return mipi_dsi_dcs_set_display_off(ctx->dsi);
368}
369
370static int k101_im2ba02_unprepare(struct drm_panel *panel)
371{
372 struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);
373 int ret;
374
375 ret = mipi_dsi_dcs_set_display_off(ctx->dsi);
376 if (ret < 0)
377 DRM_DEV_ERROR(panel->dev, "failed to set display off: %d\n",
378 ret);
379
380 ret = mipi_dsi_dcs_enter_sleep_mode(ctx->dsi);
381 if (ret < 0)
382 DRM_DEV_ERROR(panel->dev, "failed to enter sleep mode: %d\n",
383 ret);
384
385 msleep(200);
386
387 gpiod_set_value(ctx->reset, 0);
388 msleep(20);
389
390 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
391}
392
393static const struct drm_display_mode k101_im2ba02_default_mode = {
394 .clock = 70000,
395 .vrefresh = 60,
396
397 .hdisplay = 800,
398 .hsync_start = 800 + 20,
399 .hsync_end = 800 + 20 + 20,
400 .htotal = 800 + 20 + 20 + 20,
401
402 .vdisplay = 1280,
403 .vsync_start = 1280 + 16,
404 .vsync_end = 1280 + 16 + 4,
405 .vtotal = 1280 + 16 + 4 + 4,
406
407 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
408 .width_mm = 136,
409 .height_mm = 217,
410};
411
412static int k101_im2ba02_get_modes(struct drm_panel *panel,
413 struct drm_connector *connector)
414{
415 struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);
416 struct drm_display_mode *mode;
417
418 mode = drm_mode_duplicate(connector->dev, &k101_im2ba02_default_mode);
419 if (!mode) {
420 DRM_DEV_ERROR(&ctx->dsi->dev, "failed to add mode %ux%ux@%u\n",
421 k101_im2ba02_default_mode.hdisplay,
422 k101_im2ba02_default_mode.vdisplay,
423 k101_im2ba02_default_mode.vrefresh);
424 return -ENOMEM;
425 }
426
427 drm_mode_set_name(mode);
428
429 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
430 connector->display_info.width_mm = mode->width_mm;
431 connector->display_info.height_mm = mode->height_mm;
432 drm_mode_probed_add(connector, mode);
433
434 return 1;
435}
436
437static const struct drm_panel_funcs k101_im2ba02_funcs = {
438 .disable = k101_im2ba02_disable,
439 .unprepare = k101_im2ba02_unprepare,
440 .prepare = k101_im2ba02_prepare,
441 .enable = k101_im2ba02_enable,
442 .get_modes = k101_im2ba02_get_modes,
443};
444
445static int k101_im2ba02_dsi_probe(struct mipi_dsi_device *dsi)
446{
447 struct k101_im2ba02 *ctx;
448 unsigned int i;
449 int ret;
450
451 ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL);
452 if (!ctx)
453 return -ENOMEM;
454
455 mipi_dsi_set_drvdata(dsi, ctx);
456 ctx->dsi = dsi;
457
458 for (i = 0; i < ARRAY_SIZE(ctx->supplies); i++)
459 ctx->supplies[i].supply = regulator_names[i];
460
461 ret = devm_regulator_bulk_get(&dsi->dev, ARRAY_SIZE(ctx->supplies),
462 ctx->supplies);
463 if (ret < 0) {
464 DRM_DEV_ERROR(&dsi->dev, "Couldn't get regulators\n");
465 return ret;
466 }
467
468 ctx->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW);
469 if (IS_ERR(ctx->reset)) {
470 DRM_DEV_ERROR(&dsi->dev, "Couldn't get our reset GPIO\n");
471 return PTR_ERR(ctx->reset);
472 }
473
474 drm_panel_init(&ctx->panel, &dsi->dev, &k101_im2ba02_funcs,
475 DRM_MODE_CONNECTOR_DSI);
476
477 ret = drm_panel_of_backlight(&ctx->panel);
478 if (ret)
479 return ret;
480
481 ret = drm_panel_add(&ctx->panel);
482 if (ret < 0)
483 return ret;
484
485 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
486 dsi->format = MIPI_DSI_FMT_RGB888;
487 dsi->lanes = 4;
488
489 ret = mipi_dsi_attach(dsi);
490 if (ret < 0) {
491 drm_panel_remove(&ctx->panel);
492 return ret;
493 }
494
495 return 0;
496}
497
498static int k101_im2ba02_dsi_remove(struct mipi_dsi_device *dsi)
499{
500 struct k101_im2ba02 *ctx = mipi_dsi_get_drvdata(dsi);
501
502 mipi_dsi_detach(dsi);
503 drm_panel_remove(&ctx->panel);
504
505 return 0;
506}
507
508static const struct of_device_id k101_im2ba02_of_match[] = {
509 { .compatible = "feixin,k101-im2ba02", },
510 { /* sentinel */ }
511};
512MODULE_DEVICE_TABLE(of, k101_im2ba02_of_match);
513
514static struct mipi_dsi_driver k101_im2ba02_driver = {
515 .probe = k101_im2ba02_dsi_probe,
516 .remove = k101_im2ba02_dsi_remove,
517 .driver = {
518 .name = "feixin-k101-im2ba02",
519 .of_match_table = k101_im2ba02_of_match,
520 },
521};
522module_mipi_dsi_driver(k101_im2ba02_driver);
523
524MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
525MODULE_DESCRIPTION("Feixin K101 IM2BA02 MIPI-DSI LCD panel");
526MODULE_LICENSE("GPL");