tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
4 *
5 * Common Clock Framework support for S3C2443 and following SoCs.
6 */
7
8#include <linux/clk-provider.h>
9#include <linux/io.h>
10#include <linux/of.h>
11#include <linux/of_address.h>
12#include <linux/reboot.h>
13
14#include <dt-bindings/clock/s3c2443.h>
15
16#include "clk.h"
17#include "clk-pll.h"
18
19/* S3C2416 clock controller register offsets */
20#define LOCKCON0 0x00
21#define LOCKCON1 0x04
22#define MPLLCON 0x10
23#define EPLLCON 0x18
24#define EPLLCON_K 0x1C
25#define CLKSRC 0x20
26#define CLKDIV0 0x24
27#define CLKDIV1 0x28
28#define CLKDIV2 0x2C
29#define HCLKCON 0x30
30#define PCLKCON 0x34
31#define SCLKCON 0x38
32#define SWRST 0x44
33
34/* the soc types */
35enum supported_socs {
36 S3C2416,
37 S3C2443,
38 S3C2450,
39};
40
41static void __iomem *reg_base;
42
43/*
44 * list of controller registers to be saved and restored during a
45 * suspend/resume cycle.
46 */
47static unsigned long s3c2443_clk_regs[] __initdata = {
48 LOCKCON0,
49 LOCKCON1,
50 MPLLCON,
51 EPLLCON,
52 EPLLCON_K,
53 CLKSRC,
54 CLKDIV0,
55 CLKDIV1,
56 CLKDIV2,
57 PCLKCON,
58 HCLKCON,
59 SCLKCON,
60};
61
62PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" };
63PNAME(esysclk_p) = { "epllref", "epll" };
64PNAME(mpllref_p) = { "xti", "mdivclk" };
65PNAME(msysclk_p) = { "mpllref", "mpll" };
66PNAME(armclk_p) = { "armdiv" , "hclk" };
67PNAME(i2s0_p) = { "div_i2s0", "ext_i2s", "epllref", "epllref" };
68
69static struct samsung_mux_clock s3c2443_common_muxes[] __initdata = {
70 MUX(0, "epllref", epllref_p, CLKSRC, 7, 2),
71 MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1),
72 MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1),
73 MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
74 MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1),
75 MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2),
76};
77
78static struct clk_div_table hclk_d[] = {
79 { .val = 0, .div = 1 },
80 { .val = 1, .div = 2 },
81 { .val = 3, .div = 4 },
82 { /* sentinel */ },
83};
84
85static struct clk_div_table mdivclk_d[] = {
86 { .val = 0, .div = 1 },
87 { .val = 1, .div = 3 },
88 { .val = 2, .div = 5 },
89 { .val = 3, .div = 7 },
90 { .val = 4, .div = 9 },
91 { .val = 5, .div = 11 },
92 { .val = 6, .div = 13 },
93 { .val = 7, .div = 15 },
94 { /* sentinel */ },
95};
96
97static struct samsung_div_clock s3c2443_common_dividers[] __initdata = {
98 DIV_T(0, "mdivclk", "xti", CLKDIV0, 6, 3, mdivclk_d),
99 DIV(0, "prediv", "msysclk", CLKDIV0, 4, 2),
100 DIV_T(HCLK, "hclk", "prediv", CLKDIV0, 0, 2, hclk_d),
101 DIV(PCLK, "pclk", "hclk", CLKDIV0, 2, 1),
102 DIV(0, "div_hsspi0_epll", "esysclk", CLKDIV1, 24, 2),
103 DIV(0, "div_fimd", "esysclk", CLKDIV1, 16, 8),
104 DIV(0, "div_i2s0", "esysclk", CLKDIV1, 12, 4),
105 DIV(0, "div_uart", "esysclk", CLKDIV1, 8, 4),
106 DIV(0, "div_hsmmc1", "esysclk", CLKDIV1, 6, 2),
107 DIV(0, "div_usbhost", "esysclk", CLKDIV1, 4, 2),
108};
109
110static struct samsung_gate_clock s3c2443_common_gates[] __initdata = {
111 GATE(SCLK_HSMMC_EXT, "sclk_hsmmcext", "ext", SCLKCON, 13, 0, 0),
112 GATE(SCLK_HSMMC1, "sclk_hsmmc1", "div_hsmmc1", SCLKCON, 12, 0, 0),
113 GATE(SCLK_FIMD, "sclk_fimd", "div_fimd", SCLKCON, 10, 0, 0),
114 GATE(SCLK_I2S0, "sclk_i2s0", "mux_i2s0", SCLKCON, 9, 0, 0),
115 GATE(SCLK_UART, "sclk_uart", "div_uart", SCLKCON, 8, 0, 0),
116 GATE(SCLK_USBH, "sclk_usbhost", "div_usbhost", SCLKCON, 1, 0, 0),
117 GATE(HCLK_DRAM, "dram", "hclk", HCLKCON, 19, CLK_IGNORE_UNUSED, 0),
118 GATE(HCLK_SSMC, "ssmc", "hclk", HCLKCON, 18, CLK_IGNORE_UNUSED, 0),
119 GATE(HCLK_HSMMC1, "hsmmc1", "hclk", HCLKCON, 16, 0, 0),
120 GATE(HCLK_USBD, "usb-device", "hclk", HCLKCON, 12, 0, 0),
121 GATE(HCLK_USBH, "usb-host", "hclk", HCLKCON, 11, 0, 0),
122 GATE(HCLK_LCD, "lcd", "hclk", HCLKCON, 9, 0, 0),
123 GATE(HCLK_DMA5, "dma5", "hclk", HCLKCON, 5, CLK_IGNORE_UNUSED, 0),
124 GATE(HCLK_DMA4, "dma4", "hclk", HCLKCON, 4, CLK_IGNORE_UNUSED, 0),
125 GATE(HCLK_DMA3, "dma3", "hclk", HCLKCON, 3, CLK_IGNORE_UNUSED, 0),
126 GATE(HCLK_DMA2, "dma2", "hclk", HCLKCON, 2, CLK_IGNORE_UNUSED, 0),
127 GATE(HCLK_DMA1, "dma1", "hclk", HCLKCON, 1, CLK_IGNORE_UNUSED, 0),
128 GATE(HCLK_DMA0, "dma0", "hclk", HCLKCON, 0, CLK_IGNORE_UNUSED, 0),
129 GATE(PCLK_GPIO, "gpio", "pclk", PCLKCON, 13, CLK_IGNORE_UNUSED, 0),
130 GATE(PCLK_RTC, "rtc", "pclk", PCLKCON, 12, 0, 0),
131 GATE(PCLK_WDT, "wdt", "pclk", PCLKCON, 11, 0, 0),
132 GATE(PCLK_PWM, "pwm", "pclk", PCLKCON, 10, 0, 0),
133 GATE(PCLK_I2S0, "i2s0", "pclk", PCLKCON, 9, 0, 0),
134 GATE(PCLK_AC97, "ac97", "pclk", PCLKCON, 8, 0, 0),
135 GATE(PCLK_ADC, "adc", "pclk", PCLKCON, 7, 0, 0),
136 GATE(PCLK_SPI0, "spi0", "pclk", PCLKCON, 6, 0, 0),
137 GATE(PCLK_I2C0, "i2c0", "pclk", PCLKCON, 4, 0, 0),
138 GATE(PCLK_UART3, "uart3", "pclk", PCLKCON, 3, 0, 0),
139 GATE(PCLK_UART2, "uart2", "pclk", PCLKCON, 2, 0, 0),
140 GATE(PCLK_UART1, "uart1", "pclk", PCLKCON, 1, 0, 0),
141 GATE(PCLK_UART0, "uart0", "pclk", PCLKCON, 0, 0, 0),
142};
143
144static struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
145 ALIAS(MSYSCLK, NULL, "msysclk"),
146 ALIAS(ARMCLK, NULL, "armclk"),
147 ALIAS(MPLL, NULL, "mpll"),
148 ALIAS(EPLL, NULL, "epll"),
149 ALIAS(HCLK, NULL, "hclk"),
150 ALIAS(HCLK_SSMC, NULL, "nand"),
151 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
152 ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
153 ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
154 ALIAS(PCLK_UART3, "s3c2440-uart.3", "uart"),
155 ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
156 ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
157 ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
158 ALIAS(PCLK_UART3, "s3c2440-uart.3", "clk_uart_baud2"),
159 ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
160 ALIAS(PCLK_PWM, NULL, "timers"),
161 ALIAS(PCLK_RTC, NULL, "rtc"),
162 ALIAS(PCLK_WDT, NULL, "watchdog"),
163 ALIAS(PCLK_ADC, NULL, "adc"),
164 ALIAS(PCLK_I2C0, "s3c2410-i2c.0", "i2c"),
165 ALIAS(HCLK_USBD, NULL, "usb-device"),
166 ALIAS(HCLK_USBH, NULL, "usb-host"),
167 ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
168 ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi"),
169 ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi_busclk0"),
170 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"),
171 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
172 ALIAS(PCLK_I2S0, "samsung-i2s.0", "iis"),
173 ALIAS(SCLK_I2S0, NULL, "i2s-if"),
174 ALIAS(HCLK_LCD, NULL, "lcd"),
175 ALIAS(SCLK_FIMD, NULL, "sclk_fimd"),
176};
177
178/* S3C2416 specific clocks */
179
180static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = {
181 PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
182 PLL(pll_6553, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
183};
184
185PNAME(s3c2416_hsmmc0_p) = { "sclk_hsmmc0", "sclk_hsmmcext" };
186PNAME(s3c2416_hsmmc1_p) = { "sclk_hsmmc1", "sclk_hsmmcext" };
187PNAME(s3c2416_hsspi0_p) = { "hsspi0_epll", "hsspi0_mpll" };
188
189static struct clk_div_table armdiv_s3c2416_d[] = {
190 { .val = 0, .div = 1 },
191 { .val = 1, .div = 2 },
192 { .val = 2, .div = 3 },
193 { .val = 3, .div = 4 },
194 { .val = 5, .div = 6 },
195 { .val = 7, .div = 8 },
196 { /* sentinel */ },
197};
198
199static struct samsung_div_clock s3c2416_dividers[] __initdata = {
200 DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 3, armdiv_s3c2416_d),
201 DIV(0, "div_hsspi0_mpll", "msysclk", CLKDIV2, 0, 4),
202 DIV(0, "div_hsmmc0", "esysclk", CLKDIV2, 6, 2),
203};
204
205static struct samsung_mux_clock s3c2416_muxes[] __initdata = {
206 MUX(MUX_HSMMC0, "mux_hsmmc0", s3c2416_hsmmc0_p, CLKSRC, 16, 1),
207 MUX(MUX_HSMMC1, "mux_hsmmc1", s3c2416_hsmmc1_p, CLKSRC, 17, 1),
208 MUX(MUX_HSSPI0, "mux_hsspi0", s3c2416_hsspi0_p, CLKSRC, 18, 1),
209};
210
211static struct samsung_gate_clock s3c2416_gates[] __initdata = {
212 GATE(0, "hsspi0_mpll", "div_hsspi0_mpll", SCLKCON, 19, 0, 0),
213 GATE(0, "hsspi0_epll", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
214 GATE(0, "sclk_hsmmc0", "div_hsmmc0", SCLKCON, 6, 0, 0),
215 GATE(HCLK_2D, "2d", "hclk", HCLKCON, 20, 0, 0),
216 GATE(HCLK_HSMMC0, "hsmmc0", "hclk", HCLKCON, 15, 0, 0),
217 GATE(HCLK_IROM, "irom", "hclk", HCLKCON, 13, CLK_IGNORE_UNUSED, 0),
218 GATE(PCLK_PCM, "pcm", "pclk", PCLKCON, 19, 0, 0),
219};
220
221static struct samsung_clock_alias s3c2416_aliases[] __initdata = {
222 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
223 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
224 ALIAS(MUX_HSMMC0, "s3c-sdhci.0", "mmc_busclk.2"),
225 ALIAS(MUX_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"),
226 ALIAS(MUX_HSSPI0, "s3c2443-spi.0", "spi_busclk2"),
227 ALIAS(ARMDIV, NULL, "armdiv"),
228};
229
230/* S3C2443 specific clocks */
231
232static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = {
233 PLL(pll_3000, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
234 PLL(pll_2126, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
235};
236
237static struct clk_div_table armdiv_s3c2443_d[] = {
238 { .val = 0, .div = 1 },
239 { .val = 8, .div = 2 },
240 { .val = 2, .div = 3 },
241 { .val = 9, .div = 4 },
242 { .val = 10, .div = 6 },
243 { .val = 11, .div = 8 },
244 { .val = 13, .div = 12 },
245 { .val = 15, .div = 16 },
246 { /* sentinel */ },
247};
248
249static struct samsung_div_clock s3c2443_dividers[] __initdata = {
250 DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 4, armdiv_s3c2443_d),
251 DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4),
252};
253
254static struct samsung_gate_clock s3c2443_gates[] __initdata = {
255 GATE(SCLK_HSSPI0, "sclk_hsspi0", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
256 GATE(SCLK_CAM, "sclk_cam", "div_cam", SCLKCON, 11, 0, 0),
257 GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, CLK_IGNORE_UNUSED, 0),
258 GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
259 GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 15, 0, 0),
260 GATE(PCLK_SDI, "sdi", "pclk", PCLKCON, 5, 0, 0),
261};
262
263static struct samsung_clock_alias s3c2443_aliases[] __initdata = {
264 ALIAS(SCLK_HSSPI0, "s3c2443-spi.0", "spi_busclk2"),
265 ALIAS(SCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"),
266 ALIAS(SCLK_CAM, NULL, "camif-upll"),
267 ALIAS(PCLK_SPI1, "s3c2410-spi.0", "spi"),
268 ALIAS(PCLK_SDI, NULL, "sdi"),
269 ALIAS(HCLK_CFC, NULL, "cfc"),
270 ALIAS(ARMDIV, NULL, "armdiv"),
271};
272
273/* S3C2450 specific clocks */
274
275PNAME(s3c2450_cam_p) = { "div_cam", "hclk" };
276PNAME(s3c2450_hsspi1_p) = { "hsspi1_epll", "hsspi1_mpll" };
277PNAME(i2s1_p) = { "div_i2s1", "ext_i2s", "epllref", "epllref" };
278
279static struct samsung_div_clock s3c2450_dividers[] __initdata = {
280 DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4),
281 DIV(0, "div_hsspi1_epll", "esysclk", CLKDIV2, 24, 2),
282 DIV(0, "div_hsspi1_mpll", "msysclk", CLKDIV2, 16, 4),
283 DIV(0, "div_i2s1", "esysclk", CLKDIV2, 12, 4),
284};
285
286static struct samsung_mux_clock s3c2450_muxes[] __initdata = {
287 MUX(0, "mux_cam", s3c2450_cam_p, CLKSRC, 20, 1),
288 MUX(MUX_HSSPI1, "mux_hsspi1", s3c2450_hsspi1_p, CLKSRC, 19, 1),
289 MUX(0, "mux_i2s1", i2s1_p, CLKSRC, 12, 2),
290};
291
292static struct samsung_gate_clock s3c2450_gates[] __initdata = {
293 GATE(SCLK_I2S1, "sclk_i2s1", "div_i2s1", SCLKCON, 5, 0, 0),
294 GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, 0, 0),
295 GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
296 GATE(HCLK_DMA7, "dma7", "hclk", HCLKCON, 7, CLK_IGNORE_UNUSED, 0),
297 GATE(HCLK_DMA6, "dma6", "hclk", HCLKCON, 6, CLK_IGNORE_UNUSED, 0),
298 GATE(PCLK_I2S1, "i2s1", "pclk", PCLKCON, 17, 0, 0),
299 GATE(PCLK_I2C1, "i2c1", "pclk", PCLKCON, 16, 0, 0),
300 GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 14, 0, 0),
301};
302
303static struct samsung_clock_alias s3c2450_aliases[] __initdata = {
304 ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi"),
305 ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi_busclk0"),
306 ALIAS(MUX_HSSPI1, "s3c2443-spi.1", "spi_busclk2"),
307 ALIAS(PCLK_I2C1, "s3c2410-i2c.1", "i2c"),
308};
309
310static int s3c2443_restart(struct notifier_block *this,
311 unsigned long mode, void *cmd)
312{
313 __raw_writel(0x533c2443, reg_base + SWRST);
314 return NOTIFY_DONE;
315}
316
317static struct notifier_block s3c2443_restart_handler = {
318 .notifier_call = s3c2443_restart,
319 .priority = 129,
320};
321
322/*
323 * fixed rate clocks generated outside the soc
324 * Only necessary until the devicetree-move is complete
325 */
326static struct samsung_fixed_rate_clock s3c2443_common_frate_clks[] __initdata = {
327 FRATE(0, "xti", NULL, 0, 0),
328 FRATE(0, "ext", NULL, 0, 0),
329 FRATE(0, "ext_i2s", NULL, 0, 0),
330 FRATE(0, "ext_uart", NULL, 0, 0),
331};
332
333static void __init s3c2443_common_clk_register_fixed_ext(
334 struct samsung_clk_provider *ctx, unsigned long xti_f)
335{
336 s3c2443_common_frate_clks[0].fixed_rate = xti_f;
337 samsung_clk_register_fixed_rate(ctx, s3c2443_common_frate_clks,
338 ARRAY_SIZE(s3c2443_common_frate_clks));
339}
340
341void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
342 int current_soc,
343 void __iomem *base)
344{
345 struct samsung_clk_provider *ctx;
346 int ret;
347 reg_base = base;
348
349 if (np) {
350 reg_base = of_iomap(np, 0);
351 if (!reg_base)
352 panic("%s: failed to map registers\n", __func__);
353 }
354
355 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
356
357 /* Register external clocks only in non-dt cases */
358 if (!np)
359 s3c2443_common_clk_register_fixed_ext(ctx, xti_f);
360
361 /* Register PLLs. */
362 if (current_soc == S3C2416 || current_soc == S3C2450)
363 samsung_clk_register_pll(ctx, s3c2416_pll_clks,
364 ARRAY_SIZE(s3c2416_pll_clks), reg_base);
365 else
366 samsung_clk_register_pll(ctx, s3c2443_pll_clks,
367 ARRAY_SIZE(s3c2443_pll_clks), reg_base);
368
369 /* Register common internal clocks. */
370 samsung_clk_register_mux(ctx, s3c2443_common_muxes,
371 ARRAY_SIZE(s3c2443_common_muxes));
372 samsung_clk_register_div(ctx, s3c2443_common_dividers,
373 ARRAY_SIZE(s3c2443_common_dividers));
374 samsung_clk_register_gate(ctx, s3c2443_common_gates,
375 ARRAY_SIZE(s3c2443_common_gates));
376 samsung_clk_register_alias(ctx, s3c2443_common_aliases,
377 ARRAY_SIZE(s3c2443_common_aliases));
378
379 /* Register SoC-specific clocks. */
380 switch (current_soc) {
381 case S3C2450:
382 samsung_clk_register_div(ctx, s3c2450_dividers,
383 ARRAY_SIZE(s3c2450_dividers));
384 samsung_clk_register_mux(ctx, s3c2450_muxes,
385 ARRAY_SIZE(s3c2450_muxes));
386 samsung_clk_register_gate(ctx, s3c2450_gates,
387 ARRAY_SIZE(s3c2450_gates));
388 samsung_clk_register_alias(ctx, s3c2450_aliases,
389 ARRAY_SIZE(s3c2450_aliases));
390 /* fall through - as s3c2450 extends the s3c2416 clocks */
391 case S3C2416:
392 samsung_clk_register_div(ctx, s3c2416_dividers,
393 ARRAY_SIZE(s3c2416_dividers));
394 samsung_clk_register_mux(ctx, s3c2416_muxes,
395 ARRAY_SIZE(s3c2416_muxes));
396 samsung_clk_register_gate(ctx, s3c2416_gates,
397 ARRAY_SIZE(s3c2416_gates));
398 samsung_clk_register_alias(ctx, s3c2416_aliases,
399 ARRAY_SIZE(s3c2416_aliases));
400 break;
401 case S3C2443:
402 samsung_clk_register_div(ctx, s3c2443_dividers,
403 ARRAY_SIZE(s3c2443_dividers));
404 samsung_clk_register_gate(ctx, s3c2443_gates,
405 ARRAY_SIZE(s3c2443_gates));
406 samsung_clk_register_alias(ctx, s3c2443_aliases,
407 ARRAY_SIZE(s3c2443_aliases));
408 break;
409 }
410
411 samsung_clk_sleep_init(reg_base, s3c2443_clk_regs,
412 ARRAY_SIZE(s3c2443_clk_regs));
413
414 samsung_clk_of_add_provider(np, ctx);
415
416 ret = register_restart_handler(&s3c2443_restart_handler);
417 if (ret)
418 pr_warn("cannot register restart handler, %d\n", ret);
419}
420
421static void __init s3c2416_clk_init(struct device_node *np)
422{
423 s3c2443_common_clk_init(np, 0, S3C2416, NULL);
424}
425CLK_OF_DECLARE(s3c2416_clk, "samsung,s3c2416-clock", s3c2416_clk_init);
426
427static void __init s3c2443_clk_init(struct device_node *np)
428{
429 s3c2443_common_clk_init(np, 0, S3C2443, NULL);
430}
431CLK_OF_DECLARE(s3c2443_clk, "samsung,s3c2443-clock", s3c2443_clk_init);
432
433static void __init s3c2450_clk_init(struct device_node *np)
434{
435 s3c2443_common_clk_init(np, 0, S3C2450, NULL);
436}
437CLK_OF_DECLARE(s3c2450_clk, "samsung,s3c2450-clock", s3c2450_clk_init);