tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1Cadence Sierra PHY
2-----------------------
3
4Required properties:
5- compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
6 Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
7- resets: Must contain an entry for each in reset-names.
8 See ../reset/reset.txt for details.
9- reset-names: Must include "sierra_reset" and "sierra_apb".
10 "sierra_reset" must control the reset line to the PHY.
11 "sierra_apb" must control the reset line to the APB PHY
12 interface ("sierra_apb" is optional).
13- reg: register range for the PHY.
14- #address-cells: Must be 1
15- #size-cells: Must be 0
16
17Optional properties:
18- clocks: Must contain an entry in clock-names.
19 See ../clocks/clock-bindings.txt for details.
20- clock-names: Must contain "cmn_refclk_dig_div" and
21 "cmn_refclk1_dig_div" for configuring the frequency of
22 the clock to the lanes. "phy_clk" is deprecated.
23- cdns,autoconf: A boolean property whose presence indicates that the
24 PHY registers will be configured by hardware. If not
25 present, all sub-node optional properties must be
26 provided.
27
28Sub-nodes:
29 Each group of PHY lanes with a single master lane should be represented as
30 a sub-node. Note that the actual configuration of each lane is determined by
31 hardware strapping, and must match the configuration specified here.
32
33Sub-node required properties:
34- #phy-cells: Generic PHY binding; must be 0.
35- reg: The master lane number. This is the lowest numbered lane
36 in the lane group.
37- resets: Must contain one entry which controls the reset line for the
38 master lane of the sub-node.
39 See ../reset/reset.txt for details.
40
41Sub-node optional properties:
42- cdns,num-lanes: Number of lanes in this group. From 1 to 4. The
43 group is made up of consecutive lanes.
44- cdns,phy-type: Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
45 configuration of lanes.
46
47Example:
48 pcie_phy4: pcie-phy@fd240000 {
49 compatible = "cdns,sierra-phy-t0";
50 reg = <0x0 0xfd240000 0x0 0x40000>;
51 resets = <&phyrst 0>, <&phyrst 1>;
52 reset-names = "sierra_reset", "sierra_apb";
53 clocks = <&phyclock>;
54 clock-names = "phy_clk";
55 #address-cells = <1>;
56 #size-cells = <0>;
57 pcie0_phy0: pcie-phy@0 {
58 reg = <0>;
59 resets = <&phyrst 2>;
60 cdns,num-lanes = <2>;
61 #phy-cells = <0>;
62 cdns,phy-type = <PHY_TYPE_PCIE>;
63 };
64 pcie0_phy1: pcie-phy@2 {
65 reg = <2>;
66 resets = <&phyrst 4>;
67 cdns,num-lanes = <1>;
68 #phy-cells = <0>;
69 cdns,phy-type = <PHY_TYPE_PCIE>;
70 };