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linux
1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2//
3// This file is provided under a dual BSD/GPLv2 license. When using or
4// redistributing this file, you may do so under either license.
5//
6// Copyright(c) 2018 Intel Corporation. All rights reserved.
7//
8// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10// Rander Wang <rander.wang@intel.com>
11// Keyon Jie <yang.jie@linux.intel.com>
12//
13
14/*
15 * Hardware interface for HDA DSP code loader
16 */
17
18#include <linux/firmware.h>
19#include <sound/hdaudio_ext.h>
20#include <sound/sof.h>
21#include "../ops.h"
22#include "hda.h"
23
24#define HDA_FW_BOOT_ATTEMPTS 3
25
26static int cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
27 unsigned int size, struct snd_dma_buffer *dmab,
28 int direction)
29{
30 struct hdac_ext_stream *dsp_stream;
31 struct hdac_stream *hstream;
32 struct pci_dev *pci = to_pci_dev(sdev->dev);
33 int ret;
34
35 if (direction != SNDRV_PCM_STREAM_PLAYBACK) {
36 dev_err(sdev->dev, "error: code loading DMA is playback only\n");
37 return -EINVAL;
38 }
39
40 dsp_stream = hda_dsp_stream_get(sdev, direction);
41
42 if (!dsp_stream) {
43 dev_err(sdev->dev, "error: no stream available\n");
44 return -ENODEV;
45 }
46 hstream = &dsp_stream->hstream;
47 hstream->substream = NULL;
48
49 /* allocate DMA buffer */
50 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab);
51 if (ret < 0) {
52 dev_err(sdev->dev, "error: memory alloc failed: %x\n", ret);
53 goto error;
54 }
55
56 hstream->period_bytes = 0;/* initialize period_bytes */
57 hstream->format_val = format;
58 hstream->bufsize = size;
59
60 ret = hda_dsp_stream_hw_params(sdev, dsp_stream, dmab, NULL);
61 if (ret < 0) {
62 dev_err(sdev->dev, "error: hdac prepare failed: %x\n", ret);
63 goto error;
64 }
65
66 hda_dsp_stream_spib_config(sdev, dsp_stream, HDA_DSP_SPIB_ENABLE, size);
67
68 return hstream->stream_tag;
69
70error:
71 hda_dsp_stream_put(sdev, direction, hstream->stream_tag);
72 snd_dma_free_pages(dmab);
73 return ret;
74}
75
76/*
77 * first boot sequence has some extra steps. core 0 waits for power
78 * status on core 1, so power up core 1 also momentarily, keep it in
79 * reset/stall and then turn it off
80 */
81static int cl_dsp_init(struct snd_sof_dev *sdev, const void *fwdata,
82 u32 fwsize, int stream_tag)
83{
84 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
85 const struct sof_intel_dsp_desc *chip = hda->desc;
86 unsigned int status;
87 int ret;
88 int i;
89
90 /* step 1: power up corex */
91 ret = hda_dsp_core_power_up(sdev, chip->cores_mask);
92 if (ret < 0) {
93 dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
94 goto err;
95 }
96
97 /* DSP is powered up, set all SSPs to slave mode */
98 for (i = 0; i < chip->ssp_count; i++) {
99 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
100 chip->ssp_base_offset
101 + i * SSP_DEV_MEM_SIZE
102 + SSP_SSC1_OFFSET,
103 SSP_SET_SLAVE,
104 SSP_SET_SLAVE);
105 }
106
107 /* step 2: purge FW request */
108 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req,
109 chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW |
110 ((stream_tag - 1) << 9)));
111
112 /* step 3: unset core 0 reset state & unstall/run core 0 */
113 ret = hda_dsp_core_run(sdev, HDA_DSP_CORE_MASK(0));
114 if (ret < 0) {
115 dev_err(sdev->dev, "error: dsp core start failed %d\n", ret);
116 ret = -EIO;
117 goto err;
118 }
119
120 /* step 4: wait for IPC DONE bit from ROM */
121 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
122 chip->ipc_ack, status,
123 ((status & chip->ipc_ack_mask)
124 == chip->ipc_ack_mask),
125 HDA_DSP_REG_POLL_INTERVAL_US,
126 HDA_DSP_INIT_TIMEOUT_US);
127
128 if (ret < 0) {
129 dev_err(sdev->dev, "error: %s: timeout for HIPCIE done\n",
130 __func__);
131 goto err;
132 }
133
134 /* step 5: power down corex */
135 ret = hda_dsp_core_power_down(sdev,
136 chip->cores_mask & ~(HDA_DSP_CORE_MASK(0)));
137 if (ret < 0) {
138 dev_err(sdev->dev, "error: dsp core x power down failed\n");
139 goto err;
140 }
141
142 /* step 6: enable IPC interrupts */
143 hda_dsp_ipc_int_enable(sdev);
144
145 /* step 7: wait for ROM init */
146 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
147 HDA_DSP_SRAM_REG_ROM_STATUS, status,
148 ((status & HDA_DSP_ROM_STS_MASK)
149 == HDA_DSP_ROM_INIT),
150 HDA_DSP_REG_POLL_INTERVAL_US,
151 chip->rom_init_timeout *
152 USEC_PER_MSEC);
153 if (!ret)
154 return 0;
155
156 dev_err(sdev->dev,
157 "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n",
158 __func__);
159
160err:
161 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
162 hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
163
164 return ret;
165}
166
167static int cl_trigger(struct snd_sof_dev *sdev,
168 struct hdac_ext_stream *stream, int cmd)
169{
170 struct hdac_stream *hstream = &stream->hstream;
171 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
172
173 /* code loader is special case that reuses stream ops */
174 switch (cmd) {
175 case SNDRV_PCM_TRIGGER_START:
176 wait_event_timeout(sdev->waitq, !sdev->code_loading,
177 HDA_DSP_CL_TRIGGER_TIMEOUT);
178
179 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
180 1 << hstream->index,
181 1 << hstream->index);
182
183 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
184 sd_offset,
185 SOF_HDA_SD_CTL_DMA_START |
186 SOF_HDA_CL_DMA_SD_INT_MASK,
187 SOF_HDA_SD_CTL_DMA_START |
188 SOF_HDA_CL_DMA_SD_INT_MASK);
189
190 hstream->running = true;
191 return 0;
192 default:
193 return hda_dsp_stream_trigger(sdev, stream, cmd);
194 }
195}
196
197static struct hdac_ext_stream *get_stream_with_tag(struct snd_sof_dev *sdev,
198 int tag)
199{
200 struct hdac_bus *bus = sof_to_bus(sdev);
201 struct hdac_stream *s;
202
203 /* get stream with tag */
204 list_for_each_entry(s, &bus->stream_list, list) {
205 if (s->direction == SNDRV_PCM_STREAM_PLAYBACK &&
206 s->stream_tag == tag) {
207 return stream_to_hdac_ext_stream(s);
208 }
209 }
210
211 return NULL;
212}
213
214static int cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
215 struct hdac_ext_stream *stream)
216{
217 struct hdac_stream *hstream = &stream->hstream;
218 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
219 int ret;
220
221 ret = hda_dsp_stream_spib_config(sdev, stream, HDA_DSP_SPIB_DISABLE, 0);
222
223 hda_dsp_stream_put(sdev, SNDRV_PCM_STREAM_PLAYBACK,
224 hstream->stream_tag);
225 hstream->running = 0;
226 hstream->substream = NULL;
227
228 /* reset BDL address */
229 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
230 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0);
231 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
232 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
233
234 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0);
235 snd_dma_free_pages(dmab);
236 dmab->area = NULL;
237 hstream->bufsize = 0;
238 hstream->format_val = 0;
239
240 return ret;
241}
242
243static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream)
244{
245 unsigned int reg;
246 int ret, status;
247
248 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_START);
249 if (ret < 0) {
250 dev_err(sdev->dev, "error: DMA trigger start failed\n");
251 return ret;
252 }
253
254 status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
255 HDA_DSP_SRAM_REG_ROM_STATUS, reg,
256 ((reg & HDA_DSP_ROM_STS_MASK)
257 == HDA_DSP_ROM_FW_ENTERED),
258 HDA_DSP_REG_POLL_INTERVAL_US,
259 HDA_DSP_BASEFW_TIMEOUT_US);
260
261 /*
262 * even in case of errors we still need to stop the DMAs,
263 * but we return the initial error should the DMA stop also fail
264 */
265
266 if (status < 0) {
267 dev_err(sdev->dev,
268 "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n",
269 __func__);
270 }
271
272 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_STOP);
273 if (ret < 0) {
274 dev_err(sdev->dev, "error: DMA trigger stop failed\n");
275 if (!status)
276 status = ret;
277 }
278
279 return status;
280}
281
282int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
283{
284 struct snd_sof_pdata *plat_data = sdev->pdata;
285 const struct sof_dev_desc *desc = plat_data->desc;
286 const struct sof_intel_dsp_desc *chip_info;
287 struct hdac_ext_stream *stream;
288 struct firmware stripped_firmware;
289 int ret, ret1, tag, i;
290
291 chip_info = desc->chip_info;
292
293 stripped_firmware.data = plat_data->fw->data;
294 stripped_firmware.size = plat_data->fw->size;
295
296 /* init for booting wait */
297 init_waitqueue_head(&sdev->boot_wait);
298
299 /* prepare DMA for code loader stream */
300 tag = cl_stream_prepare(sdev, 0x40, stripped_firmware.size,
301 &sdev->dmab, SNDRV_PCM_STREAM_PLAYBACK);
302
303 if (tag < 0) {
304 dev_err(sdev->dev, "error: dma prepare for fw loading err: %x\n",
305 tag);
306 return tag;
307 }
308
309 /* get stream with tag */
310 stream = get_stream_with_tag(sdev, tag);
311 if (!stream) {
312 dev_err(sdev->dev,
313 "error: could not get stream with stream tag %d\n",
314 tag);
315 ret = -ENODEV;
316 goto err;
317 }
318
319 memcpy(sdev->dmab.area, stripped_firmware.data,
320 stripped_firmware.size);
321
322 /* try ROM init a few times before giving up */
323 for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) {
324 ret = cl_dsp_init(sdev, stripped_firmware.data,
325 stripped_firmware.size, tag);
326
327 /* don't retry anymore if successful */
328 if (!ret)
329 break;
330
331 dev_dbg(sdev->dev, "iteration %d of Core En/ROM load failed: %d\n",
332 i, ret);
333 dev_dbg(sdev->dev, "Error code=0x%x: FW status=0x%x\n",
334 snd_sof_dsp_read(sdev, HDA_DSP_BAR,
335 HDA_DSP_SRAM_REG_ROM_ERROR),
336 snd_sof_dsp_read(sdev, HDA_DSP_BAR,
337 HDA_DSP_SRAM_REG_ROM_STATUS));
338 }
339
340 if (i == HDA_FW_BOOT_ATTEMPTS) {
341 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n",
342 i, ret);
343 goto cleanup;
344 }
345
346 /*
347 * at this point DSP ROM has been initialized and
348 * should be ready for code loading and firmware boot
349 */
350 ret = cl_copy_fw(sdev, stream);
351 if (!ret)
352 dev_dbg(sdev->dev, "Firmware download successful, booting...\n");
353 else
354 dev_err(sdev->dev, "error: load fw failed ret: %d\n", ret);
355
356cleanup:
357 /*
358 * Perform codeloader stream cleanup.
359 * This should be done even if firmware loading fails.
360 * If the cleanup also fails, we return the initial error
361 */
362 ret1 = cl_cleanup(sdev, &sdev->dmab, stream);
363 if (ret1 < 0) {
364 dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n");
365
366 /* set return value to indicate cleanup failure */
367 if (!ret)
368 ret = ret1;
369 }
370
371 /*
372 * return master core id if both fw copy
373 * and stream clean up are successful
374 */
375 if (!ret)
376 return chip_info->init_core_mask;
377
378 /* dump dsp registers and disable DSP upon error */
379err:
380 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
381
382 /* disable DSP */
383 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
384 SOF_HDA_REG_PP_PPCTL,
385 SOF_HDA_PPCTL_GPROCEN, 0);
386 return ret;
387}
388
389/* pre fw run operations */
390int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev)
391{
392 /* disable clock gating and power gating */
393 return hda_dsp_ctrl_clock_power_gating(sdev, false);
394}
395
396/* post fw run operations */
397int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
398{
399 /* re-enable clock gating and power gating */
400 return hda_dsp_ctrl_clock_power_gating(sdev, true);
401}