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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 *
5 */
6
7#ifndef __MTK_CMDQ_MAILBOX_H__
8#define __MTK_CMDQ_MAILBOX_H__
9
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/types.h>
13
14#define CMDQ_INST_SIZE 8 /* instruction is 64-bit */
15#define CMDQ_SUBSYS_SHIFT 16
16#define CMDQ_OP_CODE_SHIFT 24
17#define CMDQ_JUMP_PASS CMDQ_INST_SIZE
18
19#define CMDQ_WFE_UPDATE BIT(31)
20#define CMDQ_WFE_WAIT BIT(15)
21#define CMDQ_WFE_WAIT_VALUE 0x1
22
23/*
24 * WFE arg_b
25 * bit 0-11: wait value
26 * bit 15: 1 - wait, 0 - no wait
27 * bit 16-27: update value
28 * bit 31: 1 - update, 0 - no update
29 */
30#define CMDQ_WFE_OPTION (CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | \
31 CMDQ_WFE_WAIT_VALUE)
32
33/** cmdq event maximum */
34#define CMDQ_MAX_EVENT 0x3ff
35
36/*
37 * CMDQ_CODE_MASK:
38 * set write mask
39 * format: op mask
40 * CMDQ_CODE_WRITE:
41 * write value into target register
42 * format: op subsys address value
43 * CMDQ_CODE_JUMP:
44 * jump by offset
45 * format: op offset
46 * CMDQ_CODE_WFE:
47 * wait for event and clear
48 * it is just clear if no wait
49 * format: [wait] op event update:1 to_wait:1 wait:1
50 * [clear] op event update:1 to_wait:0 wait:0
51 * CMDQ_CODE_EOC:
52 * end of command
53 * format: op irq_flag
54 */
55enum cmdq_code {
56 CMDQ_CODE_MASK = 0x02,
57 CMDQ_CODE_WRITE = 0x04,
58 CMDQ_CODE_POLL = 0x08,
59 CMDQ_CODE_JUMP = 0x10,
60 CMDQ_CODE_WFE = 0x20,
61 CMDQ_CODE_EOC = 0x40,
62};
63
64enum cmdq_cb_status {
65 CMDQ_CB_NORMAL = 0,
66 CMDQ_CB_ERROR
67};
68
69struct cmdq_cb_data {
70 enum cmdq_cb_status sta;
71 void *data;
72};
73
74typedef void (*cmdq_async_flush_cb)(struct cmdq_cb_data data);
75
76struct cmdq_task_cb {
77 cmdq_async_flush_cb cb;
78 void *data;
79};
80
81struct cmdq_pkt {
82 void *va_base;
83 dma_addr_t pa_base;
84 size_t cmd_buf_size; /* command occupied size */
85 size_t buf_size; /* real buffer size */
86 struct cmdq_task_cb cb;
87 struct cmdq_task_cb async_cb;
88 void *cl;
89};
90
91#endif /* __MTK_CMDQ_MAILBOX_H__ */