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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _LINUX_CORESIGHT_H
7#define _LINUX_CORESIGHT_H
8
9#include <linux/device.h>
10#include <linux/perf_event.h>
11#include <linux/sched.h>
12
13/* Peripheral id registers (0xFD0-0xFEC) */
14#define CORESIGHT_PERIPHIDR4 0xfd0
15#define CORESIGHT_PERIPHIDR5 0xfd4
16#define CORESIGHT_PERIPHIDR6 0xfd8
17#define CORESIGHT_PERIPHIDR7 0xfdC
18#define CORESIGHT_PERIPHIDR0 0xfe0
19#define CORESIGHT_PERIPHIDR1 0xfe4
20#define CORESIGHT_PERIPHIDR2 0xfe8
21#define CORESIGHT_PERIPHIDR3 0xfeC
22/* Component id registers (0xFF0-0xFFC) */
23#define CORESIGHT_COMPIDR0 0xff0
24#define CORESIGHT_COMPIDR1 0xff4
25#define CORESIGHT_COMPIDR2 0xff8
26#define CORESIGHT_COMPIDR3 0xffC
27
28#define ETM_ARCH_V3_3 0x23
29#define ETM_ARCH_V3_5 0x25
30#define PFT_ARCH_V1_0 0x30
31#define PFT_ARCH_V1_1 0x31
32
33#define CORESIGHT_UNLOCK 0xc5acce55
34
35extern struct bus_type coresight_bustype;
36
37enum coresight_dev_type {
38 CORESIGHT_DEV_TYPE_NONE,
39 CORESIGHT_DEV_TYPE_SINK,
40 CORESIGHT_DEV_TYPE_LINK,
41 CORESIGHT_DEV_TYPE_LINKSINK,
42 CORESIGHT_DEV_TYPE_SOURCE,
43 CORESIGHT_DEV_TYPE_HELPER,
44};
45
46enum coresight_dev_subtype_sink {
47 CORESIGHT_DEV_SUBTYPE_SINK_NONE,
48 CORESIGHT_DEV_SUBTYPE_SINK_PORT,
49 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
50};
51
52enum coresight_dev_subtype_link {
53 CORESIGHT_DEV_SUBTYPE_LINK_NONE,
54 CORESIGHT_DEV_SUBTYPE_LINK_MERG,
55 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
56 CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
57};
58
59enum coresight_dev_subtype_source {
60 CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
61 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
62 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
63 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
64};
65
66enum coresight_dev_subtype_helper {
67 CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
68 CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
69};
70
71/**
72 * union coresight_dev_subtype - further characterisation of a type
73 * @sink_subtype: type of sink this component is, as defined
74 * by @coresight_dev_subtype_sink.
75 * @link_subtype: type of link this component is, as defined
76 * by @coresight_dev_subtype_link.
77 * @source_subtype: type of source this component is, as defined
78 * by @coresight_dev_subtype_source.
79 * @helper_subtype: type of helper this component is, as defined
80 * by @coresight_dev_subtype_helper.
81 */
82union coresight_dev_subtype {
83 /* We have some devices which acts as LINK and SINK */
84 struct {
85 enum coresight_dev_subtype_sink sink_subtype;
86 enum coresight_dev_subtype_link link_subtype;
87 };
88 enum coresight_dev_subtype_source source_subtype;
89 enum coresight_dev_subtype_helper helper_subtype;
90};
91
92/**
93 * struct coresight_platform_data - data harvested from the DT specification
94 * @nr_inport: number of input ports for this component.
95 * @nr_outport: number of output ports for this component.
96 * @conns: Array of nr_outport connections from this component
97 */
98struct coresight_platform_data {
99 int nr_inport;
100 int nr_outport;
101 struct coresight_connection *conns;
102};
103
104/**
105 * struct coresight_desc - description of a component required from drivers
106 * @type: as defined by @coresight_dev_type.
107 * @subtype: as defined by @coresight_dev_subtype.
108 * @ops: generic operations for this component, as defined
109 * by @coresight_ops.
110 * @pdata: platform data collected from DT.
111 * @dev: The device entity associated to this component.
112 * @groups: operations specific to this component. These will end up
113 * in the component's sysfs sub-directory.
114 * @name: name for the coresight device, also shown under sysfs.
115 */
116struct coresight_desc {
117 enum coresight_dev_type type;
118 union coresight_dev_subtype subtype;
119 const struct coresight_ops *ops;
120 struct coresight_platform_data *pdata;
121 struct device *dev;
122 const struct attribute_group **groups;
123 const char *name;
124};
125
126/**
127 * struct coresight_connection - representation of a single connection
128 * @outport: a connection's output port number.
129 * @child_port: remote component's port number @output is connected to.
130 * @chid_fwnode: remote component's fwnode handle.
131 * @child_dev: a @coresight_device representation of the component
132 connected to @outport.
133 */
134struct coresight_connection {
135 int outport;
136 int child_port;
137 struct fwnode_handle *child_fwnode;
138 struct coresight_device *child_dev;
139};
140
141/**
142 * struct coresight_device - representation of a device as used by the framework
143 * @pdata: Platform data with device connections associated to this device.
144 * @type: as defined by @coresight_dev_type.
145 * @subtype: as defined by @coresight_dev_subtype.
146 * @ops: generic operations for this component, as defined
147 by @coresight_ops.
148 * @dev: The device entity associated to this component.
149 * @refcnt: keep track of what is in use.
150 * @orphan: true if the component has connections that haven't been linked.
151 * @enable: 'true' if component is currently part of an active path.
152 * @activated: 'true' only if a _sink_ has been activated. A sink can be
153 * activated but not yet enabled. Enabling for a _sink_
154 * appens when a source has been selected for that it.
155 * @ea: Device attribute for sink representation under PMU directory.
156 */
157struct coresight_device {
158 struct coresight_platform_data *pdata;
159 enum coresight_dev_type type;
160 union coresight_dev_subtype subtype;
161 const struct coresight_ops *ops;
162 struct device dev;
163 atomic_t *refcnt;
164 bool orphan;
165 bool enable; /* true only if configured as part of a path */
166 /* sink specific fields */
167 bool activated; /* true only if a sink is part of a path */
168 struct dev_ext_attribute *ea;
169};
170
171/*
172 * coresight_dev_list - Mapping for devices to "name" index for device
173 * names.
174 *
175 * @nr_idx: Number of entries already allocated.
176 * @pfx: Prefix pattern for device name.
177 * @fwnode_list: Array of fwnode_handles associated with each allocated
178 * index, upto nr_idx entries.
179 */
180struct coresight_dev_list {
181 int nr_idx;
182 const char *pfx;
183 struct fwnode_handle **fwnode_list;
184};
185
186#define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \
187static struct coresight_dev_list (var) = { \
188 .pfx = dev_pfx, \
189 .nr_idx = 0, \
190 .fwnode_list = NULL, \
191}
192
193#define to_coresight_device(d) container_of(d, struct coresight_device, dev)
194
195#define source_ops(csdev) csdev->ops->source_ops
196#define sink_ops(csdev) csdev->ops->sink_ops
197#define link_ops(csdev) csdev->ops->link_ops
198#define helper_ops(csdev) csdev->ops->helper_ops
199
200/**
201 * struct coresight_ops_sink - basic operations for a sink
202 * Operations available for sinks
203 * @enable: enables the sink.
204 * @disable: disables the sink.
205 * @alloc_buffer: initialises perf's ring buffer for trace collection.
206 * @free_buffer: release memory allocated in @get_config.
207 * @update_buffer: update buffer pointers after a trace session.
208 */
209struct coresight_ops_sink {
210 int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
211 int (*disable)(struct coresight_device *csdev);
212 void *(*alloc_buffer)(struct coresight_device *csdev,
213 struct perf_event *event, void **pages,
214 int nr_pages, bool overwrite);
215 void (*free_buffer)(void *config);
216 unsigned long (*update_buffer)(struct coresight_device *csdev,
217 struct perf_output_handle *handle,
218 void *sink_config);
219};
220
221/**
222 * struct coresight_ops_link - basic operations for a link
223 * Operations available for links.
224 * @enable: enables flow between iport and oport.
225 * @disable: disables flow between iport and oport.
226 */
227struct coresight_ops_link {
228 int (*enable)(struct coresight_device *csdev, int iport, int oport);
229 void (*disable)(struct coresight_device *csdev, int iport, int oport);
230};
231
232/**
233 * struct coresight_ops_source - basic operations for a source
234 * Operations available for sources.
235 * @cpu_id: returns the value of the CPU number this component
236 * is associated to.
237 * @trace_id: returns the value of the component's trace ID as known
238 * to the HW.
239 * @enable: enables tracing for a source.
240 * @disable: disables tracing for a source.
241 */
242struct coresight_ops_source {
243 int (*cpu_id)(struct coresight_device *csdev);
244 int (*trace_id)(struct coresight_device *csdev);
245 int (*enable)(struct coresight_device *csdev,
246 struct perf_event *event, u32 mode);
247 void (*disable)(struct coresight_device *csdev,
248 struct perf_event *event);
249};
250
251/**
252 * struct coresight_ops_helper - Operations for a helper device.
253 *
254 * All operations could pass in a device specific data, which could
255 * help the helper device to determine what to do.
256 *
257 * @enable : Enable the device
258 * @disable : Disable the device
259 */
260struct coresight_ops_helper {
261 int (*enable)(struct coresight_device *csdev, void *data);
262 int (*disable)(struct coresight_device *csdev, void *data);
263};
264
265struct coresight_ops {
266 const struct coresight_ops_sink *sink_ops;
267 const struct coresight_ops_link *link_ops;
268 const struct coresight_ops_source *source_ops;
269 const struct coresight_ops_helper *helper_ops;
270};
271
272#ifdef CONFIG_CORESIGHT
273extern struct coresight_device *
274coresight_register(struct coresight_desc *desc);
275extern void coresight_unregister(struct coresight_device *csdev);
276extern int coresight_enable(struct coresight_device *csdev);
277extern void coresight_disable(struct coresight_device *csdev);
278extern int coresight_timeout(void __iomem *addr, u32 offset,
279 int position, int value);
280
281extern int coresight_claim_device(void __iomem *base);
282extern int coresight_claim_device_unlocked(void __iomem *base);
283
284extern void coresight_disclaim_device(void __iomem *base);
285extern void coresight_disclaim_device_unlocked(void __iomem *base);
286extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
287 struct device *dev);
288
289extern bool coresight_loses_context_with_cpu(struct device *dev);
290#else
291static inline struct coresight_device *
292coresight_register(struct coresight_desc *desc) { return NULL; }
293static inline void coresight_unregister(struct coresight_device *csdev) {}
294static inline int
295coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
296static inline void coresight_disable(struct coresight_device *csdev) {}
297static inline int coresight_timeout(void __iomem *addr, u32 offset,
298 int position, int value) { return 1; }
299static inline int coresight_claim_device_unlocked(void __iomem *base)
300{
301 return -EINVAL;
302}
303
304static inline int coresight_claim_device(void __iomem *base)
305{
306 return -EINVAL;
307}
308
309static inline void coresight_disclaim_device(void __iomem *base) {}
310static inline void coresight_disclaim_device_unlocked(void __iomem *base) {}
311
312static inline bool coresight_loses_context_with_cpu(struct device *dev)
313{
314 return false;
315}
316#endif
317
318extern int coresight_get_cpu(struct device *dev);
319
320struct coresight_platform_data *coresight_get_platform_data(struct device *dev);
321
322#endif