Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * core.c - ChipIdea USB IP core family device controller
4 *
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6 *
7 * Author: David Lopo
8 */
9
10/*
11 * Description: ChipIdea USB IP core family device controller
12 *
13 * This driver is composed of several blocks:
14 * - HW: hardware interface
15 * - DBG: debug facilities (optional)
16 * - UTIL: utilities
17 * - ISR: interrupts handling
18 * - ENDPT: endpoint operations (Gadget API)
19 * - GADGET: gadget operations (Gadget API)
20 * - BUS: bus glue code, bus abstraction layer
21 *
22 * Compile Options
23 * - STALL_IN: non-empty bulk-in pipes cannot be halted
24 * if defined mass storage compliance succeeds but with warnings
25 * => case 4: Hi > Dn
26 * => case 5: Hi > Di
27 * => case 8: Hi <> Do
28 * if undefined usbtest 13 fails
29 * - TRACE: enable function tracing (depends on DEBUG)
30 *
31 * Main Features
32 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
33 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
34 * - Normal & LPM support
35 *
36 * USBTEST Report
37 * - OK: 0-12, 13 (STALL_IN defined) & 14
38 * - Not Supported: 15 & 16 (ISO)
39 *
40 * TODO List
41 * - Suspend & Remote Wakeup
42 */
43#include <linux/delay.h>
44#include <linux/device.h>
45#include <linux/dma-mapping.h>
46#include <linux/extcon.h>
47#include <linux/phy/phy.h>
48#include <linux/platform_device.h>
49#include <linux/module.h>
50#include <linux/idr.h>
51#include <linux/interrupt.h>
52#include <linux/io.h>
53#include <linux/kernel.h>
54#include <linux/slab.h>
55#include <linux/pm_runtime.h>
56#include <linux/pinctrl/consumer.h>
57#include <linux/usb/ch9.h>
58#include <linux/usb/gadget.h>
59#include <linux/usb/otg.h>
60#include <linux/usb/chipidea.h>
61#include <linux/usb/of.h>
62#include <linux/of.h>
63#include <linux/regulator/consumer.h>
64#include <linux/usb/ehci_def.h>
65
66#include "ci.h"
67#include "udc.h"
68#include "bits.h"
69#include "host.h"
70#include "otg.h"
71#include "otg_fsm.h"
72
73/* Controller register map */
74static const u8 ci_regs_nolpm[] = {
75 [CAP_CAPLENGTH] = 0x00U,
76 [CAP_HCCPARAMS] = 0x08U,
77 [CAP_DCCPARAMS] = 0x24U,
78 [CAP_TESTMODE] = 0x38U,
79 [OP_USBCMD] = 0x00U,
80 [OP_USBSTS] = 0x04U,
81 [OP_USBINTR] = 0x08U,
82 [OP_DEVICEADDR] = 0x14U,
83 [OP_ENDPTLISTADDR] = 0x18U,
84 [OP_TTCTRL] = 0x1CU,
85 [OP_BURSTSIZE] = 0x20U,
86 [OP_ULPI_VIEWPORT] = 0x30U,
87 [OP_PORTSC] = 0x44U,
88 [OP_DEVLC] = 0x84U,
89 [OP_OTGSC] = 0x64U,
90 [OP_USBMODE] = 0x68U,
91 [OP_ENDPTSETUPSTAT] = 0x6CU,
92 [OP_ENDPTPRIME] = 0x70U,
93 [OP_ENDPTFLUSH] = 0x74U,
94 [OP_ENDPTSTAT] = 0x78U,
95 [OP_ENDPTCOMPLETE] = 0x7CU,
96 [OP_ENDPTCTRL] = 0x80U,
97};
98
99static const u8 ci_regs_lpm[] = {
100 [CAP_CAPLENGTH] = 0x00U,
101 [CAP_HCCPARAMS] = 0x08U,
102 [CAP_DCCPARAMS] = 0x24U,
103 [CAP_TESTMODE] = 0xFCU,
104 [OP_USBCMD] = 0x00U,
105 [OP_USBSTS] = 0x04U,
106 [OP_USBINTR] = 0x08U,
107 [OP_DEVICEADDR] = 0x14U,
108 [OP_ENDPTLISTADDR] = 0x18U,
109 [OP_TTCTRL] = 0x1CU,
110 [OP_BURSTSIZE] = 0x20U,
111 [OP_ULPI_VIEWPORT] = 0x30U,
112 [OP_PORTSC] = 0x44U,
113 [OP_DEVLC] = 0x84U,
114 [OP_OTGSC] = 0xC4U,
115 [OP_USBMODE] = 0xC8U,
116 [OP_ENDPTSETUPSTAT] = 0xD8U,
117 [OP_ENDPTPRIME] = 0xDCU,
118 [OP_ENDPTFLUSH] = 0xE0U,
119 [OP_ENDPTSTAT] = 0xE4U,
120 [OP_ENDPTCOMPLETE] = 0xE8U,
121 [OP_ENDPTCTRL] = 0xECU,
122};
123
124static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
125{
126 int i;
127
128 for (i = 0; i < OP_ENDPTCTRL; i++)
129 ci->hw_bank.regmap[i] =
130 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
131 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
132
133 for (; i <= OP_LAST; i++)
134 ci->hw_bank.regmap[i] = ci->hw_bank.op +
135 4 * (i - OP_ENDPTCTRL) +
136 (is_lpm
137 ? ci_regs_lpm[OP_ENDPTCTRL]
138 : ci_regs_nolpm[OP_ENDPTCTRL]);
139
140}
141
142static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
143{
144 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
145 enum ci_revision rev = CI_REVISION_UNKNOWN;
146
147 if (ver == 0x2) {
148 rev = hw_read_id_reg(ci, ID_ID, REVISION)
149 >> __ffs(REVISION);
150 rev += CI_REVISION_20;
151 } else if (ver == 0x0) {
152 rev = CI_REVISION_1X;
153 }
154
155 return rev;
156}
157
158/**
159 * hw_read_intr_enable: returns interrupt enable register
160 *
161 * @ci: the controller
162 *
163 * This function returns register data
164 */
165u32 hw_read_intr_enable(struct ci_hdrc *ci)
166{
167 return hw_read(ci, OP_USBINTR, ~0);
168}
169
170/**
171 * hw_read_intr_status: returns interrupt status register
172 *
173 * @ci: the controller
174 *
175 * This function returns register data
176 */
177u32 hw_read_intr_status(struct ci_hdrc *ci)
178{
179 return hw_read(ci, OP_USBSTS, ~0);
180}
181
182/**
183 * hw_port_test_set: writes port test mode (execute without interruption)
184 * @mode: new value
185 *
186 * This function returns an error code
187 */
188int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
189{
190 const u8 TEST_MODE_MAX = 7;
191
192 if (mode > TEST_MODE_MAX)
193 return -EINVAL;
194
195 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
196 return 0;
197}
198
199/**
200 * hw_port_test_get: reads port test mode value
201 *
202 * @ci: the controller
203 *
204 * This function returns port test mode value
205 */
206u8 hw_port_test_get(struct ci_hdrc *ci)
207{
208 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
209}
210
211static void hw_wait_phy_stable(void)
212{
213 /*
214 * The phy needs some delay to output the stable status from low
215 * power mode. And for OTGSC, the status inputs are debounced
216 * using a 1 ms time constant, so, delay 2ms for controller to get
217 * the stable status, like vbus and id when the phy leaves low power.
218 */
219 usleep_range(2000, 2500);
220}
221
222/* The PHY enters/leaves low power mode */
223static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
224{
225 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
226 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
227
228 if (enable && !lpm)
229 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
230 PORTSC_PHCD(ci->hw_bank.lpm));
231 else if (!enable && lpm)
232 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
233 0);
234}
235
236static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
237{
238 u32 reg;
239
240 /* bank is a module variable */
241 ci->hw_bank.abs = base;
242
243 ci->hw_bank.cap = ci->hw_bank.abs;
244 ci->hw_bank.cap += ci->platdata->capoffset;
245 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
246
247 hw_alloc_regmap(ci, false);
248 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
249 __ffs(HCCPARAMS_LEN);
250 ci->hw_bank.lpm = reg;
251 if (reg)
252 hw_alloc_regmap(ci, !!reg);
253 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
254 ci->hw_bank.size += OP_LAST;
255 ci->hw_bank.size /= sizeof(u32);
256
257 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
258 __ffs(DCCPARAMS_DEN);
259 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
260
261 if (ci->hw_ep_max > ENDPT_MAX)
262 return -ENODEV;
263
264 ci_hdrc_enter_lpm(ci, false);
265
266 /* Disable all interrupts bits */
267 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
268
269 /* Clear all interrupts status bits*/
270 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
271
272 ci->rev = ci_get_revision(ci);
273
274 dev_dbg(ci->dev,
275 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
276 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
277
278 /* setup lock mode ? */
279
280 /* ENDPTSETUPSTAT is '0' by default */
281
282 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
283
284 return 0;
285}
286
287void hw_phymode_configure(struct ci_hdrc *ci)
288{
289 u32 portsc, lpm, sts = 0;
290
291 switch (ci->platdata->phy_mode) {
292 case USBPHY_INTERFACE_MODE_UTMI:
293 portsc = PORTSC_PTS(PTS_UTMI);
294 lpm = DEVLC_PTS(PTS_UTMI);
295 break;
296 case USBPHY_INTERFACE_MODE_UTMIW:
297 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
298 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
299 break;
300 case USBPHY_INTERFACE_MODE_ULPI:
301 portsc = PORTSC_PTS(PTS_ULPI);
302 lpm = DEVLC_PTS(PTS_ULPI);
303 break;
304 case USBPHY_INTERFACE_MODE_SERIAL:
305 portsc = PORTSC_PTS(PTS_SERIAL);
306 lpm = DEVLC_PTS(PTS_SERIAL);
307 sts = 1;
308 break;
309 case USBPHY_INTERFACE_MODE_HSIC:
310 portsc = PORTSC_PTS(PTS_HSIC);
311 lpm = DEVLC_PTS(PTS_HSIC);
312 break;
313 default:
314 return;
315 }
316
317 if (ci->hw_bank.lpm) {
318 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
319 if (sts)
320 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
321 } else {
322 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
323 if (sts)
324 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
325 }
326}
327EXPORT_SYMBOL_GPL(hw_phymode_configure);
328
329/**
330 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
331 * interfaces
332 * @ci: the controller
333 *
334 * This function returns an error code if the phy failed to init
335 */
336static int _ci_usb_phy_init(struct ci_hdrc *ci)
337{
338 int ret;
339
340 if (ci->phy) {
341 ret = phy_init(ci->phy);
342 if (ret)
343 return ret;
344
345 ret = phy_power_on(ci->phy);
346 if (ret) {
347 phy_exit(ci->phy);
348 return ret;
349 }
350 } else {
351 ret = usb_phy_init(ci->usb_phy);
352 }
353
354 return ret;
355}
356
357/**
358 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
359 * interfaces
360 * @ci: the controller
361 */
362static void ci_usb_phy_exit(struct ci_hdrc *ci)
363{
364 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
365 return;
366
367 if (ci->phy) {
368 phy_power_off(ci->phy);
369 phy_exit(ci->phy);
370 } else {
371 usb_phy_shutdown(ci->usb_phy);
372 }
373}
374
375/**
376 * ci_usb_phy_init: initialize phy according to different phy type
377 * @ci: the controller
378 *
379 * This function returns an error code if usb_phy_init has failed
380 */
381static int ci_usb_phy_init(struct ci_hdrc *ci)
382{
383 int ret;
384
385 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
386 return 0;
387
388 switch (ci->platdata->phy_mode) {
389 case USBPHY_INTERFACE_MODE_UTMI:
390 case USBPHY_INTERFACE_MODE_UTMIW:
391 case USBPHY_INTERFACE_MODE_HSIC:
392 ret = _ci_usb_phy_init(ci);
393 if (!ret)
394 hw_wait_phy_stable();
395 else
396 return ret;
397 hw_phymode_configure(ci);
398 break;
399 case USBPHY_INTERFACE_MODE_ULPI:
400 case USBPHY_INTERFACE_MODE_SERIAL:
401 hw_phymode_configure(ci);
402 ret = _ci_usb_phy_init(ci);
403 if (ret)
404 return ret;
405 break;
406 default:
407 ret = _ci_usb_phy_init(ci);
408 if (!ret)
409 hw_wait_phy_stable();
410 }
411
412 return ret;
413}
414
415
416/**
417 * ci_platform_configure: do controller configure
418 * @ci: the controller
419 *
420 */
421void ci_platform_configure(struct ci_hdrc *ci)
422{
423 bool is_device_mode, is_host_mode;
424
425 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
426 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
427
428 if (is_device_mode) {
429 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
430
431 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
432 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
433 USBMODE_CI_SDIS);
434 }
435
436 if (is_host_mode) {
437 phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
438
439 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
440 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
441 USBMODE_CI_SDIS);
442 }
443
444 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
445 if (ci->hw_bank.lpm)
446 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
447 else
448 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
449 }
450
451 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
452 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
453
454 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
455
456 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
457 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
458 ci->platdata->ahb_burst_config);
459
460 /* override burst size, take effect only when ahb_burst_config is 0 */
461 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
462 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
463 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
464 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
465
466 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
467 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
468 ci->platdata->rx_burst_size);
469 }
470}
471
472/**
473 * hw_controller_reset: do controller reset
474 * @ci: the controller
475 *
476 * This function returns an error code
477 */
478static int hw_controller_reset(struct ci_hdrc *ci)
479{
480 int count = 0;
481
482 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
483 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
484 udelay(10);
485 if (count++ > 1000)
486 return -ETIMEDOUT;
487 }
488
489 return 0;
490}
491
492/**
493 * hw_device_reset: resets chip (execute without interruption)
494 * @ci: the controller
495 *
496 * This function returns an error code
497 */
498int hw_device_reset(struct ci_hdrc *ci)
499{
500 int ret;
501
502 /* should flush & stop before reset */
503 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
504 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
505
506 ret = hw_controller_reset(ci);
507 if (ret) {
508 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
509 return ret;
510 }
511
512 if (ci->platdata->notify_event) {
513 ret = ci->platdata->notify_event(ci,
514 CI_HDRC_CONTROLLER_RESET_EVENT);
515 if (ret)
516 return ret;
517 }
518
519 /* USBMODE should be configured step by step */
520 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
521 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
522 /* HW >= 2.3 */
523 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
524
525 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
526 dev_err(ci->dev, "cannot enter in %s device mode\n",
527 ci_role(ci)->name);
528 dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm);
529 return -ENODEV;
530 }
531
532 ci_platform_configure(ci);
533
534 return 0;
535}
536
537static irqreturn_t ci_irq(int irq, void *data)
538{
539 struct ci_hdrc *ci = data;
540 irqreturn_t ret = IRQ_NONE;
541 u32 otgsc = 0;
542
543 if (ci->in_lpm) {
544 disable_irq_nosync(irq);
545 ci->wakeup_int = true;
546 pm_runtime_get(ci->dev);
547 return IRQ_HANDLED;
548 }
549
550 if (ci->is_otg) {
551 otgsc = hw_read_otgsc(ci, ~0);
552 if (ci_otg_is_fsm_mode(ci)) {
553 ret = ci_otg_fsm_irq(ci);
554 if (ret == IRQ_HANDLED)
555 return ret;
556 }
557 }
558
559 /*
560 * Handle id change interrupt, it indicates device/host function
561 * switch.
562 */
563 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
564 ci->id_event = true;
565 /* Clear ID change irq status */
566 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
567 ci_otg_queue_work(ci);
568 return IRQ_HANDLED;
569 }
570
571 /*
572 * Handle vbus change interrupt, it indicates device connection
573 * and disconnection events.
574 */
575 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
576 ci->b_sess_valid_event = true;
577 /* Clear BSV irq */
578 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
579 ci_otg_queue_work(ci);
580 return IRQ_HANDLED;
581 }
582
583 /* Handle device/host interrupt */
584 if (ci->role != CI_ROLE_END)
585 ret = ci_role(ci)->irq(ci);
586
587 return ret;
588}
589
590static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
591 void *ptr)
592{
593 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
594 struct ci_hdrc *ci = cbl->ci;
595
596 cbl->connected = event;
597 cbl->changed = true;
598
599 ci_irq(ci->irq, ci);
600 return NOTIFY_DONE;
601}
602
603static enum usb_role ci_usb_role_switch_get(struct device *dev)
604{
605 struct ci_hdrc *ci = dev_get_drvdata(dev);
606 enum usb_role role;
607 unsigned long flags;
608
609 spin_lock_irqsave(&ci->lock, flags);
610 role = ci_role_to_usb_role(ci);
611 spin_unlock_irqrestore(&ci->lock, flags);
612
613 return role;
614}
615
616static int ci_usb_role_switch_set(struct device *dev, enum usb_role role)
617{
618 struct ci_hdrc *ci = dev_get_drvdata(dev);
619 struct ci_hdrc_cable *cable = NULL;
620 enum usb_role current_role = ci_role_to_usb_role(ci);
621 enum ci_role ci_role = usb_role_to_ci_role(role);
622 unsigned long flags;
623
624 if ((ci_role != CI_ROLE_END && !ci->roles[ci_role]) ||
625 (current_role == role))
626 return 0;
627
628 pm_runtime_get_sync(ci->dev);
629 /* Stop current role */
630 spin_lock_irqsave(&ci->lock, flags);
631 if (current_role == USB_ROLE_DEVICE)
632 cable = &ci->platdata->vbus_extcon;
633 else if (current_role == USB_ROLE_HOST)
634 cable = &ci->platdata->id_extcon;
635
636 if (cable) {
637 cable->changed = true;
638 cable->connected = false;
639 ci_irq(ci->irq, ci);
640 spin_unlock_irqrestore(&ci->lock, flags);
641 if (ci->wq && role != USB_ROLE_NONE)
642 flush_workqueue(ci->wq);
643 spin_lock_irqsave(&ci->lock, flags);
644 }
645
646 cable = NULL;
647
648 /* Start target role */
649 if (role == USB_ROLE_DEVICE)
650 cable = &ci->platdata->vbus_extcon;
651 else if (role == USB_ROLE_HOST)
652 cable = &ci->platdata->id_extcon;
653
654 if (cable) {
655 cable->changed = true;
656 cable->connected = true;
657 ci_irq(ci->irq, ci);
658 }
659 spin_unlock_irqrestore(&ci->lock, flags);
660 pm_runtime_put_sync(ci->dev);
661
662 return 0;
663}
664
665static struct usb_role_switch_desc ci_role_switch = {
666 .set = ci_usb_role_switch_set,
667 .get = ci_usb_role_switch_get,
668};
669
670static int ci_get_platdata(struct device *dev,
671 struct ci_hdrc_platform_data *platdata)
672{
673 struct extcon_dev *ext_vbus, *ext_id;
674 struct ci_hdrc_cable *cable;
675 int ret;
676
677 if (!platdata->phy_mode)
678 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
679
680 if (!platdata->dr_mode)
681 platdata->dr_mode = usb_get_dr_mode(dev);
682
683 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
684 platdata->dr_mode = USB_DR_MODE_OTG;
685
686 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
687 /* Get the vbus regulator */
688 platdata->reg_vbus = devm_regulator_get_optional(dev, "vbus");
689 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
690 return -EPROBE_DEFER;
691 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
692 /* no vbus regulator is needed */
693 platdata->reg_vbus = NULL;
694 } else if (IS_ERR(platdata->reg_vbus)) {
695 dev_err(dev, "Getting regulator error: %ld\n",
696 PTR_ERR(platdata->reg_vbus));
697 return PTR_ERR(platdata->reg_vbus);
698 }
699 /* Get TPL support */
700 if (!platdata->tpl_support)
701 platdata->tpl_support =
702 of_usb_host_tpl_support(dev->of_node);
703 }
704
705 if (platdata->dr_mode == USB_DR_MODE_OTG) {
706 /* We can support HNP and SRP of OTG 2.0 */
707 platdata->ci_otg_caps.otg_rev = 0x0200;
708 platdata->ci_otg_caps.hnp_support = true;
709 platdata->ci_otg_caps.srp_support = true;
710
711 /* Update otg capabilities by DT properties */
712 ret = of_usb_update_otg_caps(dev->of_node,
713 &platdata->ci_otg_caps);
714 if (ret)
715 return ret;
716 }
717
718 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
719 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
720
721 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
722 &platdata->phy_clkgate_delay_us);
723
724 platdata->itc_setting = 1;
725
726 of_property_read_u32(dev->of_node, "itc-setting",
727 &platdata->itc_setting);
728
729 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
730 &platdata->ahb_burst_config);
731 if (!ret) {
732 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
733 } else if (ret != -EINVAL) {
734 dev_err(dev, "failed to get ahb-burst-config\n");
735 return ret;
736 }
737
738 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
739 &platdata->tx_burst_size);
740 if (!ret) {
741 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
742 } else if (ret != -EINVAL) {
743 dev_err(dev, "failed to get tx-burst-size-dword\n");
744 return ret;
745 }
746
747 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
748 &platdata->rx_burst_size);
749 if (!ret) {
750 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
751 } else if (ret != -EINVAL) {
752 dev_err(dev, "failed to get rx-burst-size-dword\n");
753 return ret;
754 }
755
756 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
757 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
758
759 ext_id = ERR_PTR(-ENODEV);
760 ext_vbus = ERR_PTR(-ENODEV);
761 if (of_property_read_bool(dev->of_node, "extcon")) {
762 /* Each one of them is not mandatory */
763 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
764 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
765 return PTR_ERR(ext_vbus);
766
767 ext_id = extcon_get_edev_by_phandle(dev, 1);
768 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
769 return PTR_ERR(ext_id);
770 }
771
772 cable = &platdata->vbus_extcon;
773 cable->nb.notifier_call = ci_cable_notifier;
774 cable->edev = ext_vbus;
775
776 if (!IS_ERR(ext_vbus)) {
777 ret = extcon_get_state(cable->edev, EXTCON_USB);
778 if (ret)
779 cable->connected = true;
780 else
781 cable->connected = false;
782 }
783
784 cable = &platdata->id_extcon;
785 cable->nb.notifier_call = ci_cable_notifier;
786 cable->edev = ext_id;
787
788 if (!IS_ERR(ext_id)) {
789 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
790 if (ret)
791 cable->connected = true;
792 else
793 cable->connected = false;
794 }
795
796 if (device_property_read_bool(dev, "usb-role-switch"))
797 ci_role_switch.fwnode = dev->fwnode;
798
799 platdata->pctl = devm_pinctrl_get(dev);
800 if (!IS_ERR(platdata->pctl)) {
801 struct pinctrl_state *p;
802
803 p = pinctrl_lookup_state(platdata->pctl, "default");
804 if (!IS_ERR(p))
805 platdata->pins_default = p;
806
807 p = pinctrl_lookup_state(platdata->pctl, "host");
808 if (!IS_ERR(p))
809 platdata->pins_host = p;
810
811 p = pinctrl_lookup_state(platdata->pctl, "device");
812 if (!IS_ERR(p))
813 platdata->pins_device = p;
814 }
815
816 return 0;
817}
818
819static int ci_extcon_register(struct ci_hdrc *ci)
820{
821 struct ci_hdrc_cable *id, *vbus;
822 int ret;
823
824 id = &ci->platdata->id_extcon;
825 id->ci = ci;
826 if (!IS_ERR_OR_NULL(id->edev)) {
827 ret = devm_extcon_register_notifier(ci->dev, id->edev,
828 EXTCON_USB_HOST, &id->nb);
829 if (ret < 0) {
830 dev_err(ci->dev, "register ID failed\n");
831 return ret;
832 }
833 }
834
835 vbus = &ci->platdata->vbus_extcon;
836 vbus->ci = ci;
837 if (!IS_ERR_OR_NULL(vbus->edev)) {
838 ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
839 EXTCON_USB, &vbus->nb);
840 if (ret < 0) {
841 dev_err(ci->dev, "register VBUS failed\n");
842 return ret;
843 }
844 }
845
846 return 0;
847}
848
849static DEFINE_IDA(ci_ida);
850
851struct platform_device *ci_hdrc_add_device(struct device *dev,
852 struct resource *res, int nres,
853 struct ci_hdrc_platform_data *platdata)
854{
855 struct platform_device *pdev;
856 int id, ret;
857
858 ret = ci_get_platdata(dev, platdata);
859 if (ret)
860 return ERR_PTR(ret);
861
862 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
863 if (id < 0)
864 return ERR_PTR(id);
865
866 pdev = platform_device_alloc("ci_hdrc", id);
867 if (!pdev) {
868 ret = -ENOMEM;
869 goto put_id;
870 }
871
872 pdev->dev.parent = dev;
873
874 ret = platform_device_add_resources(pdev, res, nres);
875 if (ret)
876 goto err;
877
878 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
879 if (ret)
880 goto err;
881
882 ret = platform_device_add(pdev);
883 if (ret)
884 goto err;
885
886 return pdev;
887
888err:
889 platform_device_put(pdev);
890put_id:
891 ida_simple_remove(&ci_ida, id);
892 return ERR_PTR(ret);
893}
894EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
895
896void ci_hdrc_remove_device(struct platform_device *pdev)
897{
898 int id = pdev->id;
899 platform_device_unregister(pdev);
900 ida_simple_remove(&ci_ida, id);
901}
902EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
903
904static inline void ci_role_destroy(struct ci_hdrc *ci)
905{
906 ci_hdrc_gadget_destroy(ci);
907 ci_hdrc_host_destroy(ci);
908 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
909 ci_hdrc_otg_destroy(ci);
910}
911
912static void ci_get_otg_capable(struct ci_hdrc *ci)
913{
914 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
915 ci->is_otg = false;
916 else
917 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
918 DCCPARAMS_DC | DCCPARAMS_HC)
919 == (DCCPARAMS_DC | DCCPARAMS_HC));
920 if (ci->is_otg) {
921 dev_dbg(ci->dev, "It is OTG capable controller\n");
922 /* Disable and clear all OTG irq */
923 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
924 OTGSC_INT_STATUS_BITS);
925 }
926}
927
928static ssize_t role_show(struct device *dev, struct device_attribute *attr,
929 char *buf)
930{
931 struct ci_hdrc *ci = dev_get_drvdata(dev);
932
933 if (ci->role != CI_ROLE_END)
934 return sprintf(buf, "%s\n", ci_role(ci)->name);
935
936 return 0;
937}
938
939static ssize_t role_store(struct device *dev,
940 struct device_attribute *attr, const char *buf, size_t n)
941{
942 struct ci_hdrc *ci = dev_get_drvdata(dev);
943 enum ci_role role;
944 int ret;
945
946 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
947 dev_warn(dev, "Current configuration is not dual-role, quit\n");
948 return -EPERM;
949 }
950
951 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
952 if (!strncmp(buf, ci->roles[role]->name,
953 strlen(ci->roles[role]->name)))
954 break;
955
956 if (role == CI_ROLE_END || role == ci->role)
957 return -EINVAL;
958
959 pm_runtime_get_sync(dev);
960 disable_irq(ci->irq);
961 ci_role_stop(ci);
962 ret = ci_role_start(ci, role);
963 if (!ret && ci->role == CI_ROLE_GADGET)
964 ci_handle_vbus_change(ci);
965 enable_irq(ci->irq);
966 pm_runtime_put_sync(dev);
967
968 return (ret == 0) ? n : ret;
969}
970static DEVICE_ATTR_RW(role);
971
972static struct attribute *ci_attrs[] = {
973 &dev_attr_role.attr,
974 NULL,
975};
976ATTRIBUTE_GROUPS(ci);
977
978static int ci_hdrc_probe(struct platform_device *pdev)
979{
980 struct device *dev = &pdev->dev;
981 struct ci_hdrc *ci;
982 struct resource *res;
983 void __iomem *base;
984 int ret;
985 enum usb_dr_mode dr_mode;
986
987 if (!dev_get_platdata(dev)) {
988 dev_err(dev, "platform data missing\n");
989 return -ENODEV;
990 }
991
992 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
993 base = devm_ioremap_resource(dev, res);
994 if (IS_ERR(base))
995 return PTR_ERR(base);
996
997 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
998 if (!ci)
999 return -ENOMEM;
1000
1001 spin_lock_init(&ci->lock);
1002 ci->dev = dev;
1003 ci->platdata = dev_get_platdata(dev);
1004 ci->imx28_write_fix = !!(ci->platdata->flags &
1005 CI_HDRC_IMX28_WRITE_FIX);
1006 ci->supports_runtime_pm = !!(ci->platdata->flags &
1007 CI_HDRC_SUPPORTS_RUNTIME_PM);
1008 platform_set_drvdata(pdev, ci);
1009
1010 ret = hw_device_init(ci, base);
1011 if (ret < 0) {
1012 dev_err(dev, "can't initialize hardware\n");
1013 return -ENODEV;
1014 }
1015
1016 ret = ci_ulpi_init(ci);
1017 if (ret)
1018 return ret;
1019
1020 if (ci->platdata->phy) {
1021 ci->phy = ci->platdata->phy;
1022 } else if (ci->platdata->usb_phy) {
1023 ci->usb_phy = ci->platdata->usb_phy;
1024 } else {
1025 /* Look for a generic PHY first */
1026 ci->phy = devm_phy_get(dev->parent, "usb-phy");
1027
1028 if (PTR_ERR(ci->phy) == -EPROBE_DEFER) {
1029 ret = -EPROBE_DEFER;
1030 goto ulpi_exit;
1031 } else if (IS_ERR(ci->phy)) {
1032 ci->phy = NULL;
1033 }
1034
1035 /* Look for a legacy USB PHY from device-tree next */
1036 if (!ci->phy) {
1037 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent,
1038 "phys", 0);
1039
1040 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1041 ret = -EPROBE_DEFER;
1042 goto ulpi_exit;
1043 } else if (IS_ERR(ci->usb_phy)) {
1044 ci->usb_phy = NULL;
1045 }
1046 }
1047
1048 /* Look for any registered legacy USB PHY as last resort */
1049 if (!ci->phy && !ci->usb_phy) {
1050 ci->usb_phy = devm_usb_get_phy(dev->parent,
1051 USB_PHY_TYPE_USB2);
1052
1053 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1054 ret = -EPROBE_DEFER;
1055 goto ulpi_exit;
1056 } else if (IS_ERR(ci->usb_phy)) {
1057 ci->usb_phy = NULL;
1058 }
1059 }
1060
1061 /* No USB PHY was found in the end */
1062 if (!ci->phy && !ci->usb_phy) {
1063 ret = -ENXIO;
1064 goto ulpi_exit;
1065 }
1066 }
1067
1068 ret = ci_usb_phy_init(ci);
1069 if (ret) {
1070 dev_err(dev, "unable to init phy: %d\n", ret);
1071 return ret;
1072 }
1073
1074 ci->hw_bank.phys = res->start;
1075
1076 ci->irq = platform_get_irq(pdev, 0);
1077 if (ci->irq < 0) {
1078 ret = ci->irq;
1079 goto deinit_phy;
1080 }
1081
1082 ci_get_otg_capable(ci);
1083
1084 dr_mode = ci->platdata->dr_mode;
1085 /* initialize role(s) before the interrupt is requested */
1086 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
1087 ret = ci_hdrc_host_init(ci);
1088 if (ret) {
1089 if (ret == -ENXIO)
1090 dev_info(dev, "doesn't support host\n");
1091 else
1092 goto deinit_phy;
1093 }
1094 }
1095
1096 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1097 ret = ci_hdrc_gadget_init(ci);
1098 if (ret) {
1099 if (ret == -ENXIO)
1100 dev_info(dev, "doesn't support gadget\n");
1101 else
1102 goto deinit_host;
1103 }
1104 }
1105
1106 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1107 dev_err(dev, "no supported roles\n");
1108 ret = -ENODEV;
1109 goto deinit_gadget;
1110 }
1111
1112 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1113 ret = ci_hdrc_otg_init(ci);
1114 if (ret) {
1115 dev_err(dev, "init otg fails, ret = %d\n", ret);
1116 goto deinit_gadget;
1117 }
1118 }
1119
1120 if (ci_role_switch.fwnode) {
1121 ci->role_switch = usb_role_switch_register(dev,
1122 &ci_role_switch);
1123 if (IS_ERR(ci->role_switch)) {
1124 ret = PTR_ERR(ci->role_switch);
1125 goto deinit_otg;
1126 }
1127 }
1128
1129 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1130 if (ci->is_otg) {
1131 ci->role = ci_otg_role(ci);
1132 /* Enable ID change irq */
1133 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1134 } else {
1135 /*
1136 * If the controller is not OTG capable, but support
1137 * role switch, the defalt role is gadget, and the
1138 * user can switch it through debugfs.
1139 */
1140 ci->role = CI_ROLE_GADGET;
1141 }
1142 } else {
1143 ci->role = ci->roles[CI_ROLE_HOST]
1144 ? CI_ROLE_HOST
1145 : CI_ROLE_GADGET;
1146 }
1147
1148 if (!ci_otg_is_fsm_mode(ci)) {
1149 /* only update vbus status for peripheral */
1150 if (ci->role == CI_ROLE_GADGET)
1151 ci_handle_vbus_change(ci);
1152
1153 ret = ci_role_start(ci, ci->role);
1154 if (ret) {
1155 dev_err(dev, "can't start %s role\n",
1156 ci_role(ci)->name);
1157 goto stop;
1158 }
1159 }
1160
1161 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
1162 ci->platdata->name, ci);
1163 if (ret)
1164 goto stop;
1165
1166 ret = ci_extcon_register(ci);
1167 if (ret)
1168 goto stop;
1169
1170 if (ci->supports_runtime_pm) {
1171 pm_runtime_set_active(&pdev->dev);
1172 pm_runtime_enable(&pdev->dev);
1173 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1174 pm_runtime_mark_last_busy(ci->dev);
1175 pm_runtime_use_autosuspend(&pdev->dev);
1176 }
1177
1178 if (ci_otg_is_fsm_mode(ci))
1179 ci_hdrc_otg_fsm_start(ci);
1180
1181 device_set_wakeup_capable(&pdev->dev, true);
1182 dbg_create_files(ci);
1183
1184 return 0;
1185
1186stop:
1187 if (ci->role_switch)
1188 usb_role_switch_unregister(ci->role_switch);
1189deinit_otg:
1190 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1191 ci_hdrc_otg_destroy(ci);
1192deinit_gadget:
1193 ci_hdrc_gadget_destroy(ci);
1194deinit_host:
1195 ci_hdrc_host_destroy(ci);
1196deinit_phy:
1197 ci_usb_phy_exit(ci);
1198ulpi_exit:
1199 ci_ulpi_exit(ci);
1200
1201 return ret;
1202}
1203
1204static int ci_hdrc_remove(struct platform_device *pdev)
1205{
1206 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1207
1208 if (ci->role_switch)
1209 usb_role_switch_unregister(ci->role_switch);
1210
1211 if (ci->supports_runtime_pm) {
1212 pm_runtime_get_sync(&pdev->dev);
1213 pm_runtime_disable(&pdev->dev);
1214 pm_runtime_put_noidle(&pdev->dev);
1215 }
1216
1217 dbg_remove_files(ci);
1218 ci_role_destroy(ci);
1219 ci_hdrc_enter_lpm(ci, true);
1220 ci_usb_phy_exit(ci);
1221 ci_ulpi_exit(ci);
1222
1223 return 0;
1224}
1225
1226#ifdef CONFIG_PM
1227/* Prepare wakeup by SRP before suspend */
1228static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1229{
1230 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1231 !hw_read_otgsc(ci, OTGSC_ID)) {
1232 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1233 PORTSC_PP);
1234 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1235 PORTSC_WKCN);
1236 }
1237}
1238
1239/* Handle SRP when wakeup by data pulse */
1240static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1241{
1242 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1243 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1244 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1245 ci->fsm.a_srp_det = 1;
1246 ci->fsm.a_bus_drop = 0;
1247 } else {
1248 ci->fsm.id = 1;
1249 }
1250 ci_otg_queue_work(ci);
1251 }
1252}
1253
1254static void ci_controller_suspend(struct ci_hdrc *ci)
1255{
1256 disable_irq(ci->irq);
1257 ci_hdrc_enter_lpm(ci, true);
1258 if (ci->platdata->phy_clkgate_delay_us)
1259 usleep_range(ci->platdata->phy_clkgate_delay_us,
1260 ci->platdata->phy_clkgate_delay_us + 50);
1261 usb_phy_set_suspend(ci->usb_phy, 1);
1262 ci->in_lpm = true;
1263 enable_irq(ci->irq);
1264}
1265
1266static int ci_controller_resume(struct device *dev)
1267{
1268 struct ci_hdrc *ci = dev_get_drvdata(dev);
1269 int ret;
1270
1271 dev_dbg(dev, "at %s\n", __func__);
1272
1273 if (!ci->in_lpm) {
1274 WARN_ON(1);
1275 return 0;
1276 }
1277
1278 ci_hdrc_enter_lpm(ci, false);
1279
1280 ret = ci_ulpi_resume(ci);
1281 if (ret)
1282 return ret;
1283
1284 if (ci->usb_phy) {
1285 usb_phy_set_suspend(ci->usb_phy, 0);
1286 usb_phy_set_wakeup(ci->usb_phy, false);
1287 hw_wait_phy_stable();
1288 }
1289
1290 ci->in_lpm = false;
1291 if (ci->wakeup_int) {
1292 ci->wakeup_int = false;
1293 pm_runtime_mark_last_busy(ci->dev);
1294 pm_runtime_put_autosuspend(ci->dev);
1295 enable_irq(ci->irq);
1296 if (ci_otg_is_fsm_mode(ci))
1297 ci_otg_fsm_wakeup_by_srp(ci);
1298 }
1299
1300 return 0;
1301}
1302
1303#ifdef CONFIG_PM_SLEEP
1304static int ci_suspend(struct device *dev)
1305{
1306 struct ci_hdrc *ci = dev_get_drvdata(dev);
1307
1308 if (ci->wq)
1309 flush_workqueue(ci->wq);
1310 /*
1311 * Controller needs to be active during suspend, otherwise the core
1312 * may run resume when the parent is at suspend if other driver's
1313 * suspend fails, it occurs before parent's suspend has not started,
1314 * but the core suspend has finished.
1315 */
1316 if (ci->in_lpm)
1317 pm_runtime_resume(dev);
1318
1319 if (ci->in_lpm) {
1320 WARN_ON(1);
1321 return 0;
1322 }
1323
1324 if (device_may_wakeup(dev)) {
1325 if (ci_otg_is_fsm_mode(ci))
1326 ci_otg_fsm_suspend_for_srp(ci);
1327
1328 usb_phy_set_wakeup(ci->usb_phy, true);
1329 enable_irq_wake(ci->irq);
1330 }
1331
1332 ci_controller_suspend(ci);
1333
1334 return 0;
1335}
1336
1337static int ci_resume(struct device *dev)
1338{
1339 struct ci_hdrc *ci = dev_get_drvdata(dev);
1340 int ret;
1341
1342 if (device_may_wakeup(dev))
1343 disable_irq_wake(ci->irq);
1344
1345 ret = ci_controller_resume(dev);
1346 if (ret)
1347 return ret;
1348
1349 if (ci->supports_runtime_pm) {
1350 pm_runtime_disable(dev);
1351 pm_runtime_set_active(dev);
1352 pm_runtime_enable(dev);
1353 }
1354
1355 return ret;
1356}
1357#endif /* CONFIG_PM_SLEEP */
1358
1359static int ci_runtime_suspend(struct device *dev)
1360{
1361 struct ci_hdrc *ci = dev_get_drvdata(dev);
1362
1363 dev_dbg(dev, "at %s\n", __func__);
1364
1365 if (ci->in_lpm) {
1366 WARN_ON(1);
1367 return 0;
1368 }
1369
1370 if (ci_otg_is_fsm_mode(ci))
1371 ci_otg_fsm_suspend_for_srp(ci);
1372
1373 usb_phy_set_wakeup(ci->usb_phy, true);
1374 ci_controller_suspend(ci);
1375
1376 return 0;
1377}
1378
1379static int ci_runtime_resume(struct device *dev)
1380{
1381 return ci_controller_resume(dev);
1382}
1383
1384#endif /* CONFIG_PM */
1385static const struct dev_pm_ops ci_pm_ops = {
1386 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1387 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1388};
1389
1390static struct platform_driver ci_hdrc_driver = {
1391 .probe = ci_hdrc_probe,
1392 .remove = ci_hdrc_remove,
1393 .driver = {
1394 .name = "ci_hdrc",
1395 .pm = &ci_pm_ops,
1396 .dev_groups = ci_groups,
1397 },
1398};
1399
1400static int __init ci_hdrc_platform_register(void)
1401{
1402 ci_hdrc_host_driver_init();
1403 return platform_driver_register(&ci_hdrc_driver);
1404}
1405module_init(ci_hdrc_platform_register);
1406
1407static void __exit ci_hdrc_platform_unregister(void)
1408{
1409 platform_driver_unregister(&ci_hdrc_driver);
1410}
1411module_exit(ci_hdrc_platform_unregister);
1412
1413MODULE_ALIAS("platform:ci_hdrc");
1414MODULE_LICENSE("GPL v2");
1415MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1416MODULE_DESCRIPTION("ChipIdea HDRC Driver");