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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef __DSI_PHY_H__
7#define __DSI_PHY_H__
8
9#include <linux/regulator/consumer.h>
10
11#include "dsi.h"
12
13#define dsi_phy_read(offset) msm_readl((offset))
14#define dsi_phy_write(offset, data) msm_writel((data), (offset))
15
16/* v3.0.0 10nm implementation that requires the old timings settings */
17#define V3_0_0_10NM_OLD_TIMINGS_QUIRK BIT(0)
18
19struct msm_dsi_phy_ops {
20 int (*init) (struct msm_dsi_phy *phy);
21 int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
22 struct msm_dsi_phy_clk_request *clk_req);
23 void (*disable)(struct msm_dsi_phy *phy);
24};
25
26struct msm_dsi_phy_cfg {
27 enum msm_dsi_phy_type type;
28 struct dsi_reg_config reg_cfg;
29 struct msm_dsi_phy_ops ops;
30
31 /*
32 * Each cell {phy_id, pll_id} of the truth table indicates
33 * if the source PLL selection bit should be set for each PHY.
34 * Fill default H/W values in illegal cells, eg. cell {0, 1}.
35 */
36 bool src_pll_truthtable[DSI_MAX][DSI_MAX];
37 const resource_size_t io_start[DSI_MAX];
38 const int num_dsi_phy;
39 const int quirks;
40};
41
42extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
43extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
44extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
45extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
46extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
47extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
48extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
49extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
50
51struct msm_dsi_dphy_timing {
52 u32 clk_pre;
53 u32 clk_post;
54 u32 clk_zero;
55 u32 clk_trail;
56 u32 clk_prepare;
57 u32 hs_exit;
58 u32 hs_zero;
59 u32 hs_prepare;
60 u32 hs_trail;
61 u32 hs_rqst;
62 u32 ta_go;
63 u32 ta_sure;
64 u32 ta_get;
65
66 struct msm_dsi_phy_shared_timings shared_timings;
67
68 /* For PHY v2 only */
69 u32 hs_rqst_ckln;
70 u32 hs_prep_dly;
71 u32 hs_prep_dly_ckln;
72 u8 hs_halfbyte_en;
73 u8 hs_halfbyte_en_ckln;
74};
75
76struct msm_dsi_phy {
77 struct platform_device *pdev;
78 void __iomem *base;
79 void __iomem *reg_base;
80 void __iomem *lane_base;
81 int id;
82
83 struct clk *ahb_clk;
84 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
85
86 struct msm_dsi_dphy_timing timing;
87 const struct msm_dsi_phy_cfg *cfg;
88
89 enum msm_dsi_phy_usecase usecase;
90 bool regulator_ldo_mode;
91
92 struct msm_dsi_pll *pll;
93};
94
95/*
96 * PHY internal functions
97 */
98int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
99 struct msm_dsi_phy_clk_request *clk_req);
100int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
101 struct msm_dsi_phy_clk_request *clk_req);
102int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
103 struct msm_dsi_phy_clk_request *clk_req);
104void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
105 u32 bit_mask);
106int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);
107
108#endif /* __DSI_PHY_H__ */
109