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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/include/asm/processor.h
4 *
5 * Copyright (C) 1995-1999 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 */
8#ifndef __ASM_PROCESSOR_H
9#define __ASM_PROCESSOR_H
10
11#define KERNEL_DS UL(-1)
12#define USER_DS ((UL(1) << VA_BITS) - 1)
13
14/*
15 * On arm64 systems, unaligned accesses by the CPU are cheap, and so there is
16 * no point in shifting all network buffers by 2 bytes just to make some IP
17 * header fields appear aligned in memory, potentially sacrificing some DMA
18 * performance on some platforms.
19 */
20#define NET_IP_ALIGN 0
21
22#ifndef __ASSEMBLY__
23
24#include <linux/build_bug.h>
25#include <linux/cache.h>
26#include <linux/init.h>
27#include <linux/stddef.h>
28#include <linux/string.h>
29#include <linux/thread_info.h>
30
31#include <asm/alternative.h>
32#include <asm/cpufeature.h>
33#include <asm/hw_breakpoint.h>
34#include <asm/kasan.h>
35#include <asm/lse.h>
36#include <asm/pgtable-hwdef.h>
37#include <asm/pointer_auth.h>
38#include <asm/ptrace.h>
39#include <asm/types.h>
40
41/*
42 * TASK_SIZE - the maximum size of a user space task.
43 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
44 */
45
46#define DEFAULT_MAP_WINDOW_64 (UL(1) << VA_BITS_MIN)
47#define TASK_SIZE_64 (UL(1) << vabits_actual)
48
49#ifdef CONFIG_COMPAT
50#if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS)
51/*
52 * With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied
53 * by the compat vectors page.
54 */
55#define TASK_SIZE_32 UL(0x100000000)
56#else
57#define TASK_SIZE_32 (UL(0x100000000) - PAGE_SIZE)
58#endif /* CONFIG_ARM64_64K_PAGES */
59#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
60 TASK_SIZE_32 : TASK_SIZE_64)
61#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
62 TASK_SIZE_32 : TASK_SIZE_64)
63#define DEFAULT_MAP_WINDOW (test_thread_flag(TIF_32BIT) ? \
64 TASK_SIZE_32 : DEFAULT_MAP_WINDOW_64)
65#else
66#define TASK_SIZE TASK_SIZE_64
67#define DEFAULT_MAP_WINDOW DEFAULT_MAP_WINDOW_64
68#endif /* CONFIG_COMPAT */
69
70#ifdef CONFIG_ARM64_FORCE_52BIT
71#define STACK_TOP_MAX TASK_SIZE_64
72#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4))
73#else
74#define STACK_TOP_MAX DEFAULT_MAP_WINDOW_64
75#define TASK_UNMAPPED_BASE (PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4))
76#endif /* CONFIG_ARM64_FORCE_52BIT */
77
78#ifdef CONFIG_COMPAT
79#define AARCH32_VECTORS_BASE 0xffff0000
80#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
81 AARCH32_VECTORS_BASE : STACK_TOP_MAX)
82#else
83#define STACK_TOP STACK_TOP_MAX
84#endif /* CONFIG_COMPAT */
85
86#ifndef CONFIG_ARM64_FORCE_52BIT
87#define arch_get_mmap_end(addr) ((addr > DEFAULT_MAP_WINDOW) ? TASK_SIZE :\
88 DEFAULT_MAP_WINDOW)
89
90#define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \
91 base + TASK_SIZE - DEFAULT_MAP_WINDOW :\
92 base)
93#endif /* CONFIG_ARM64_FORCE_52BIT */
94
95extern phys_addr_t arm64_dma_phys_limit;
96#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
97
98struct debug_info {
99#ifdef CONFIG_HAVE_HW_BREAKPOINT
100 /* Have we suspended stepping by a debugger? */
101 int suspended_step;
102 /* Allow breakpoints and watchpoints to be disabled for this thread. */
103 int bps_disabled;
104 int wps_disabled;
105 /* Hardware breakpoints pinned to this task. */
106 struct perf_event *hbp_break[ARM_MAX_BRP];
107 struct perf_event *hbp_watch[ARM_MAX_WRP];
108#endif
109};
110
111struct cpu_context {
112 unsigned long x19;
113 unsigned long x20;
114 unsigned long x21;
115 unsigned long x22;
116 unsigned long x23;
117 unsigned long x24;
118 unsigned long x25;
119 unsigned long x26;
120 unsigned long x27;
121 unsigned long x28;
122 unsigned long fp;
123 unsigned long sp;
124 unsigned long pc;
125};
126
127struct thread_struct {
128 struct cpu_context cpu_context; /* cpu context */
129
130 /*
131 * Whitelisted fields for hardened usercopy:
132 * Maintainers must ensure manually that this contains no
133 * implicit padding.
134 */
135 struct {
136 unsigned long tp_value; /* TLS register */
137 unsigned long tp2_value;
138 struct user_fpsimd_state fpsimd_state;
139 } uw;
140
141 unsigned int fpsimd_cpu;
142 void *sve_state; /* SVE registers, if any */
143 unsigned int sve_vl; /* SVE vector length */
144 unsigned int sve_vl_onexec; /* SVE vl after next exec */
145 unsigned long fault_address; /* fault info */
146 unsigned long fault_code; /* ESR_EL1 value */
147 struct debug_info debug; /* debugging */
148#ifdef CONFIG_ARM64_PTR_AUTH
149 struct ptrauth_keys keys_user;
150#endif
151};
152
153static inline void arch_thread_struct_whitelist(unsigned long *offset,
154 unsigned long *size)
155{
156 /* Verify that there is no padding among the whitelisted fields: */
157 BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) !=
158 sizeof_field(struct thread_struct, uw.tp_value) +
159 sizeof_field(struct thread_struct, uw.tp2_value) +
160 sizeof_field(struct thread_struct, uw.fpsimd_state));
161
162 *offset = offsetof(struct thread_struct, uw);
163 *size = sizeof_field(struct thread_struct, uw);
164}
165
166#ifdef CONFIG_COMPAT
167#define task_user_tls(t) \
168({ \
169 unsigned long *__tls; \
170 if (is_compat_thread(task_thread_info(t))) \
171 __tls = &(t)->thread.uw.tp2_value; \
172 else \
173 __tls = &(t)->thread.uw.tp_value; \
174 __tls; \
175 })
176#else
177#define task_user_tls(t) (&(t)->thread.uw.tp_value)
178#endif
179
180/* Sync TPIDR_EL0 back to thread_struct for current */
181void tls_preserve_current_state(void);
182
183#define INIT_THREAD { \
184 .fpsimd_cpu = NR_CPUS, \
185}
186
187static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
188{
189 memset(regs, 0, sizeof(*regs));
190 forget_syscall(regs);
191 regs->pc = pc;
192
193 if (system_uses_irq_prio_masking())
194 regs->pmr_save = GIC_PRIO_IRQON;
195}
196
197static inline void set_ssbs_bit(struct pt_regs *regs)
198{
199 regs->pstate |= PSR_SSBS_BIT;
200}
201
202static inline void set_compat_ssbs_bit(struct pt_regs *regs)
203{
204 regs->pstate |= PSR_AA32_SSBS_BIT;
205}
206
207static inline void start_thread(struct pt_regs *regs, unsigned long pc,
208 unsigned long sp)
209{
210 start_thread_common(regs, pc);
211 regs->pstate = PSR_MODE_EL0t;
212
213 if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
214 set_ssbs_bit(regs);
215
216 regs->sp = sp;
217}
218
219static inline bool is_ttbr0_addr(unsigned long addr)
220{
221 /* entry assembly clears tags for TTBR0 addrs */
222 return addr < TASK_SIZE;
223}
224
225static inline bool is_ttbr1_addr(unsigned long addr)
226{
227 /* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */
228 return arch_kasan_reset_tag(addr) >= PAGE_OFFSET;
229}
230
231#ifdef CONFIG_COMPAT
232static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
233 unsigned long sp)
234{
235 start_thread_common(regs, pc);
236 regs->pstate = PSR_AA32_MODE_USR;
237 if (pc & 1)
238 regs->pstate |= PSR_AA32_T_BIT;
239
240#ifdef __AARCH64EB__
241 regs->pstate |= PSR_AA32_E_BIT;
242#endif
243
244 if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
245 set_compat_ssbs_bit(regs);
246
247 regs->compat_sp = sp;
248}
249#endif
250
251/* Forward declaration, a strange C thing */
252struct task_struct;
253
254/* Free all resources held by a thread. */
255extern void release_thread(struct task_struct *);
256
257unsigned long get_wchan(struct task_struct *p);
258
259static inline void cpu_relax(void)
260{
261 asm volatile("yield" ::: "memory");
262}
263
264/* Thread switching */
265extern struct task_struct *cpu_switch_to(struct task_struct *prev,
266 struct task_struct *next);
267
268#define task_pt_regs(p) \
269 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
270
271#define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
272#define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
273
274/*
275 * Prefetching support
276 */
277#define ARCH_HAS_PREFETCH
278static inline void prefetch(const void *ptr)
279{
280 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
281}
282
283#define ARCH_HAS_PREFETCHW
284static inline void prefetchw(const void *ptr)
285{
286 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
287}
288
289#define ARCH_HAS_SPINLOCK_PREFETCH
290static inline void spin_lock_prefetch(const void *ptr)
291{
292 asm volatile(ARM64_LSE_ATOMIC_INSN(
293 "prfm pstl1strm, %a0",
294 "nop") : : "p" (ptr));
295}
296
297extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */
298extern void __init minsigstksz_setup(void);
299
300/*
301 * Not at the top of the file due to a direct #include cycle between
302 * <asm/fpsimd.h> and <asm/processor.h>. Deferring this #include
303 * ensures that contents of processor.h are visible to fpsimd.h even if
304 * processor.h is included first.
305 *
306 * These prctl helpers are the only things in this file that require
307 * fpsimd.h. The core code expects them to be in this header.
308 */
309#include <asm/fpsimd.h>
310
311/* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */
312#define SVE_SET_VL(arg) sve_set_current_vl(arg)
313#define SVE_GET_VL() sve_get_current_vl()
314
315/* PR_PAC_RESET_KEYS prctl */
316#define PAC_RESET_KEYS(tsk, arg) ptrauth_prctl_reset_keys(tsk, arg)
317
318#ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
319/* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */
320long set_tagged_addr_ctrl(unsigned long arg);
321long get_tagged_addr_ctrl(void);
322#define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(arg)
323#define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl()
324#endif
325
326/*
327 * For CONFIG_GCC_PLUGIN_STACKLEAK
328 *
329 * These need to be macros because otherwise we get stuck in a nightmare
330 * of header definitions for the use of task_stack_page.
331 */
332
333#define current_top_of_stack() \
334({ \
335 struct stack_info _info; \
336 BUG_ON(!on_accessible_stack(current, current_stack_pointer, &_info)); \
337 _info.high; \
338})
339#define on_thread_stack() (on_task_stack(current, current_stack_pointer, NULL))
340
341#endif /* __ASSEMBLY__ */
342#endif /* __ASM_PROCESSOR_H */