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1Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
2
3The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
4bus width configurations.
5
6The Zynq DDR ECC controller has an optional ECC support in half-bus width
7(16-bit) configuration.
8
9These both ECC controllers correct single bit ECC errors and detect double bit
10ECC errors.
11
12Required properties:
13 - compatible: One of:
14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
16 - reg: Should contain DDR controller registers location and length.
17
18Required properties for "xlnx,zynqmp-ddrc-2.40a":
19 - interrupts: Property with a value describing the interrupt number.
20
21Example:
22 memory-controller@f8006000 {
23 compatible = "xlnx,zynq-ddrc-a05";
24 reg = <0xf8006000 0x1000>;
25 };
26
27 mc: memory-controller@fd070000 {
28 compatible = "xlnx,zynqmp-ddrc-2.40a";
29 reg = <0x0 0xfd070000 0x0 0x30000>;
30 interrupt-parent = <&gic>;
31 interrupts = <0 112 4>;
32 };