tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include "amdgpu.h"
29#include "amdgpu_atombios.h"
30#include "amdgpu_ih.h"
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33#include "amdgpu_ucode.h"
34#include "amdgpu_psp.h"
35#include "atom.h"
36#include "amd_pcie.h"
37
38#include "uvd/uvd_7_0_offset.h"
39#include "gc/gc_9_0_offset.h"
40#include "gc/gc_9_0_sh_mask.h"
41#include "sdma0/sdma0_4_0_offset.h"
42#include "sdma1/sdma1_4_0_offset.h"
43#include "hdp/hdp_4_0_offset.h"
44#include "hdp/hdp_4_0_sh_mask.h"
45#include "smuio/smuio_9_0_offset.h"
46#include "smuio/smuio_9_0_sh_mask.h"
47#include "nbio/nbio_7_0_default.h"
48#include "nbio/nbio_7_0_offset.h"
49#include "nbio/nbio_7_0_sh_mask.h"
50#include "nbio/nbio_7_0_smn.h"
51#include "mp/mp_9_0_offset.h"
52
53#include "soc15.h"
54#include "soc15_common.h"
55#include "gfx_v9_0.h"
56#include "gmc_v9_0.h"
57#include "gfxhub_v1_0.h"
58#include "mmhub_v1_0.h"
59#include "df_v1_7.h"
60#include "df_v3_6.h"
61#include "nbio_v6_1.h"
62#include "nbio_v7_0.h"
63#include "nbio_v7_4.h"
64#include "vega10_ih.h"
65#include "sdma_v4_0.h"
66#include "uvd_v7_0.h"
67#include "vce_v4_0.h"
68#include "vcn_v1_0.h"
69#include "vcn_v2_0.h"
70#include "jpeg_v2_0.h"
71#include "vcn_v2_5.h"
72#include "jpeg_v2_5.h"
73#include "dce_virtual.h"
74#include "mxgpu_ai.h"
75#include "amdgpu_smu.h"
76#include "amdgpu_ras.h"
77#include "amdgpu_xgmi.h"
78#include <uapi/linux/kfd_ioctl.h>
79
80#define mmMP0_MISC_CGTT_CTRL0 0x01b9
81#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
82#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
83#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
84
85/* for Vega20 register name change */
86#define mmHDP_MEM_POWER_CTRL 0x00d4
87#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
88#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
89#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
90#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
91#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
92
93/* for Vega20/arcturus regiter offset change */
94#define mmROM_INDEX_VG20 0x00e4
95#define mmROM_INDEX_VG20_BASE_IDX 0
96#define mmROM_DATA_VG20 0x00e5
97#define mmROM_DATA_VG20_BASE_IDX 0
98
99/*
100 * Indirect registers accessor
101 */
102static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
103{
104 unsigned long flags, address, data;
105 u32 r;
106 address = adev->nbio.funcs->get_pcie_index_offset(adev);
107 data = adev->nbio.funcs->get_pcie_data_offset(adev);
108
109 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
110 WREG32(address, reg);
111 (void)RREG32(address);
112 r = RREG32(data);
113 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
114 return r;
115}
116
117static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
118{
119 unsigned long flags, address, data;
120
121 address = adev->nbio.funcs->get_pcie_index_offset(adev);
122 data = adev->nbio.funcs->get_pcie_data_offset(adev);
123
124 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
125 WREG32(address, reg);
126 (void)RREG32(address);
127 WREG32(data, v);
128 (void)RREG32(data);
129 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
130}
131
132static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
133{
134 unsigned long flags, address, data;
135 u64 r;
136 address = adev->nbio.funcs->get_pcie_index_offset(adev);
137 data = adev->nbio.funcs->get_pcie_data_offset(adev);
138
139 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
140 /* read low 32 bit */
141 WREG32(address, reg);
142 (void)RREG32(address);
143 r = RREG32(data);
144
145 /* read high 32 bit*/
146 WREG32(address, reg + 4);
147 (void)RREG32(address);
148 r |= ((u64)RREG32(data) << 32);
149 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
150 return r;
151}
152
153static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
154{
155 unsigned long flags, address, data;
156
157 address = adev->nbio.funcs->get_pcie_index_offset(adev);
158 data = adev->nbio.funcs->get_pcie_data_offset(adev);
159
160 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
161 /* write low 32 bit */
162 WREG32(address, reg);
163 (void)RREG32(address);
164 WREG32(data, (u32)(v & 0xffffffffULL));
165 (void)RREG32(data);
166
167 /* write high 32 bit */
168 WREG32(address, reg + 4);
169 (void)RREG32(address);
170 WREG32(data, (u32)(v >> 32));
171 (void)RREG32(data);
172 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
173}
174
175static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
176{
177 unsigned long flags, address, data;
178 u32 r;
179
180 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
181 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
182
183 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
184 WREG32(address, ((reg) & 0x1ff));
185 r = RREG32(data);
186 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
187 return r;
188}
189
190static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
191{
192 unsigned long flags, address, data;
193
194 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
195 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
196
197 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
198 WREG32(address, ((reg) & 0x1ff));
199 WREG32(data, (v));
200 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
201}
202
203static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
204{
205 unsigned long flags, address, data;
206 u32 r;
207
208 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
209 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
210
211 spin_lock_irqsave(&adev->didt_idx_lock, flags);
212 WREG32(address, (reg));
213 r = RREG32(data);
214 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
215 return r;
216}
217
218static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
219{
220 unsigned long flags, address, data;
221
222 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
223 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
224
225 spin_lock_irqsave(&adev->didt_idx_lock, flags);
226 WREG32(address, (reg));
227 WREG32(data, (v));
228 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
229}
230
231static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
232{
233 unsigned long flags;
234 u32 r;
235
236 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
237 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
238 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
239 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
240 return r;
241}
242
243static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
244{
245 unsigned long flags;
246
247 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
248 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
249 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
250 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
251}
252
253static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
254{
255 unsigned long flags;
256 u32 r;
257
258 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
259 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
260 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
261 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
262 return r;
263}
264
265static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
266{
267 unsigned long flags;
268
269 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
270 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
271 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
272 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
273}
274
275static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
276{
277 return adev->nbio.funcs->get_memsize(adev);
278}
279
280static u32 soc15_get_xclk(struct amdgpu_device *adev)
281{
282 u32 reference_clock = adev->clock.spll.reference_freq;
283
284 if (adev->asic_type == CHIP_RAVEN)
285 return reference_clock / 4;
286
287 return reference_clock;
288}
289
290
291void soc15_grbm_select(struct amdgpu_device *adev,
292 u32 me, u32 pipe, u32 queue, u32 vmid)
293{
294 u32 grbm_gfx_cntl = 0;
295 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
296 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
297 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
298 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
299
300 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
301}
302
303static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
304{
305 /* todo */
306}
307
308static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
309{
310 /* todo */
311 return false;
312}
313
314static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
315 u8 *bios, u32 length_bytes)
316{
317 u32 *dw_ptr;
318 u32 i, length_dw;
319 uint32_t rom_index_offset;
320 uint32_t rom_data_offset;
321
322 if (bios == NULL)
323 return false;
324 if (length_bytes == 0)
325 return false;
326 /* APU vbios image is part of sbios image */
327 if (adev->flags & AMD_IS_APU)
328 return false;
329
330 dw_ptr = (u32 *)bios;
331 length_dw = ALIGN(length_bytes, 4) / 4;
332
333 switch (adev->asic_type) {
334 case CHIP_VEGA20:
335 case CHIP_ARCTURUS:
336 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20);
337 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20);
338 break;
339 default:
340 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
341 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
342 break;
343 }
344
345 /* set rom index to 0 */
346 WREG32(rom_index_offset, 0);
347 /* read out the rom data */
348 for (i = 0; i < length_dw; i++)
349 dw_ptr[i] = RREG32(rom_data_offset);
350
351 return true;
352}
353
354static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
355 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
356 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
357 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
358 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
359 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
360 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
361 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
362 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
363 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
364 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
365 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
366 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
367 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
368 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
369 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
370 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
371 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
372 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
373 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
374 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
375};
376
377static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
378 u32 sh_num, u32 reg_offset)
379{
380 uint32_t val;
381
382 mutex_lock(&adev->grbm_idx_mutex);
383 if (se_num != 0xffffffff || sh_num != 0xffffffff)
384 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
385
386 val = RREG32(reg_offset);
387
388 if (se_num != 0xffffffff || sh_num != 0xffffffff)
389 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
390 mutex_unlock(&adev->grbm_idx_mutex);
391 return val;
392}
393
394static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
395 bool indexed, u32 se_num,
396 u32 sh_num, u32 reg_offset)
397{
398 if (indexed) {
399 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
400 } else {
401 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
402 return adev->gfx.config.gb_addr_config;
403 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
404 return adev->gfx.config.db_debug2;
405 return RREG32(reg_offset);
406 }
407}
408
409static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
410 u32 sh_num, u32 reg_offset, u32 *value)
411{
412 uint32_t i;
413 struct soc15_allowed_register_entry *en;
414
415 *value = 0;
416 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
417 en = &soc15_allowed_read_registers[i];
418 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
419 + en->reg_offset))
420 continue;
421
422 *value = soc15_get_register_value(adev,
423 soc15_allowed_read_registers[i].grbm_indexed,
424 se_num, sh_num, reg_offset);
425 return 0;
426 }
427 return -EINVAL;
428}
429
430
431/**
432 * soc15_program_register_sequence - program an array of registers.
433 *
434 * @adev: amdgpu_device pointer
435 * @regs: pointer to the register array
436 * @array_size: size of the register array
437 *
438 * Programs an array or registers with and and or masks.
439 * This is a helper for setting golden registers.
440 */
441
442void soc15_program_register_sequence(struct amdgpu_device *adev,
443 const struct soc15_reg_golden *regs,
444 const u32 array_size)
445{
446 const struct soc15_reg_golden *entry;
447 u32 tmp, reg;
448 int i;
449
450 for (i = 0; i < array_size; ++i) {
451 entry = ®s[i];
452 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
453
454 if (entry->and_mask == 0xffffffff) {
455 tmp = entry->or_mask;
456 } else {
457 tmp = RREG32(reg);
458 tmp &= ~(entry->and_mask);
459 tmp |= (entry->or_mask & entry->and_mask);
460 }
461
462 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
463 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
464 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
465 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
466 WREG32_RLC(reg, tmp);
467 else
468 WREG32(reg, tmp);
469
470 }
471
472}
473
474static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
475{
476 u32 i;
477 int ret = 0;
478
479 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
480
481 dev_info(adev->dev, "GPU mode1 reset\n");
482
483 /* disable BM */
484 pci_clear_master(adev->pdev);
485
486 pci_save_state(adev->pdev);
487
488 ret = psp_gpu_reset(adev);
489 if (ret)
490 dev_err(adev->dev, "GPU mode1 reset failed\n");
491
492 pci_restore_state(adev->pdev);
493
494 /* wait for asic to come out of reset */
495 for (i = 0; i < adev->usec_timeout; i++) {
496 u32 memsize = adev->nbio.funcs->get_memsize(adev);
497
498 if (memsize != 0xffffffff)
499 break;
500 udelay(1);
501 }
502
503 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
504
505 return ret;
506}
507
508static int soc15_asic_baco_reset(struct amdgpu_device *adev)
509{
510 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
511 int ret = 0;
512
513 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
514 if (ras && ras->supported)
515 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
516
517 ret = amdgpu_dpm_baco_reset(adev);
518 if (ret)
519 return ret;
520
521 /* re-enable doorbell interrupt after BACO exit */
522 if (ras && ras->supported)
523 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
524
525 return 0;
526}
527
528static enum amd_reset_method
529soc15_asic_reset_method(struct amdgpu_device *adev)
530{
531 bool baco_reset = false;
532 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
533
534 switch (adev->asic_type) {
535 case CHIP_RAVEN:
536 case CHIP_RENOIR:
537 return AMD_RESET_METHOD_MODE2;
538 case CHIP_VEGA10:
539 case CHIP_VEGA12:
540 case CHIP_ARCTURUS:
541 baco_reset = amdgpu_dpm_is_baco_supported(adev);
542 break;
543 case CHIP_VEGA20:
544 if (adev->psp.sos_fw_version >= 0x80067)
545 baco_reset = amdgpu_dpm_is_baco_supported(adev);
546
547 /*
548 * 1. PMFW version > 0x284300: all cases use baco
549 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
550 */
551 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
552 baco_reset = false;
553 break;
554 default:
555 break;
556 }
557
558 if (baco_reset)
559 return AMD_RESET_METHOD_BACO;
560 else
561 return AMD_RESET_METHOD_MODE1;
562}
563
564static int soc15_asic_reset(struct amdgpu_device *adev)
565{
566 /* original raven doesn't have full asic reset */
567 if (adev->pdev->device == 0x15dd && adev->rev_id < 0x8)
568 return 0;
569
570 switch (soc15_asic_reset_method(adev)) {
571 case AMD_RESET_METHOD_BACO:
572 if (!adev->in_suspend)
573 amdgpu_inc_vram_lost(adev);
574 return soc15_asic_baco_reset(adev);
575 case AMD_RESET_METHOD_MODE2:
576 return amdgpu_dpm_mode2_reset(adev);
577 default:
578 if (!adev->in_suspend)
579 amdgpu_inc_vram_lost(adev);
580 return soc15_asic_mode1_reset(adev);
581 }
582}
583
584static bool soc15_supports_baco(struct amdgpu_device *adev)
585{
586 switch (adev->asic_type) {
587 case CHIP_VEGA10:
588 case CHIP_VEGA12:
589 case CHIP_ARCTURUS:
590 return amdgpu_dpm_is_baco_supported(adev);
591 case CHIP_VEGA20:
592 if (adev->psp.sos_fw_version >= 0x80067)
593 return amdgpu_dpm_is_baco_supported(adev);
594 return false;
595 default:
596 return false;
597 }
598}
599
600/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
601 u32 cntl_reg, u32 status_reg)
602{
603 return 0;
604}*/
605
606static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
607{
608 /*int r;
609
610 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
611 if (r)
612 return r;
613
614 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
615 */
616 return 0;
617}
618
619static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
620{
621 /* todo */
622
623 return 0;
624}
625
626static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
627{
628 if (pci_is_root_bus(adev->pdev->bus))
629 return;
630
631 if (amdgpu_pcie_gen2 == 0)
632 return;
633
634 if (adev->flags & AMD_IS_APU)
635 return;
636
637 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
638 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
639 return;
640
641 /* todo */
642}
643
644static void soc15_program_aspm(struct amdgpu_device *adev)
645{
646
647 if (amdgpu_aspm == 0)
648 return;
649
650 /* todo */
651}
652
653static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
654 bool enable)
655{
656 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
657 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
658}
659
660static const struct amdgpu_ip_block_version vega10_common_ip_block =
661{
662 .type = AMD_IP_BLOCK_TYPE_COMMON,
663 .major = 2,
664 .minor = 0,
665 .rev = 0,
666 .funcs = &soc15_common_ip_funcs,
667};
668
669static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
670{
671 return adev->nbio.funcs->get_rev_id(adev);
672}
673
674int soc15_set_ip_blocks(struct amdgpu_device *adev)
675{
676 /* Set IP register base before any HW register access */
677 switch (adev->asic_type) {
678 case CHIP_VEGA10:
679 case CHIP_VEGA12:
680 case CHIP_RAVEN:
681 case CHIP_RENOIR:
682 vega10_reg_base_init(adev);
683 break;
684 case CHIP_VEGA20:
685 vega20_reg_base_init(adev);
686 break;
687 case CHIP_ARCTURUS:
688 arct_reg_base_init(adev);
689 break;
690 default:
691 return -EINVAL;
692 }
693
694 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
695 adev->gmc.xgmi.supported = true;
696
697 if (adev->flags & AMD_IS_APU) {
698 adev->nbio.funcs = &nbio_v7_0_funcs;
699 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
700 } else if (adev->asic_type == CHIP_VEGA20 ||
701 adev->asic_type == CHIP_ARCTURUS) {
702 adev->nbio.funcs = &nbio_v7_4_funcs;
703 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
704 } else {
705 adev->nbio.funcs = &nbio_v6_1_funcs;
706 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
707 }
708
709 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
710 adev->df.funcs = &df_v3_6_funcs;
711 else
712 adev->df.funcs = &df_v1_7_funcs;
713
714 adev->rev_id = soc15_get_rev_id(adev);
715 adev->nbio.funcs->detect_hw_virt(adev);
716
717 if (amdgpu_sriov_vf(adev))
718 adev->virt.ops = &xgpu_ai_virt_ops;
719
720 switch (adev->asic_type) {
721 case CHIP_VEGA10:
722 case CHIP_VEGA12:
723 case CHIP_VEGA20:
724 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
725 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
726
727 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
728 if (amdgpu_sriov_vf(adev)) {
729 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
730 if (adev->asic_type == CHIP_VEGA20)
731 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
732 else
733 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
734 }
735 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
736 } else {
737 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
738 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
739 if (adev->asic_type == CHIP_VEGA20)
740 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
741 else
742 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
743 }
744 }
745 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
746 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
747 if (is_support_sw_smu(adev)) {
748 if (!amdgpu_sriov_vf(adev))
749 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
750 } else {
751 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
752 }
753 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
754 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
755#if defined(CONFIG_DRM_AMD_DC)
756 else if (amdgpu_device_has_dc_support(adev))
757 amdgpu_device_ip_block_add(adev, &dm_ip_block);
758#endif
759 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
760 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
761 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
762 }
763 break;
764 case CHIP_RAVEN:
765 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
766 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
767 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
768 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
769 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
770 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
771 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
772 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
773 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
774 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
775#if defined(CONFIG_DRM_AMD_DC)
776 else if (amdgpu_device_has_dc_support(adev))
777 amdgpu_device_ip_block_add(adev, &dm_ip_block);
778#endif
779 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
780 break;
781 case CHIP_ARCTURUS:
782 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
783 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
784
785 if (amdgpu_sriov_vf(adev)) {
786 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
787 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
788 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
789 } else {
790 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
791 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
792 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
793 }
794
795 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
796 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
797 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
798 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
799 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
800
801 if (amdgpu_sriov_vf(adev)) {
802 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
803 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
804 } else {
805 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
806 }
807 if (!amdgpu_sriov_vf(adev))
808 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
809 break;
810 case CHIP_RENOIR:
811 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
812 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
813 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
814 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
815 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
816 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
817 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
818 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
819 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
820 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
821#if defined(CONFIG_DRM_AMD_DC)
822 else if (amdgpu_device_has_dc_support(adev))
823 amdgpu_device_ip_block_add(adev, &dm_ip_block);
824#endif
825 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
826 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
827 break;
828 default:
829 return -EINVAL;
830 }
831
832 return 0;
833}
834
835static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
836{
837 adev->nbio.funcs->hdp_flush(adev, ring);
838}
839
840static void soc15_invalidate_hdp(struct amdgpu_device *adev,
841 struct amdgpu_ring *ring)
842{
843 if (!ring || !ring->funcs->emit_wreg)
844 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
845 else
846 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
847 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
848}
849
850static bool soc15_need_full_reset(struct amdgpu_device *adev)
851{
852 /* change this when we implement soft reset */
853 return true;
854}
855static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
856 uint64_t *count1)
857{
858 uint32_t perfctr = 0;
859 uint64_t cnt0_of, cnt1_of;
860 int tmp;
861
862 /* This reports 0 on APUs, so return to avoid writing/reading registers
863 * that may or may not be different from their GPU counterparts
864 */
865 if (adev->flags & AMD_IS_APU)
866 return;
867
868 /* Set the 2 events that we wish to watch, defined above */
869 /* Reg 40 is # received msgs */
870 /* Reg 104 is # of posted requests sent */
871 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
872 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
873
874 /* Write to enable desired perf counters */
875 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
876 /* Zero out and enable the perf counters
877 * Write 0x5:
878 * Bit 0 = Start all counters(1)
879 * Bit 2 = Global counter reset enable(1)
880 */
881 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
882
883 msleep(1000);
884
885 /* Load the shadow and disable the perf counters
886 * Write 0x2:
887 * Bit 0 = Stop counters(0)
888 * Bit 1 = Load the shadow counters(1)
889 */
890 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
891
892 /* Read register values to get any >32bit overflow */
893 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
894 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
895 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
896
897 /* Get the values and add the overflow */
898 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
899 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
900}
901
902static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
903 uint64_t *count1)
904{
905 uint32_t perfctr = 0;
906 uint64_t cnt0_of, cnt1_of;
907 int tmp;
908
909 /* This reports 0 on APUs, so return to avoid writing/reading registers
910 * that may or may not be different from their GPU counterparts
911 */
912 if (adev->flags & AMD_IS_APU)
913 return;
914
915 /* Set the 2 events that we wish to watch, defined above */
916 /* Reg 40 is # received msgs */
917 /* Reg 108 is # of posted requests sent on VG20 */
918 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
919 EVENT0_SEL, 40);
920 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
921 EVENT1_SEL, 108);
922
923 /* Write to enable desired perf counters */
924 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
925 /* Zero out and enable the perf counters
926 * Write 0x5:
927 * Bit 0 = Start all counters(1)
928 * Bit 2 = Global counter reset enable(1)
929 */
930 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
931
932 msleep(1000);
933
934 /* Load the shadow and disable the perf counters
935 * Write 0x2:
936 * Bit 0 = Stop counters(0)
937 * Bit 1 = Load the shadow counters(1)
938 */
939 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
940
941 /* Read register values to get any >32bit overflow */
942 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
943 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
944 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
945
946 /* Get the values and add the overflow */
947 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
948 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
949}
950
951static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
952{
953 u32 sol_reg;
954
955 /* Just return false for soc15 GPUs. Reset does not seem to
956 * be necessary.
957 */
958 if (!amdgpu_passthrough(adev))
959 return false;
960
961 if (adev->flags & AMD_IS_APU)
962 return false;
963
964 /* Check sOS sign of life register to confirm sys driver and sOS
965 * are already been loaded.
966 */
967 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
968 if (sol_reg)
969 return true;
970
971 return false;
972}
973
974static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
975{
976 uint64_t nak_r, nak_g;
977
978 /* Get the number of NAKs received and generated */
979 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
980 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
981
982 /* Add the total number of NAKs, i.e the number of replays */
983 return (nak_r + nak_g);
984}
985
986static const struct amdgpu_asic_funcs soc15_asic_funcs =
987{
988 .read_disabled_bios = &soc15_read_disabled_bios,
989 .read_bios_from_rom = &soc15_read_bios_from_rom,
990 .read_register = &soc15_read_register,
991 .reset = &soc15_asic_reset,
992 .reset_method = &soc15_asic_reset_method,
993 .set_vga_state = &soc15_vga_set_state,
994 .get_xclk = &soc15_get_xclk,
995 .set_uvd_clocks = &soc15_set_uvd_clocks,
996 .set_vce_clocks = &soc15_set_vce_clocks,
997 .get_config_memsize = &soc15_get_config_memsize,
998 .flush_hdp = &soc15_flush_hdp,
999 .invalidate_hdp = &soc15_invalidate_hdp,
1000 .need_full_reset = &soc15_need_full_reset,
1001 .init_doorbell_index = &vega10_doorbell_index_init,
1002 .get_pcie_usage = &soc15_get_pcie_usage,
1003 .need_reset_on_init = &soc15_need_reset_on_init,
1004 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1005 .supports_baco = &soc15_supports_baco,
1006};
1007
1008static const struct amdgpu_asic_funcs vega20_asic_funcs =
1009{
1010 .read_disabled_bios = &soc15_read_disabled_bios,
1011 .read_bios_from_rom = &soc15_read_bios_from_rom,
1012 .read_register = &soc15_read_register,
1013 .reset = &soc15_asic_reset,
1014 .reset_method = &soc15_asic_reset_method,
1015 .set_vga_state = &soc15_vga_set_state,
1016 .get_xclk = &soc15_get_xclk,
1017 .set_uvd_clocks = &soc15_set_uvd_clocks,
1018 .set_vce_clocks = &soc15_set_vce_clocks,
1019 .get_config_memsize = &soc15_get_config_memsize,
1020 .flush_hdp = &soc15_flush_hdp,
1021 .invalidate_hdp = &soc15_invalidate_hdp,
1022 .need_full_reset = &soc15_need_full_reset,
1023 .init_doorbell_index = &vega20_doorbell_index_init,
1024 .get_pcie_usage = &vega20_get_pcie_usage,
1025 .need_reset_on_init = &soc15_need_reset_on_init,
1026 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1027 .supports_baco = &soc15_supports_baco,
1028};
1029
1030static int soc15_common_early_init(void *handle)
1031{
1032#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034
1035 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1036 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1037 adev->smc_rreg = NULL;
1038 adev->smc_wreg = NULL;
1039 adev->pcie_rreg = &soc15_pcie_rreg;
1040 adev->pcie_wreg = &soc15_pcie_wreg;
1041 adev->pcie_rreg64 = &soc15_pcie_rreg64;
1042 adev->pcie_wreg64 = &soc15_pcie_wreg64;
1043 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1044 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1045 adev->didt_rreg = &soc15_didt_rreg;
1046 adev->didt_wreg = &soc15_didt_wreg;
1047 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1048 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1049 adev->se_cac_rreg = &soc15_se_cac_rreg;
1050 adev->se_cac_wreg = &soc15_se_cac_wreg;
1051
1052
1053 adev->external_rev_id = 0xFF;
1054 switch (adev->asic_type) {
1055 case CHIP_VEGA10:
1056 adev->asic_funcs = &soc15_asic_funcs;
1057 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1058 AMD_CG_SUPPORT_GFX_MGLS |
1059 AMD_CG_SUPPORT_GFX_RLC_LS |
1060 AMD_CG_SUPPORT_GFX_CP_LS |
1061 AMD_CG_SUPPORT_GFX_3D_CGCG |
1062 AMD_CG_SUPPORT_GFX_3D_CGLS |
1063 AMD_CG_SUPPORT_GFX_CGCG |
1064 AMD_CG_SUPPORT_GFX_CGLS |
1065 AMD_CG_SUPPORT_BIF_MGCG |
1066 AMD_CG_SUPPORT_BIF_LS |
1067 AMD_CG_SUPPORT_HDP_LS |
1068 AMD_CG_SUPPORT_DRM_MGCG |
1069 AMD_CG_SUPPORT_DRM_LS |
1070 AMD_CG_SUPPORT_ROM_MGCG |
1071 AMD_CG_SUPPORT_DF_MGCG |
1072 AMD_CG_SUPPORT_SDMA_MGCG |
1073 AMD_CG_SUPPORT_SDMA_LS |
1074 AMD_CG_SUPPORT_MC_MGCG |
1075 AMD_CG_SUPPORT_MC_LS;
1076 adev->pg_flags = 0;
1077 adev->external_rev_id = 0x1;
1078 break;
1079 case CHIP_VEGA12:
1080 adev->asic_funcs = &soc15_asic_funcs;
1081 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1082 AMD_CG_SUPPORT_GFX_MGLS |
1083 AMD_CG_SUPPORT_GFX_CGCG |
1084 AMD_CG_SUPPORT_GFX_CGLS |
1085 AMD_CG_SUPPORT_GFX_3D_CGCG |
1086 AMD_CG_SUPPORT_GFX_3D_CGLS |
1087 AMD_CG_SUPPORT_GFX_CP_LS |
1088 AMD_CG_SUPPORT_MC_LS |
1089 AMD_CG_SUPPORT_MC_MGCG |
1090 AMD_CG_SUPPORT_SDMA_MGCG |
1091 AMD_CG_SUPPORT_SDMA_LS |
1092 AMD_CG_SUPPORT_BIF_MGCG |
1093 AMD_CG_SUPPORT_BIF_LS |
1094 AMD_CG_SUPPORT_HDP_MGCG |
1095 AMD_CG_SUPPORT_HDP_LS |
1096 AMD_CG_SUPPORT_ROM_MGCG |
1097 AMD_CG_SUPPORT_VCE_MGCG |
1098 AMD_CG_SUPPORT_UVD_MGCG;
1099 adev->pg_flags = 0;
1100 adev->external_rev_id = adev->rev_id + 0x14;
1101 break;
1102 case CHIP_VEGA20:
1103 adev->asic_funcs = &vega20_asic_funcs;
1104 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1105 AMD_CG_SUPPORT_GFX_MGLS |
1106 AMD_CG_SUPPORT_GFX_CGCG |
1107 AMD_CG_SUPPORT_GFX_CGLS |
1108 AMD_CG_SUPPORT_GFX_3D_CGCG |
1109 AMD_CG_SUPPORT_GFX_3D_CGLS |
1110 AMD_CG_SUPPORT_GFX_CP_LS |
1111 AMD_CG_SUPPORT_MC_LS |
1112 AMD_CG_SUPPORT_MC_MGCG |
1113 AMD_CG_SUPPORT_SDMA_MGCG |
1114 AMD_CG_SUPPORT_SDMA_LS |
1115 AMD_CG_SUPPORT_BIF_MGCG |
1116 AMD_CG_SUPPORT_BIF_LS |
1117 AMD_CG_SUPPORT_HDP_MGCG |
1118 AMD_CG_SUPPORT_HDP_LS |
1119 AMD_CG_SUPPORT_ROM_MGCG |
1120 AMD_CG_SUPPORT_VCE_MGCG |
1121 AMD_CG_SUPPORT_UVD_MGCG;
1122 adev->pg_flags = 0;
1123 adev->external_rev_id = adev->rev_id + 0x28;
1124 break;
1125 case CHIP_RAVEN:
1126 adev->asic_funcs = &soc15_asic_funcs;
1127 if (adev->rev_id >= 0x8)
1128 adev->external_rev_id = adev->rev_id + 0x79;
1129 else if (adev->pdev->device == 0x15d8)
1130 adev->external_rev_id = adev->rev_id + 0x41;
1131 else if (adev->rev_id == 1)
1132 adev->external_rev_id = adev->rev_id + 0x20;
1133 else
1134 adev->external_rev_id = adev->rev_id + 0x01;
1135
1136 if (adev->rev_id >= 0x8) {
1137 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1138 AMD_CG_SUPPORT_GFX_MGLS |
1139 AMD_CG_SUPPORT_GFX_CP_LS |
1140 AMD_CG_SUPPORT_GFX_3D_CGCG |
1141 AMD_CG_SUPPORT_GFX_3D_CGLS |
1142 AMD_CG_SUPPORT_GFX_CGCG |
1143 AMD_CG_SUPPORT_GFX_CGLS |
1144 AMD_CG_SUPPORT_BIF_LS |
1145 AMD_CG_SUPPORT_HDP_LS |
1146 AMD_CG_SUPPORT_ROM_MGCG |
1147 AMD_CG_SUPPORT_MC_MGCG |
1148 AMD_CG_SUPPORT_MC_LS |
1149 AMD_CG_SUPPORT_SDMA_MGCG |
1150 AMD_CG_SUPPORT_SDMA_LS |
1151 AMD_CG_SUPPORT_VCN_MGCG;
1152
1153 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1154 } else if (adev->pdev->device == 0x15d8) {
1155 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1156 AMD_CG_SUPPORT_GFX_MGLS |
1157 AMD_CG_SUPPORT_GFX_CP_LS |
1158 AMD_CG_SUPPORT_GFX_3D_CGCG |
1159 AMD_CG_SUPPORT_GFX_3D_CGLS |
1160 AMD_CG_SUPPORT_GFX_CGCG |
1161 AMD_CG_SUPPORT_GFX_CGLS |
1162 AMD_CG_SUPPORT_BIF_LS |
1163 AMD_CG_SUPPORT_HDP_LS |
1164 AMD_CG_SUPPORT_ROM_MGCG |
1165 AMD_CG_SUPPORT_MC_MGCG |
1166 AMD_CG_SUPPORT_MC_LS |
1167 AMD_CG_SUPPORT_SDMA_MGCG |
1168 AMD_CG_SUPPORT_SDMA_LS;
1169
1170 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1171 AMD_PG_SUPPORT_MMHUB |
1172 AMD_PG_SUPPORT_VCN |
1173 AMD_PG_SUPPORT_VCN_DPG;
1174 } else {
1175 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1176 AMD_CG_SUPPORT_GFX_MGLS |
1177 AMD_CG_SUPPORT_GFX_RLC_LS |
1178 AMD_CG_SUPPORT_GFX_CP_LS |
1179 AMD_CG_SUPPORT_GFX_3D_CGCG |
1180 AMD_CG_SUPPORT_GFX_3D_CGLS |
1181 AMD_CG_SUPPORT_GFX_CGCG |
1182 AMD_CG_SUPPORT_GFX_CGLS |
1183 AMD_CG_SUPPORT_BIF_MGCG |
1184 AMD_CG_SUPPORT_BIF_LS |
1185 AMD_CG_SUPPORT_HDP_MGCG |
1186 AMD_CG_SUPPORT_HDP_LS |
1187 AMD_CG_SUPPORT_DRM_MGCG |
1188 AMD_CG_SUPPORT_DRM_LS |
1189 AMD_CG_SUPPORT_ROM_MGCG |
1190 AMD_CG_SUPPORT_MC_MGCG |
1191 AMD_CG_SUPPORT_MC_LS |
1192 AMD_CG_SUPPORT_SDMA_MGCG |
1193 AMD_CG_SUPPORT_SDMA_LS |
1194 AMD_CG_SUPPORT_VCN_MGCG;
1195
1196 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1197 }
1198 break;
1199 case CHIP_ARCTURUS:
1200 adev->asic_funcs = &vega20_asic_funcs;
1201 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1202 AMD_CG_SUPPORT_GFX_MGLS |
1203 AMD_CG_SUPPORT_GFX_CGCG |
1204 AMD_CG_SUPPORT_GFX_CGLS |
1205 AMD_CG_SUPPORT_GFX_CP_LS |
1206 AMD_CG_SUPPORT_HDP_MGCG |
1207 AMD_CG_SUPPORT_HDP_LS |
1208 AMD_CG_SUPPORT_SDMA_MGCG |
1209 AMD_CG_SUPPORT_SDMA_LS |
1210 AMD_CG_SUPPORT_MC_MGCG |
1211 AMD_CG_SUPPORT_MC_LS |
1212 AMD_CG_SUPPORT_IH_CG |
1213 AMD_CG_SUPPORT_VCN_MGCG |
1214 AMD_CG_SUPPORT_JPEG_MGCG;
1215 adev->pg_flags = 0;
1216 adev->external_rev_id = adev->rev_id + 0x32;
1217 break;
1218 case CHIP_RENOIR:
1219 adev->asic_funcs = &soc15_asic_funcs;
1220 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1221 AMD_CG_SUPPORT_GFX_MGLS |
1222 AMD_CG_SUPPORT_GFX_3D_CGCG |
1223 AMD_CG_SUPPORT_GFX_3D_CGLS |
1224 AMD_CG_SUPPORT_GFX_CGCG |
1225 AMD_CG_SUPPORT_GFX_CGLS |
1226 AMD_CG_SUPPORT_GFX_CP_LS |
1227 AMD_CG_SUPPORT_MC_MGCG |
1228 AMD_CG_SUPPORT_MC_LS |
1229 AMD_CG_SUPPORT_SDMA_MGCG |
1230 AMD_CG_SUPPORT_SDMA_LS |
1231 AMD_CG_SUPPORT_BIF_LS |
1232 AMD_CG_SUPPORT_HDP_LS |
1233 AMD_CG_SUPPORT_ROM_MGCG |
1234 AMD_CG_SUPPORT_VCN_MGCG |
1235 AMD_CG_SUPPORT_JPEG_MGCG |
1236 AMD_CG_SUPPORT_IH_CG |
1237 AMD_CG_SUPPORT_ATHUB_LS |
1238 AMD_CG_SUPPORT_ATHUB_MGCG |
1239 AMD_CG_SUPPORT_DF_MGCG;
1240 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1241 AMD_PG_SUPPORT_VCN |
1242 AMD_PG_SUPPORT_JPEG |
1243 AMD_PG_SUPPORT_VCN_DPG;
1244 adev->external_rev_id = adev->rev_id + 0x91;
1245 break;
1246 default:
1247 /* FIXME: not supported yet */
1248 return -EINVAL;
1249 }
1250
1251 if (amdgpu_sriov_vf(adev)) {
1252 amdgpu_virt_init_setting(adev);
1253 xgpu_ai_mailbox_set_irq_funcs(adev);
1254 }
1255
1256 return 0;
1257}
1258
1259static int soc15_common_late_init(void *handle)
1260{
1261 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1262 int r = 0;
1263
1264 if (amdgpu_sriov_vf(adev))
1265 xgpu_ai_mailbox_get_irq(adev);
1266
1267 if (adev->nbio.funcs->ras_late_init)
1268 r = adev->nbio.funcs->ras_late_init(adev);
1269
1270 return r;
1271}
1272
1273static int soc15_common_sw_init(void *handle)
1274{
1275 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1276
1277 if (amdgpu_sriov_vf(adev))
1278 xgpu_ai_mailbox_add_irq_id(adev);
1279
1280 adev->df.funcs->sw_init(adev);
1281
1282 return 0;
1283}
1284
1285static int soc15_common_sw_fini(void *handle)
1286{
1287 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1288
1289 amdgpu_nbio_ras_fini(adev);
1290 adev->df.funcs->sw_fini(adev);
1291 return 0;
1292}
1293
1294static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1295{
1296 int i;
1297 struct amdgpu_ring *ring;
1298
1299 /* sdma/ih doorbell range are programed by hypervisor */
1300 if (!amdgpu_sriov_vf(adev)) {
1301 for (i = 0; i < adev->sdma.num_instances; i++) {
1302 ring = &adev->sdma.instance[i].ring;
1303 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1304 ring->use_doorbell, ring->doorbell_index,
1305 adev->doorbell_index.sdma_doorbell_range);
1306 }
1307
1308 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1309 adev->irq.ih.doorbell_index);
1310 }
1311}
1312
1313static int soc15_common_hw_init(void *handle)
1314{
1315 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1316
1317 /* enable pcie gen2/3 link */
1318 soc15_pcie_gen3_enable(adev);
1319 /* enable aspm */
1320 soc15_program_aspm(adev);
1321 /* setup nbio registers */
1322 adev->nbio.funcs->init_registers(adev);
1323 /* remap HDP registers to a hole in mmio space,
1324 * for the purpose of expose those registers
1325 * to process space
1326 */
1327 if (adev->nbio.funcs->remap_hdp_registers)
1328 adev->nbio.funcs->remap_hdp_registers(adev);
1329
1330 /* enable the doorbell aperture */
1331 soc15_enable_doorbell_aperture(adev, true);
1332 /* HW doorbell routing policy: doorbell writing not
1333 * in SDMA/IH/MM/ACV range will be routed to CP. So
1334 * we need to init SDMA/IH/MM/ACV doorbell range prior
1335 * to CP ip block init and ring test.
1336 */
1337 soc15_doorbell_range_init(adev);
1338
1339 return 0;
1340}
1341
1342static int soc15_common_hw_fini(void *handle)
1343{
1344 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1345
1346 /* disable the doorbell aperture */
1347 soc15_enable_doorbell_aperture(adev, false);
1348 if (amdgpu_sriov_vf(adev))
1349 xgpu_ai_mailbox_put_irq(adev);
1350
1351 if (adev->nbio.ras_if &&
1352 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1353 if (adev->nbio.funcs->init_ras_controller_interrupt)
1354 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1355 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
1356 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1357 }
1358
1359 return 0;
1360}
1361
1362static int soc15_common_suspend(void *handle)
1363{
1364 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1365
1366 return soc15_common_hw_fini(adev);
1367}
1368
1369static int soc15_common_resume(void *handle)
1370{
1371 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1372
1373 return soc15_common_hw_init(adev);
1374}
1375
1376static bool soc15_common_is_idle(void *handle)
1377{
1378 return true;
1379}
1380
1381static int soc15_common_wait_for_idle(void *handle)
1382{
1383 return 0;
1384}
1385
1386static int soc15_common_soft_reset(void *handle)
1387{
1388 return 0;
1389}
1390
1391static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1392{
1393 uint32_t def, data;
1394
1395 if (adev->asic_type == CHIP_VEGA20 ||
1396 adev->asic_type == CHIP_ARCTURUS) {
1397 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1398
1399 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1400 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1401 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1402 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1403 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1404 else
1405 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1406 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1407 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1408 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1409
1410 if (def != data)
1411 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1412 } else {
1413 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1414
1415 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1416 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1417 else
1418 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1419
1420 if (def != data)
1421 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1422 }
1423}
1424
1425static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1426{
1427 uint32_t def, data;
1428
1429 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1430
1431 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1432 data &= ~(0x01000000 |
1433 0x02000000 |
1434 0x04000000 |
1435 0x08000000 |
1436 0x10000000 |
1437 0x20000000 |
1438 0x40000000 |
1439 0x80000000);
1440 else
1441 data |= (0x01000000 |
1442 0x02000000 |
1443 0x04000000 |
1444 0x08000000 |
1445 0x10000000 |
1446 0x20000000 |
1447 0x40000000 |
1448 0x80000000);
1449
1450 if (def != data)
1451 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1452}
1453
1454static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1455{
1456 uint32_t def, data;
1457
1458 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1459
1460 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1461 data |= 1;
1462 else
1463 data &= ~1;
1464
1465 if (def != data)
1466 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1467}
1468
1469static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1470 bool enable)
1471{
1472 uint32_t def, data;
1473
1474 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1475
1476 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1477 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1478 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1479 else
1480 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1481 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1482
1483 if (def != data)
1484 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1485}
1486
1487static int soc15_common_set_clockgating_state(void *handle,
1488 enum amd_clockgating_state state)
1489{
1490 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1491
1492 if (amdgpu_sriov_vf(adev))
1493 return 0;
1494
1495 switch (adev->asic_type) {
1496 case CHIP_VEGA10:
1497 case CHIP_VEGA12:
1498 case CHIP_VEGA20:
1499 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1500 state == AMD_CG_STATE_GATE);
1501 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1502 state == AMD_CG_STATE_GATE);
1503 soc15_update_hdp_light_sleep(adev,
1504 state == AMD_CG_STATE_GATE);
1505 soc15_update_drm_clock_gating(adev,
1506 state == AMD_CG_STATE_GATE);
1507 soc15_update_drm_light_sleep(adev,
1508 state == AMD_CG_STATE_GATE);
1509 soc15_update_rom_medium_grain_clock_gating(adev,
1510 state == AMD_CG_STATE_GATE);
1511 adev->df.funcs->update_medium_grain_clock_gating(adev,
1512 state == AMD_CG_STATE_GATE);
1513 break;
1514 case CHIP_RAVEN:
1515 case CHIP_RENOIR:
1516 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1517 state == AMD_CG_STATE_GATE);
1518 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1519 state == AMD_CG_STATE_GATE);
1520 soc15_update_hdp_light_sleep(adev,
1521 state == AMD_CG_STATE_GATE);
1522 soc15_update_drm_clock_gating(adev,
1523 state == AMD_CG_STATE_GATE);
1524 soc15_update_drm_light_sleep(adev,
1525 state == AMD_CG_STATE_GATE);
1526 soc15_update_rom_medium_grain_clock_gating(adev,
1527 state == AMD_CG_STATE_GATE);
1528 break;
1529 case CHIP_ARCTURUS:
1530 soc15_update_hdp_light_sleep(adev,
1531 state == AMD_CG_STATE_GATE);
1532 break;
1533 default:
1534 break;
1535 }
1536 return 0;
1537}
1538
1539static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1540{
1541 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1542 int data;
1543
1544 if (amdgpu_sriov_vf(adev))
1545 *flags = 0;
1546
1547 adev->nbio.funcs->get_clockgating_state(adev, flags);
1548
1549 /* AMD_CG_SUPPORT_HDP_LS */
1550 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1551 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1552 *flags |= AMD_CG_SUPPORT_HDP_LS;
1553
1554 /* AMD_CG_SUPPORT_DRM_MGCG */
1555 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1556 if (!(data & 0x01000000))
1557 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1558
1559 /* AMD_CG_SUPPORT_DRM_LS */
1560 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1561 if (data & 0x1)
1562 *flags |= AMD_CG_SUPPORT_DRM_LS;
1563
1564 /* AMD_CG_SUPPORT_ROM_MGCG */
1565 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1566 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1567 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1568
1569 adev->df.funcs->get_clockgating_state(adev, flags);
1570}
1571
1572static int soc15_common_set_powergating_state(void *handle,
1573 enum amd_powergating_state state)
1574{
1575 /* todo */
1576 return 0;
1577}
1578
1579const struct amd_ip_funcs soc15_common_ip_funcs = {
1580 .name = "soc15_common",
1581 .early_init = soc15_common_early_init,
1582 .late_init = soc15_common_late_init,
1583 .sw_init = soc15_common_sw_init,
1584 .sw_fini = soc15_common_sw_fini,
1585 .hw_init = soc15_common_hw_init,
1586 .hw_fini = soc15_common_hw_fini,
1587 .suspend = soc15_common_suspend,
1588 .resume = soc15_common_resume,
1589 .is_idle = soc15_common_is_idle,
1590 .wait_for_idle = soc15_common_wait_for_idle,
1591 .soft_reset = soc15_common_soft_reset,
1592 .set_clockgating_state = soc15_common_set_clockgating_state,
1593 .set_powergating_state = soc15_common_set_powergating_state,
1594 .get_clockgating_state= soc15_common_get_clockgating_state,
1595};