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1NVIDIA Tegra20 MC(Memory Controller)
2
3Required properties:
4- compatible : "nvidia,tegra20-mc-gart"
5- reg : Should contain 2 register ranges: physical base address and length of
6 the controller's registers and the GART aperture respectively.
7- clocks: Must contain an entry for each entry in clock-names.
8 See ../clocks/clock-bindings.txt for details.
9- clock-names: Must include the following entries:
10 - mc: the module's clock input
11- interrupts : Should contain MC General interrupt.
12- #reset-cells : Should be 1. This cell represents memory client module ID.
13 The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>
14 or in the TRM documentation.
15- #iommu-cells: Should be 0. This cell represents the number of cells in an
16 IOMMU specifier needed to encode an address. GART supports only a single
17 address space that is shared by all devices, therefore no additional
18 information needed for the address encoding.
19
20Example:
21 mc: memory-controller@7000f000 {
22 compatible = "nvidia,tegra20-mc-gart";
23 reg = <0x7000f000 0x400 /* controller registers */
24 0x58000000 0x02000000>; /* GART aperture */
25 clocks = <&tegra_car TEGRA20_CLK_MC>;
26 clock-names = "mc";
27 interrupts = <GIC_SPI 77 0x04>;
28 #reset-cells = <1>;
29 #iommu-cells = <0>;
30 };
31
32 video-codec@6001a000 {
33 compatible = "nvidia,tegra20-vde";
34 ...
35 resets = <&mc TEGRA20_MC_RESET_VDE>;
36 iommus = <&mc>;
37 };