tjh.dev
Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Xilinx Zynq MPSoC Firmware layer
4 *
5 * Copyright (C) 2014-2019 Xilinx
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
11 */
12
13#ifndef __FIRMWARE_ZYNQMP_H__
14#define __FIRMWARE_ZYNQMP_H__
15
16#define ZYNQMP_PM_VERSION_MAJOR 1
17#define ZYNQMP_PM_VERSION_MINOR 0
18
19#define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
20 ZYNQMP_PM_VERSION_MINOR)
21
22#define ZYNQMP_TZ_VERSION_MAJOR 1
23#define ZYNQMP_TZ_VERSION_MINOR 0
24
25#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
26 ZYNQMP_TZ_VERSION_MINOR)
27
28/* SMC SIP service Call Function Identifier Prefix */
29#define PM_SIP_SVC 0xC2000000
30#define PM_GET_TRUSTZONE_VERSION 0xa03
31#define PM_SET_SUSPEND_MODE 0xa02
32#define GET_CALLBACK_DATA 0xa01
33
34/* Number of 32bits values in payload */
35#define PAYLOAD_ARG_CNT 4U
36
37/* Number of arguments for a callback */
38#define CB_ARG_CNT 4
39
40/* Payload size (consists of callback API ID + arguments) */
41#define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
42
43#define ZYNQMP_PM_MAX_QOS 100U
44
45/* Node capabilities */
46#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
47#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
48#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
49#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
50
51/* Feature check status */
52#define PM_FEATURE_INVALID -1
53#define PM_FEATURE_UNCHECKED 0
54
55/*
56 * Firmware FPGA Manager flags
57 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
58 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
59 */
60#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
61#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
62
63enum pm_api_id {
64 PM_GET_API_VERSION = 1,
65 PM_REQUEST_NODE = 13,
66 PM_RELEASE_NODE,
67 PM_SET_REQUIREMENT,
68 PM_RESET_ASSERT = 17,
69 PM_RESET_GET_STATUS,
70 PM_PM_INIT_FINALIZE = 21,
71 PM_FPGA_LOAD,
72 PM_FPGA_GET_STATUS,
73 PM_GET_CHIPID = 24,
74 PM_IOCTL = 34,
75 PM_QUERY_DATA,
76 PM_CLOCK_ENABLE,
77 PM_CLOCK_DISABLE,
78 PM_CLOCK_GETSTATE,
79 PM_CLOCK_SETDIVIDER,
80 PM_CLOCK_GETDIVIDER,
81 PM_CLOCK_SETRATE,
82 PM_CLOCK_GETRATE,
83 PM_CLOCK_SETPARENT,
84 PM_CLOCK_GETPARENT,
85 PM_FEATURE_CHECK = 63,
86 PM_API_MAX,
87};
88
89/* PMU-FW return status codes */
90enum pm_ret_status {
91 XST_PM_SUCCESS = 0,
92 XST_PM_NO_FEATURE = 19,
93 XST_PM_INTERNAL = 2000,
94 XST_PM_CONFLICT,
95 XST_PM_NO_ACCESS,
96 XST_PM_INVALID_NODE,
97 XST_PM_DOUBLE_REQ,
98 XST_PM_ABORT_SUSPEND,
99 XST_PM_MULT_USER = 2008,
100};
101
102enum pm_ioctl_id {
103 IOCTL_SET_SD_TAPDELAY = 7,
104 IOCTL_SET_PLL_FRAC_MODE,
105 IOCTL_GET_PLL_FRAC_MODE,
106 IOCTL_SET_PLL_FRAC_DATA,
107 IOCTL_GET_PLL_FRAC_DATA,
108};
109
110enum pm_query_id {
111 PM_QID_INVALID,
112 PM_QID_CLOCK_GET_NAME,
113 PM_QID_CLOCK_GET_TOPOLOGY,
114 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
115 PM_QID_CLOCK_GET_PARENTS,
116 PM_QID_CLOCK_GET_ATTRIBUTES,
117 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
118 PM_QID_CLOCK_GET_MAX_DIVISOR,
119};
120
121enum zynqmp_pm_reset_action {
122 PM_RESET_ACTION_RELEASE,
123 PM_RESET_ACTION_ASSERT,
124 PM_RESET_ACTION_PULSE,
125};
126
127enum zynqmp_pm_reset {
128 ZYNQMP_PM_RESET_START = 1000,
129 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
130 ZYNQMP_PM_RESET_PCIE_BRIDGE,
131 ZYNQMP_PM_RESET_PCIE_CTRL,
132 ZYNQMP_PM_RESET_DP,
133 ZYNQMP_PM_RESET_SWDT_CRF,
134 ZYNQMP_PM_RESET_AFI_FM5,
135 ZYNQMP_PM_RESET_AFI_FM4,
136 ZYNQMP_PM_RESET_AFI_FM3,
137 ZYNQMP_PM_RESET_AFI_FM2,
138 ZYNQMP_PM_RESET_AFI_FM1,
139 ZYNQMP_PM_RESET_AFI_FM0,
140 ZYNQMP_PM_RESET_GDMA,
141 ZYNQMP_PM_RESET_GPU_PP1,
142 ZYNQMP_PM_RESET_GPU_PP0,
143 ZYNQMP_PM_RESET_GPU,
144 ZYNQMP_PM_RESET_GT,
145 ZYNQMP_PM_RESET_SATA,
146 ZYNQMP_PM_RESET_ACPU3_PWRON,
147 ZYNQMP_PM_RESET_ACPU2_PWRON,
148 ZYNQMP_PM_RESET_ACPU1_PWRON,
149 ZYNQMP_PM_RESET_ACPU0_PWRON,
150 ZYNQMP_PM_RESET_APU_L2,
151 ZYNQMP_PM_RESET_ACPU3,
152 ZYNQMP_PM_RESET_ACPU2,
153 ZYNQMP_PM_RESET_ACPU1,
154 ZYNQMP_PM_RESET_ACPU0,
155 ZYNQMP_PM_RESET_DDR,
156 ZYNQMP_PM_RESET_APM_FPD,
157 ZYNQMP_PM_RESET_SOFT,
158 ZYNQMP_PM_RESET_GEM0,
159 ZYNQMP_PM_RESET_GEM1,
160 ZYNQMP_PM_RESET_GEM2,
161 ZYNQMP_PM_RESET_GEM3,
162 ZYNQMP_PM_RESET_QSPI,
163 ZYNQMP_PM_RESET_UART0,
164 ZYNQMP_PM_RESET_UART1,
165 ZYNQMP_PM_RESET_SPI0,
166 ZYNQMP_PM_RESET_SPI1,
167 ZYNQMP_PM_RESET_SDIO0,
168 ZYNQMP_PM_RESET_SDIO1,
169 ZYNQMP_PM_RESET_CAN0,
170 ZYNQMP_PM_RESET_CAN1,
171 ZYNQMP_PM_RESET_I2C0,
172 ZYNQMP_PM_RESET_I2C1,
173 ZYNQMP_PM_RESET_TTC0,
174 ZYNQMP_PM_RESET_TTC1,
175 ZYNQMP_PM_RESET_TTC2,
176 ZYNQMP_PM_RESET_TTC3,
177 ZYNQMP_PM_RESET_SWDT_CRL,
178 ZYNQMP_PM_RESET_NAND,
179 ZYNQMP_PM_RESET_ADMA,
180 ZYNQMP_PM_RESET_GPIO,
181 ZYNQMP_PM_RESET_IOU_CC,
182 ZYNQMP_PM_RESET_TIMESTAMP,
183 ZYNQMP_PM_RESET_RPU_R50,
184 ZYNQMP_PM_RESET_RPU_R51,
185 ZYNQMP_PM_RESET_RPU_AMBA,
186 ZYNQMP_PM_RESET_OCM,
187 ZYNQMP_PM_RESET_RPU_PGE,
188 ZYNQMP_PM_RESET_USB0_CORERESET,
189 ZYNQMP_PM_RESET_USB1_CORERESET,
190 ZYNQMP_PM_RESET_USB0_HIBERRESET,
191 ZYNQMP_PM_RESET_USB1_HIBERRESET,
192 ZYNQMP_PM_RESET_USB0_APB,
193 ZYNQMP_PM_RESET_USB1_APB,
194 ZYNQMP_PM_RESET_IPI,
195 ZYNQMP_PM_RESET_APM_LPD,
196 ZYNQMP_PM_RESET_RTC,
197 ZYNQMP_PM_RESET_SYSMON,
198 ZYNQMP_PM_RESET_AFI_FM6,
199 ZYNQMP_PM_RESET_LPD_SWDT,
200 ZYNQMP_PM_RESET_FPD,
201 ZYNQMP_PM_RESET_RPU_DBG1,
202 ZYNQMP_PM_RESET_RPU_DBG0,
203 ZYNQMP_PM_RESET_DBG_LPD,
204 ZYNQMP_PM_RESET_DBG_FPD,
205 ZYNQMP_PM_RESET_APLL,
206 ZYNQMP_PM_RESET_DPLL,
207 ZYNQMP_PM_RESET_VPLL,
208 ZYNQMP_PM_RESET_IOPLL,
209 ZYNQMP_PM_RESET_RPLL,
210 ZYNQMP_PM_RESET_GPO3_PL_0,
211 ZYNQMP_PM_RESET_GPO3_PL_1,
212 ZYNQMP_PM_RESET_GPO3_PL_2,
213 ZYNQMP_PM_RESET_GPO3_PL_3,
214 ZYNQMP_PM_RESET_GPO3_PL_4,
215 ZYNQMP_PM_RESET_GPO3_PL_5,
216 ZYNQMP_PM_RESET_GPO3_PL_6,
217 ZYNQMP_PM_RESET_GPO3_PL_7,
218 ZYNQMP_PM_RESET_GPO3_PL_8,
219 ZYNQMP_PM_RESET_GPO3_PL_9,
220 ZYNQMP_PM_RESET_GPO3_PL_10,
221 ZYNQMP_PM_RESET_GPO3_PL_11,
222 ZYNQMP_PM_RESET_GPO3_PL_12,
223 ZYNQMP_PM_RESET_GPO3_PL_13,
224 ZYNQMP_PM_RESET_GPO3_PL_14,
225 ZYNQMP_PM_RESET_GPO3_PL_15,
226 ZYNQMP_PM_RESET_GPO3_PL_16,
227 ZYNQMP_PM_RESET_GPO3_PL_17,
228 ZYNQMP_PM_RESET_GPO3_PL_18,
229 ZYNQMP_PM_RESET_GPO3_PL_19,
230 ZYNQMP_PM_RESET_GPO3_PL_20,
231 ZYNQMP_PM_RESET_GPO3_PL_21,
232 ZYNQMP_PM_RESET_GPO3_PL_22,
233 ZYNQMP_PM_RESET_GPO3_PL_23,
234 ZYNQMP_PM_RESET_GPO3_PL_24,
235 ZYNQMP_PM_RESET_GPO3_PL_25,
236 ZYNQMP_PM_RESET_GPO3_PL_26,
237 ZYNQMP_PM_RESET_GPO3_PL_27,
238 ZYNQMP_PM_RESET_GPO3_PL_28,
239 ZYNQMP_PM_RESET_GPO3_PL_29,
240 ZYNQMP_PM_RESET_GPO3_PL_30,
241 ZYNQMP_PM_RESET_GPO3_PL_31,
242 ZYNQMP_PM_RESET_RPU_LS,
243 ZYNQMP_PM_RESET_PS_ONLY,
244 ZYNQMP_PM_RESET_PL,
245 ZYNQMP_PM_RESET_PS_PL0,
246 ZYNQMP_PM_RESET_PS_PL1,
247 ZYNQMP_PM_RESET_PS_PL2,
248 ZYNQMP_PM_RESET_PS_PL3,
249 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
250};
251
252enum zynqmp_pm_suspend_reason {
253 SUSPEND_POWER_REQUEST = 201,
254 SUSPEND_ALERT,
255 SUSPEND_SYSTEM_SHUTDOWN,
256};
257
258enum zynqmp_pm_request_ack {
259 ZYNQMP_PM_REQUEST_ACK_NO = 1,
260 ZYNQMP_PM_REQUEST_ACK_BLOCKING,
261 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
262};
263
264enum pm_node_id {
265 NODE_SD_0 = 39,
266 NODE_SD_1,
267};
268
269enum tap_delay_type {
270 PM_TAPDELAY_INPUT = 0,
271 PM_TAPDELAY_OUTPUT,
272};
273
274/**
275 * struct zynqmp_pm_query_data - PM query data
276 * @qid: query ID
277 * @arg1: Argument 1 of query data
278 * @arg2: Argument 2 of query data
279 * @arg3: Argument 3 of query data
280 */
281struct zynqmp_pm_query_data {
282 u32 qid;
283 u32 arg1;
284 u32 arg2;
285 u32 arg3;
286};
287
288struct zynqmp_eemi_ops {
289 int (*get_api_version)(u32 *version);
290 int (*get_chipid)(u32 *idcode, u32 *version);
291 int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
292 int (*fpga_get_status)(u32 *value);
293 int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
294 int (*clock_enable)(u32 clock_id);
295 int (*clock_disable)(u32 clock_id);
296 int (*clock_getstate)(u32 clock_id, u32 *state);
297 int (*clock_setdivider)(u32 clock_id, u32 divider);
298 int (*clock_getdivider)(u32 clock_id, u32 *divider);
299 int (*clock_setrate)(u32 clock_id, u64 rate);
300 int (*clock_getrate)(u32 clock_id, u64 *rate);
301 int (*clock_setparent)(u32 clock_id, u32 parent_id);
302 int (*clock_getparent)(u32 clock_id, u32 *parent_id);
303 int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
304 int (*reset_assert)(const enum zynqmp_pm_reset reset,
305 const enum zynqmp_pm_reset_action assert_flag);
306 int (*reset_get_status)(const enum zynqmp_pm_reset reset, u32 *status);
307 int (*init_finalize)(void);
308 int (*set_suspend_mode)(u32 mode);
309 int (*request_node)(const u32 node,
310 const u32 capabilities,
311 const u32 qos,
312 const enum zynqmp_pm_request_ack ack);
313 int (*release_node)(const u32 node);
314 int (*set_requirement)(const u32 node,
315 const u32 capabilities,
316 const u32 qos,
317 const enum zynqmp_pm_request_ack ack);
318};
319
320int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
321 u32 arg2, u32 arg3, u32 *ret_payload);
322
323#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
324const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
325#else
326static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
327{
328 return ERR_PTR(-ENODEV);
329}
330#endif
331
332#endif /* __FIRMWARE_ZYNQMP_H__ */