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1NXP i.MX Messaging Unit (MU)
2--------------------------------------------------------------------
3
4The Messaging Unit module enables two processors within the SoC to
5communicate and coordinate by passing messages (e.g. data, status
6and control) through the MU interface. The MU also provides the ability
7for one processor to signal the other processor using interrupts.
8
9Because the MU manages the messaging between processors, the MU uses
10different clocks (from each side of the different peripheral buses).
11Therefore, the MU must synchronize the accesses from one side to the
12other. The MU accomplishes synchronization using two sets of matching
13registers (Processor A-facing, Processor B-facing).
14
15Messaging Unit Device Node:
16=============================
17
18Required properties:
19-------------------
20- compatible : should be "fsl,<chip>-mu", the supported chips include
21 imx6sx, imx7s, imx8qxp, imx8qm.
22 The "fsl,imx6sx-mu" compatible is seen as generic and should
23 be included together with SoC specific compatible.
24 There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu"
25 compatible to support it.
26- reg : Should contain the registers location and length
27- interrupts : Interrupt number. The interrupt specifier format depends
28 on the interrupt controller parent.
29- #mbox-cells: Must be 2.
30 <&phandle type channel>
31 phandle : Label name of controller
32 type : Channel type
33 channel : Channel number
34
35 This MU support 4 type of unidirectional channels, each type
36 has 4 channels. A total of 16 channels. Following types are
37 supported:
38 0 - TX channel with 32bit transmit register and IRQ transmit
39 acknowledgment support.
40 1 - RX channel with 32bit receive register and IRQ support
41 2 - TX doorbell channel. Without own register and no ACK support.
42 3 - RX doorbell channel.
43
44Optional properties:
45-------------------
46- clocks : phandle to the input clock.
47- fsl,mu-side-b : Should be set for side B MU.
48
49Examples:
50--------
51lsio_mu0: mailbox@5d1b0000 {
52 compatible = "fsl,imx8qxp-mu";
53 reg = <0x0 0x5d1b0000 0x0 0x10000>;
54 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
55 #mbox-cells = <2>;
56};