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1/*
2 * Copyright 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef DRM_FOURCC_H
25#define DRM_FOURCC_H
26
27#include "drm.h"
28
29#if defined(__cplusplus)
30extern "C" {
31#endif
32
33/**
34 * DOC: overview
35 *
36 * In the DRM subsystem, framebuffer pixel formats are described using the
37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
38 * fourcc code, a Format Modifier may optionally be provided, in order to
39 * further describe the buffer's format - for example tiling or compression.
40 *
41 * Format Modifiers
42 * ----------------
43 *
44 * Format modifiers are used in conjunction with a fourcc code, forming a
45 * unique fourcc:modifier pair. This format:modifier pair must fully define the
46 * format and data layout of the buffer, and should be the only way to describe
47 * that particular buffer.
48 *
49 * Having multiple fourcc:modifier pairs which describe the same layout should
50 * be avoided, as such aliases run the risk of different drivers exposing
51 * different names for the same data format, forcing userspace to understand
52 * that they are aliases.
53 *
54 * Format modifiers may change any property of the buffer, including the number
55 * of planes and/or the required allocation size. Format modifiers are
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * modifier is specific to the modifer being used. For example, some modifiers
58 * may preserve meaning - such as number of planes - from the fourcc code,
59 * whereas others may not.
60 *
61 * Vendors should document their modifier usage in as much detail as
62 * possible, to ensure maximum compatibility across devices, drivers and
63 * applications.
64 *
65 * The authoritative list of format modifier codes is found in
66 * `include/uapi/drm/drm_fourcc.h`
67 */
68
69#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
70 ((__u32)(c) << 16) | ((__u32)(d) << 24))
71
72#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
73
74/* Reserve 0 for the invalid format specifier */
75#define DRM_FORMAT_INVALID 0
76
77/* color index */
78#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
79
80/* 8 bpp Red */
81#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
82
83/* 16 bpp Red */
84#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
85
86/* 16 bpp RG */
87#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
88#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
89
90/* 32 bpp RG */
91#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
92#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
93
94/* 8 bpp RGB */
95#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
96#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
97
98/* 16 bpp RGB */
99#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
100#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
101#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
102#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
103
104#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
105#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
106#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
107#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
108
109#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
110#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
111#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
112#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
113
114#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
115#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
116#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
117#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
118
119#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
120#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
121
122/* 24 bpp RGB */
123#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
124#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
125
126/* 32 bpp RGB */
127#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
128#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
129#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
130#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
131
132#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
133#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
134#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
135#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
136
137#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
138#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
139#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
140#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
141
142#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
143#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
144#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
145#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
146
147/*
148 * Floating point 64bpp RGB
149 * IEEE 754-2008 binary16 half-precision float
150 * [15:0] sign:exponent:mantissa 1:5:10
151 */
152#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
153#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
154
155#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
156#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
157
158/* packed YCbCr */
159#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
160#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
161#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
162#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
163
164#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
165#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
166#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
167#define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
168
169/*
170 * packed Y2xx indicate for each component, xx valid data occupy msb
171 * 16-xx padding occupy lsb
172 */
173#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
174#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
175#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
176
177/*
178 * packed Y4xx indicate for each component, xx valid data occupy msb
179 * 16-xx padding occupy lsb except Y410
180 */
181#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
182#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
183#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
184
185#define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
186#define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
187#define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
188
189/*
190 * packed YCbCr420 2x2 tiled formats
191 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
192 */
193/* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
194#define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
195/* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
196#define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
197
198/* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
199#define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
200/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
201#define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
202
203/*
204 * 1-plane YUV 4:2:0
205 * In these formats, the component ordering is specified (Y, followed by U
206 * then V), but the exact Linear layout is undefined.
207 * These formats can only be used with a non-Linear modifier.
208 */
209#define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
210#define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
211
212/*
213 * 2 plane RGB + A
214 * index 0 = RGB plane, same format as the corresponding non _A8 format has
215 * index 1 = A plane, [7:0] A
216 */
217#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
218#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
219#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
220#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
221#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
222#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
223#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
224#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
225
226/*
227 * 2 plane YCbCr
228 * index 0 = Y plane, [7:0] Y
229 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
230 * or
231 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
232 */
233#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
234#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
235#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
236#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
237#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
238#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
239
240/*
241 * 2 plane YCbCr MSB aligned
242 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
243 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
244 */
245#define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
246
247/*
248 * 2 plane YCbCr MSB aligned
249 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
250 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
251 */
252#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
253
254/*
255 * 2 plane YCbCr MSB aligned
256 * index 0 = Y plane, [15:0] Y:x [12:4] little endian
257 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
258 */
259#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
260
261/*
262 * 2 plane YCbCr MSB aligned
263 * index 0 = Y plane, [15:0] Y little endian
264 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
265 */
266#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
267
268/*
269 * 3 plane YCbCr
270 * index 0: Y plane, [7:0] Y
271 * index 1: Cb plane, [7:0] Cb
272 * index 2: Cr plane, [7:0] Cr
273 * or
274 * index 1: Cr plane, [7:0] Cr
275 * index 2: Cb plane, [7:0] Cb
276 */
277#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
278#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
279#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
280#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
281#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
282#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
283#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
284#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
285#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
286#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
287
288
289/*
290 * Format Modifiers:
291 *
292 * Format modifiers describe, typically, a re-ordering or modification
293 * of the data in a plane of an FB. This can be used to express tiled/
294 * swizzled formats, or compression, or a combination of the two.
295 *
296 * The upper 8 bits of the format modifier are a vendor-id as assigned
297 * below. The lower 56 bits are assigned as vendor sees fit.
298 */
299
300/* Vendor Ids: */
301#define DRM_FORMAT_MOD_NONE 0
302#define DRM_FORMAT_MOD_VENDOR_NONE 0
303#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
304#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
305#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
306#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
307#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
308#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
309#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
310#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
311#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
312
313/* add more to the end as needed */
314
315#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
316
317#define fourcc_mod_code(vendor, val) \
318 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
319
320/*
321 * Format Modifier tokens:
322 *
323 * When adding a new token please document the layout with a code comment,
324 * similar to the fourcc codes above. drm_fourcc.h is considered the
325 * authoritative source for all of these.
326 */
327
328/*
329 * Invalid Modifier
330 *
331 * This modifier can be used as a sentinel to terminate the format modifiers
332 * list, or to initialize a variable with an invalid modifier. It might also be
333 * used to report an error back to userspace for certain APIs.
334 */
335#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
336
337/*
338 * Linear Layout
339 *
340 * Just plain linear layout. Note that this is different from no specifying any
341 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
342 * which tells the driver to also take driver-internal information into account
343 * and so might actually result in a tiled framebuffer.
344 */
345#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
346
347/* Intel framebuffer modifiers */
348
349/*
350 * Intel X-tiling layout
351 *
352 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
353 * in row-major layout. Within the tile bytes are laid out row-major, with
354 * a platform-dependent stride. On top of that the memory can apply
355 * platform-depending swizzling of some higher address bits into bit6.
356 *
357 * This format is highly platforms specific and not useful for cross-driver
358 * sharing. It exists since on a given platform it does uniquely identify the
359 * layout in a simple way for i915-specific userspace.
360 */
361#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
362
363/*
364 * Intel Y-tiling layout
365 *
366 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
367 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
368 * chunks column-major, with a platform-dependent height. On top of that the
369 * memory can apply platform-depending swizzling of some higher address bits
370 * into bit6.
371 *
372 * This format is highly platforms specific and not useful for cross-driver
373 * sharing. It exists since on a given platform it does uniquely identify the
374 * layout in a simple way for i915-specific userspace.
375 */
376#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
377
378/*
379 * Intel Yf-tiling layout
380 *
381 * This is a tiled layout using 4Kb tiles in row-major layout.
382 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
383 * are arranged in four groups (two wide, two high) with column-major layout.
384 * Each group therefore consits out of four 256 byte units, which are also laid
385 * out as 2x2 column-major.
386 * 256 byte units are made out of four 64 byte blocks of pixels, producing
387 * either a square block or a 2:1 unit.
388 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
389 * in pixel depends on the pixel depth.
390 */
391#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
392
393/*
394 * Intel color control surface (CCS) for render compression
395 *
396 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
397 * The main surface will be plane index 0 and must be Y/Yf-tiled,
398 * the CCS will be plane index 1.
399 *
400 * Each CCS tile matches a 1024x512 pixel area of the main surface.
401 * To match certain aspects of the 3D hardware the CCS is
402 * considered to be made up of normal 128Bx32 Y tiles, Thus
403 * the CCS pitch must be specified in multiples of 128 bytes.
404 *
405 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
406 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
407 * But that fact is not relevant unless the memory is accessed
408 * directly.
409 */
410#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
411#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
412
413/*
414 * Intel color control surfaces (CCS) for Gen-12 render compression.
415 *
416 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
417 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
418 * main surface. In other words, 4 bits in CCS map to a main surface cache
419 * line pair. The main surface pitch is required to be a multiple of four
420 * Y-tile widths.
421 */
422#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
423
424/*
425 * Intel color control surfaces (CCS) for Gen-12 media compression
426 *
427 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
428 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
429 * main surface. In other words, 4 bits in CCS map to a main surface cache
430 * line pair. The main surface pitch is required to be a multiple of four
431 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
432 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
433 * planes 2 and 3 for the respective CCS.
434 */
435#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
436
437/*
438 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
439 *
440 * Macroblocks are laid in a Z-shape, and each pixel data is following the
441 * standard NV12 style.
442 * As for NV12, an image is the result of two frame buffers: one for Y,
443 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
444 * Alignment requirements are (for each buffer):
445 * - multiple of 128 pixels for the width
446 * - multiple of 32 pixels for the height
447 *
448 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
449 */
450#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
451
452/*
453 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
454 *
455 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
456 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
457 * they correspond to their 16x16 luma block.
458 */
459#define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
460
461/*
462 * Qualcomm Compressed Format
463 *
464 * Refers to a compressed variant of the base format that is compressed.
465 * Implementation may be platform and base-format specific.
466 *
467 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
468 * Pixel data pitch/stride is aligned with macrotile width.
469 * Pixel data height is aligned with macrotile height.
470 * Entire pixel data buffer is aligned with 4k(bytes).
471 */
472#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
473
474/* Vivante framebuffer modifiers */
475
476/*
477 * Vivante 4x4 tiling layout
478 *
479 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
480 * layout.
481 */
482#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
483
484/*
485 * Vivante 64x64 super-tiling layout
486 *
487 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
488 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
489 * major layout.
490 *
491 * For more information: see
492 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
493 */
494#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
495
496/*
497 * Vivante 4x4 tiling layout for dual-pipe
498 *
499 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
500 * different base address. Offsets from the base addresses are therefore halved
501 * compared to the non-split tiled layout.
502 */
503#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
504
505/*
506 * Vivante 64x64 super-tiling layout for dual-pipe
507 *
508 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
509 * starts at a different base address. Offsets from the base addresses are
510 * therefore halved compared to the non-split super-tiled layout.
511 */
512#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
513
514/* NVIDIA frame buffer modifiers */
515
516/*
517 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
518 *
519 * Pixels are arranged in simple tiles of 16 x 16 bytes.
520 */
521#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
522
523/*
524 * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
525 *
526 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
527 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
528 *
529 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
530 *
531 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
532 * Valid values are:
533 *
534 * 0 == ONE_GOB
535 * 1 == TWO_GOBS
536 * 2 == FOUR_GOBS
537 * 3 == EIGHT_GOBS
538 * 4 == SIXTEEN_GOBS
539 * 5 == THIRTYTWO_GOBS
540 *
541 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
542 * in full detail.
543 */
544#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
545 fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
546
547#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
548 fourcc_mod_code(NVIDIA, 0x10)
549#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
550 fourcc_mod_code(NVIDIA, 0x11)
551#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
552 fourcc_mod_code(NVIDIA, 0x12)
553#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
554 fourcc_mod_code(NVIDIA, 0x13)
555#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
556 fourcc_mod_code(NVIDIA, 0x14)
557#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
558 fourcc_mod_code(NVIDIA, 0x15)
559
560/*
561 * Some Broadcom modifiers take parameters, for example the number of
562 * vertical lines in the image. Reserve the lower 32 bits for modifier
563 * type, and the next 24 bits for parameters. Top 8 bits are the
564 * vendor code.
565 */
566#define __fourcc_mod_broadcom_param_shift 8
567#define __fourcc_mod_broadcom_param_bits 48
568#define fourcc_mod_broadcom_code(val, params) \
569 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
570#define fourcc_mod_broadcom_param(m) \
571 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
572 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
573#define fourcc_mod_broadcom_mod(m) \
574 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
575 __fourcc_mod_broadcom_param_shift))
576
577/*
578 * Broadcom VC4 "T" format
579 *
580 * This is the primary layout that the V3D GPU can texture from (it
581 * can't do linear). The T format has:
582 *
583 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
584 * pixels at 32 bit depth.
585 *
586 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
587 * 16x16 pixels).
588 *
589 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
590 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
591 * they're (TR, BR, BL, TL), where bottom left is start of memory.
592 *
593 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
594 * tiles) or right-to-left (odd rows of 4k tiles).
595 */
596#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
597
598/*
599 * Broadcom SAND format
600 *
601 * This is the native format that the H.264 codec block uses. For VC4
602 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
603 *
604 * The image can be considered to be split into columns, and the
605 * columns are placed consecutively into memory. The width of those
606 * columns can be either 32, 64, 128, or 256 pixels, but in practice
607 * only 128 pixel columns are used.
608 *
609 * The pitch between the start of each column is set to optimally
610 * switch between SDRAM banks. This is passed as the number of lines
611 * of column width in the modifier (we can't use the stride value due
612 * to various core checks that look at it , so you should set the
613 * stride to width*cpp).
614 *
615 * Note that the column height for this format modifier is the same
616 * for all of the planes, assuming that each column contains both Y
617 * and UV. Some SAND-using hardware stores UV in a separate tiled
618 * image from Y to reduce the column height, which is not supported
619 * with these modifiers.
620 */
621
622#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
623 fourcc_mod_broadcom_code(2, v)
624#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
625 fourcc_mod_broadcom_code(3, v)
626#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
627 fourcc_mod_broadcom_code(4, v)
628#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
629 fourcc_mod_broadcom_code(5, v)
630
631#define DRM_FORMAT_MOD_BROADCOM_SAND32 \
632 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
633#define DRM_FORMAT_MOD_BROADCOM_SAND64 \
634 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
635#define DRM_FORMAT_MOD_BROADCOM_SAND128 \
636 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
637#define DRM_FORMAT_MOD_BROADCOM_SAND256 \
638 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
639
640/* Broadcom UIF format
641 *
642 * This is the common format for the current Broadcom multimedia
643 * blocks, including V3D 3.x and newer, newer video codecs, and
644 * displays.
645 *
646 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
647 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
648 * stored in columns, with padding between the columns to ensure that
649 * moving from one column to the next doesn't hit the same SDRAM page
650 * bank.
651 *
652 * To calculate the padding, it is assumed that each hardware block
653 * and the software driving it knows the platform's SDRAM page size,
654 * number of banks, and XOR address, and that it's identical between
655 * all blocks using the format. This tiling modifier will use XOR as
656 * necessary to reduce the padding. If a hardware block can't do XOR,
657 * the assumption is that a no-XOR tiling modifier will be created.
658 */
659#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
660
661/*
662 * Arm Framebuffer Compression (AFBC) modifiers
663 *
664 * AFBC is a proprietary lossless image compression protocol and format.
665 * It provides fine-grained random access and minimizes the amount of data
666 * transferred between IP blocks.
667 *
668 * AFBC has several features which may be supported and/or used, which are
669 * represented using bits in the modifier. Not all combinations are valid,
670 * and different devices or use-cases may support different combinations.
671 *
672 * Further information on the use of AFBC modifiers can be found in
673 * Documentation/gpu/afbc.rst
674 */
675
676/*
677 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
678 * modifiers) denote the category for modifiers. Currently we have only two
679 * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
680 * different categories.
681 */
682#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
683 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
684
685#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
686#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
687
688#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
689 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
690
691/*
692 * AFBC superblock size
693 *
694 * Indicates the superblock size(s) used for the AFBC buffer. The buffer
695 * size (in pixels) must be aligned to a multiple of the superblock size.
696 * Four lowest significant bits(LSBs) are reserved for block size.
697 *
698 * Where one superblock size is specified, it applies to all planes of the
699 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
700 * the first applies to the Luma plane and the second applies to the Chroma
701 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
702 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
703 */
704#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
705#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
706#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
707#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
708#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
709
710/*
711 * AFBC lossless colorspace transform
712 *
713 * Indicates that the buffer makes use of the AFBC lossless colorspace
714 * transform.
715 */
716#define AFBC_FORMAT_MOD_YTR (1ULL << 4)
717
718/*
719 * AFBC block-split
720 *
721 * Indicates that the payload of each superblock is split. The second
722 * half of the payload is positioned at a predefined offset from the start
723 * of the superblock payload.
724 */
725#define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
726
727/*
728 * AFBC sparse layout
729 *
730 * This flag indicates that the payload of each superblock must be stored at a
731 * predefined position relative to the other superblocks in the same AFBC
732 * buffer. This order is the same order used by the header buffer. In this mode
733 * each superblock is given the same amount of space as an uncompressed
734 * superblock of the particular format would require, rounding up to the next
735 * multiple of 128 bytes in size.
736 */
737#define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
738
739/*
740 * AFBC copy-block restrict
741 *
742 * Buffers with this flag must obey the copy-block restriction. The restriction
743 * is such that there are no copy-blocks referring across the border of 8x8
744 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
745 */
746#define AFBC_FORMAT_MOD_CBR (1ULL << 7)
747
748/*
749 * AFBC tiled layout
750 *
751 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
752 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
753 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
754 * larger bpp formats. The order between the tiles is scan line.
755 * When the tiled layout is used, the buffer size (in pixels) must be aligned
756 * to the tile size.
757 */
758#define AFBC_FORMAT_MOD_TILED (1ULL << 8)
759
760/*
761 * AFBC solid color blocks
762 *
763 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
764 * can be reduced if a whole superblock is a single color.
765 */
766#define AFBC_FORMAT_MOD_SC (1ULL << 9)
767
768/*
769 * AFBC double-buffer
770 *
771 * Indicates that the buffer is allocated in a layout safe for front-buffer
772 * rendering.
773 */
774#define AFBC_FORMAT_MOD_DB (1ULL << 10)
775
776/*
777 * AFBC buffer content hints
778 *
779 * Indicates that the buffer includes per-superblock content hints.
780 */
781#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
782
783/*
784 * Arm 16x16 Block U-Interleaved modifier
785 *
786 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
787 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
788 * in the block are reordered.
789 */
790#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
791 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
792
793/*
794 * Allwinner tiled modifier
795 *
796 * This tiling mode is implemented by the VPU found on all Allwinner platforms,
797 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
798 * planes.
799 *
800 * With this tiling, the luminance samples are disposed in tiles representing
801 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
802 * The pixel order in each tile is linear and the tiles are disposed linearly,
803 * both in row-major order.
804 */
805#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
806
807#if defined(__cplusplus)
808}
809#endif
810
811#endif /* DRM_FOURCC_H */