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1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Multimedia Clock & Reset Controller Binding
8
9maintainers:
10 - Jeffrey Hugo <jhugo@codeaurora.org>
11 - Taniya Das <tdas@codeaurora.org>
12
13description: |
14 Qualcomm multimedia clock control module which supports the clocks, resets and
15 power domains.
16
17properties:
18 compatible :
19 enum:
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8660
23 - qcom,mmcc-msm8960
24 - qcom,mmcc-msm8974
25 - qcom,mmcc-msm8996
26 - qcom,mmcc-msm8998
27
28 clocks:
29 items:
30 - description: Board XO source
31 - description: Board sleep source
32 - description: Global PLL 0 clock
33 - description: DSI phy instance 0 dsi clock
34 - description: DSI phy instance 0 byte clock
35 - description: DSI phy instance 1 dsi clock
36 - description: DSI phy instance 1 byte clock
37 - description: HDMI phy PLL clock
38 - description: DisplayPort phy PLL vco clock
39 - description: DisplayPort phy PLL link clock
40
41 clock-names:
42 items:
43 - const: xo
44 - const: sleep
45 - const: gpll0
46 - const: dsi0dsi
47 - const: dsi0byte
48 - const: dsi1dsi
49 - const: dsi1byte
50 - const: hdmipll
51 - const: dpvco
52 - const: dplink
53
54 '#clock-cells':
55 const: 1
56
57 '#reset-cells':
58 const: 1
59
60 '#power-domain-cells':
61 const: 1
62
63 reg:
64 maxItems: 1
65
66 protected-clocks:
67 description:
68 Protected clock specifier list as per common clock binding
69
70required:
71 - compatible
72 - reg
73 - '#clock-cells'
74 - '#reset-cells'
75 - '#power-domain-cells'
76
77if:
78 properties:
79 compatible:
80 contains:
81 const: qcom,mmcc-msm8998
82
83then:
84 required:
85 - clocks
86 - clock-names
87
88examples:
89 # Example for MMCC for MSM8960:
90 - |
91 clock-controller@4000000 {
92 compatible = "qcom,mmcc-msm8960";
93 reg = <0x4000000 0x1000>;
94 #clock-cells = <1>;
95 #reset-cells = <1>;
96 #power-domain-cells = <1>;
97 };
98...