tjh.dev
Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Cryptographic API.
4 *
5 * Support for OMAP AES HW ACCELERATOR defines
6 *
7 * Copyright (c) 2015 Texas Instruments Incorporated
8 */
9#ifndef __OMAP_AES_H__
10#define __OMAP_AES_H__
11
12#include <crypto/aes.h>
13#include <crypto/engine.h>
14
15#define DST_MAXBURST 4
16#define DMA_MIN (DST_MAXBURST * sizeof(u32))
17
18#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
19
20/*
21 * OMAP TRM gives bitfields as start:end, where start is the higher bit
22 * number. For example 7:0
23 */
24#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
25#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
26
27#define AES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
28 (((x) ^ 0x01) * 0x04))
29#define AES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
30
31#define AES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
32#define AES_REG_CTRL_CONTEXT_READY BIT(31)
33#define AES_REG_CTRL_CTR_WIDTH_MASK GENMASK(8, 7)
34#define AES_REG_CTRL_CTR_WIDTH_32 0
35#define AES_REG_CTRL_CTR_WIDTH_64 BIT(7)
36#define AES_REG_CTRL_CTR_WIDTH_96 BIT(8)
37#define AES_REG_CTRL_CTR_WIDTH_128 GENMASK(8, 7)
38#define AES_REG_CTRL_GCM GENMASK(17, 16)
39#define AES_REG_CTRL_CTR BIT(6)
40#define AES_REG_CTRL_CBC BIT(5)
41#define AES_REG_CTRL_KEY_SIZE GENMASK(4, 3)
42#define AES_REG_CTRL_DIRECTION BIT(2)
43#define AES_REG_CTRL_INPUT_READY BIT(1)
44#define AES_REG_CTRL_OUTPUT_READY BIT(0)
45#define AES_REG_CTRL_MASK GENMASK(24, 2)
46
47#define AES_REG_C_LEN_0 0x54
48#define AES_REG_C_LEN_1 0x58
49#define AES_REG_A_LEN 0x5C
50
51#define AES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
52#define AES_REG_TAG_N(dd, x) (0x70 + ((x) * 0x04))
53
54#define AES_REG_REV(dd) ((dd)->pdata->rev_ofs)
55
56#define AES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
57#define AES_REG_MASK_SIDLE BIT(6)
58#define AES_REG_MASK_START BIT(5)
59#define AES_REG_MASK_DMA_OUT_EN BIT(3)
60#define AES_REG_MASK_DMA_IN_EN BIT(2)
61#define AES_REG_MASK_SOFTRESET BIT(1)
62#define AES_REG_AUTOIDLE BIT(0)
63
64#define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04))
65
66#define AES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
67#define AES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
68#define AES_REG_IRQ_DATA_IN BIT(1)
69#define AES_REG_IRQ_DATA_OUT BIT(2)
70#define DEFAULT_TIMEOUT (5 * HZ)
71
72#define DEFAULT_AUTOSUSPEND_DELAY 1000
73
74#define FLAGS_MODE_MASK 0x001f
75#define FLAGS_ENCRYPT BIT(0)
76#define FLAGS_CBC BIT(1)
77#define FLAGS_CTR BIT(2)
78#define FLAGS_GCM BIT(3)
79#define FLAGS_RFC4106_GCM BIT(4)
80
81#define FLAGS_INIT BIT(5)
82#define FLAGS_FAST BIT(6)
83
84#define FLAGS_IN_DATA_ST_SHIFT 8
85#define FLAGS_OUT_DATA_ST_SHIFT 10
86#define FLAGS_ASSOC_DATA_ST_SHIFT 12
87
88#define AES_BLOCK_WORDS (AES_BLOCK_SIZE >> 2)
89
90struct omap_aes_gcm_result {
91 struct completion completion;
92 int err;
93};
94
95struct omap_aes_ctx {
96 struct crypto_engine_ctx enginectx;
97 int keylen;
98 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
99 u8 nonce[4];
100 struct crypto_sync_skcipher *fallback;
101};
102
103struct omap_aes_gcm_ctx {
104 struct omap_aes_ctx octx;
105 struct crypto_aes_ctx actx;
106};
107
108struct omap_aes_reqctx {
109 struct omap_aes_dev *dd;
110 unsigned long mode;
111 u8 iv[AES_BLOCK_SIZE];
112 u32 auth_tag[AES_BLOCK_SIZE / sizeof(u32)];
113};
114
115#define OMAP_AES_QUEUE_LENGTH 1
116#define OMAP_AES_CACHE_SIZE 0
117
118struct omap_aes_algs_info {
119 struct skcipher_alg *algs_list;
120 unsigned int size;
121 unsigned int registered;
122};
123
124struct omap_aes_aead_algs {
125 struct aead_alg *algs_list;
126 unsigned int size;
127 unsigned int registered;
128};
129
130struct omap_aes_pdata {
131 struct omap_aes_algs_info *algs_info;
132 unsigned int algs_info_size;
133 struct omap_aes_aead_algs *aead_algs_info;
134
135 void (*trigger)(struct omap_aes_dev *dd, int length);
136
137 u32 key_ofs;
138 u32 iv_ofs;
139 u32 ctrl_ofs;
140 u32 data_ofs;
141 u32 rev_ofs;
142 u32 mask_ofs;
143 u32 irq_enable_ofs;
144 u32 irq_status_ofs;
145
146 u32 dma_enable_in;
147 u32 dma_enable_out;
148 u32 dma_start;
149
150 u32 major_mask;
151 u32 major_shift;
152 u32 minor_mask;
153 u32 minor_shift;
154};
155
156struct omap_aes_dev {
157 struct list_head list;
158 unsigned long phys_base;
159 void __iomem *io_base;
160 struct omap_aes_ctx *ctx;
161 struct device *dev;
162 unsigned long flags;
163 int err;
164
165 struct tasklet_struct done_task;
166 struct aead_queue aead_queue;
167 spinlock_t lock;
168
169 struct skcipher_request *req;
170 struct aead_request *aead_req;
171 struct crypto_engine *engine;
172
173 /*
174 * total is used by PIO mode for book keeping so introduce
175 * variable total_save as need it to calc page_order
176 */
177 size_t total;
178 size_t total_save;
179 size_t assoc_len;
180 size_t authsize;
181
182 struct scatterlist *in_sg;
183 struct scatterlist *out_sg;
184
185 /* Buffers for copying for unaligned cases */
186 struct scatterlist in_sgl[2];
187 struct scatterlist out_sgl;
188 struct scatterlist *orig_out;
189
190 struct scatter_walk in_walk;
191 struct scatter_walk out_walk;
192 struct dma_chan *dma_lch_in;
193 struct dma_chan *dma_lch_out;
194 int in_sg_len;
195 int out_sg_len;
196 int pio_only;
197 const struct omap_aes_pdata *pdata;
198};
199
200u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset);
201void omap_aes_write(struct omap_aes_dev *dd, u32 offset, u32 value);
202struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx);
203int omap_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
204 unsigned int keylen);
205int omap_aes_4106gcm_setkey(struct crypto_aead *tfm, const u8 *key,
206 unsigned int keylen);
207int omap_aes_gcm_encrypt(struct aead_request *req);
208int omap_aes_gcm_decrypt(struct aead_request *req);
209int omap_aes_gcm_setauthsize(struct crypto_aead *tfm, unsigned int authsize);
210int omap_aes_4106gcm_encrypt(struct aead_request *req);
211int omap_aes_4106gcm_decrypt(struct aead_request *req);
212int omap_aes_4106gcm_setauthsize(struct crypto_aead *parent,
213 unsigned int authsize);
214int omap_aes_gcm_cra_init(struct crypto_aead *tfm);
215int omap_aes_write_ctrl(struct omap_aes_dev *dd);
216int omap_aes_crypt_dma_start(struct omap_aes_dev *dd);
217int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd);
218void omap_aes_gcm_dma_out_callback(void *data);
219void omap_aes_clear_copy_flags(struct omap_aes_dev *dd);
220
221#endif