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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2#ifndef _ASM_POWERPC_PROCESSOR_H
3#define _ASM_POWERPC_PROCESSOR_H
4
5/*
6 * Copyright (C) 2001 PPC 64 Team, IBM Corp
7 */
8
9#include <asm/reg.h>
10
11#ifdef CONFIG_VSX
12#define TS_FPRWIDTH 2
13
14#ifdef __BIG_ENDIAN__
15#define TS_FPROFFSET 0
16#define TS_VSRLOWOFFSET 1
17#else
18#define TS_FPROFFSET 1
19#define TS_VSRLOWOFFSET 0
20#endif
21
22#else
23#define TS_FPRWIDTH 1
24#define TS_FPROFFSET 0
25#endif
26
27#ifdef CONFIG_PPC64
28/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
29#define PPR_PRIORITY 3
30#ifdef __ASSEMBLY__
31#define DEFAULT_PPR (PPR_PRIORITY << 50)
32#else
33#define DEFAULT_PPR ((u64)PPR_PRIORITY << 50)
34#endif /* __ASSEMBLY__ */
35#endif /* CONFIG_PPC64 */
36
37#ifndef __ASSEMBLY__
38#include <linux/types.h>
39#include <linux/thread_info.h>
40#include <asm/ptrace.h>
41#include <asm/hw_breakpoint.h>
42
43/* We do _not_ want to define new machine types at all, those must die
44 * in favor of using the device-tree
45 * -- BenH.
46 */
47
48/* PREP sub-platform types. Unused */
49#define _PREP_Motorola 0x01 /* motorola prep */
50#define _PREP_Firm 0x02 /* firmworks prep */
51#define _PREP_IBM 0x00 /* ibm prep */
52#define _PREP_Bull 0x03 /* bull prep */
53
54/* CHRP sub-platform types. These are arbitrary */
55#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
56#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
57#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
58#define _CHRP_briq 0x07 /* TotalImpact's briQ */
59
60#if defined(__KERNEL__) && defined(CONFIG_PPC32)
61
62extern int _chrp_type;
63
64#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
65
66/* Macros for adjusting thread priority (hardware multi-threading) */
67#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
68#define HMT_low() asm volatile("or 1,1,1 # low priority")
69#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
70#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
71#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
72#define HMT_high() asm volatile("or 3,3,3 # high priority")
73
74#ifdef __KERNEL__
75
76#ifdef CONFIG_PPC64
77#include <asm/task_size_64.h>
78#else
79#include <asm/task_size_32.h>
80#endif
81
82struct task_struct;
83void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
84void release_thread(struct task_struct *);
85
86typedef struct {
87 unsigned long seg;
88} mm_segment_t;
89
90#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
91#define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
92
93/* FP and VSX 0-31 register set */
94struct thread_fp_state {
95 u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
96 u64 fpscr; /* Floating point status */
97};
98
99/* Complete AltiVec register set including VSCR */
100struct thread_vr_state {
101 vector128 vr[32] __attribute__((aligned(16)));
102 vector128 vscr __attribute__((aligned(16)));
103};
104
105struct debug_reg {
106#ifdef CONFIG_PPC_ADV_DEBUG_REGS
107 /*
108 * The following help to manage the use of Debug Control Registers
109 * om the BookE platforms.
110 */
111 uint32_t dbcr0;
112 uint32_t dbcr1;
113#ifdef CONFIG_BOOKE
114 uint32_t dbcr2;
115#endif
116 /*
117 * The stored value of the DBSR register will be the value at the
118 * last debug interrupt. This register can only be read from the
119 * user (will never be written to) and has value while helping to
120 * describe the reason for the last debug trap. Torez
121 */
122 uint32_t dbsr;
123 /*
124 * The following will contain addresses used by debug applications
125 * to help trace and trap on particular address locations.
126 * The bits in the Debug Control Registers above help define which
127 * of the following registers will contain valid data and/or addresses.
128 */
129 unsigned long iac1;
130 unsigned long iac2;
131#if CONFIG_PPC_ADV_DEBUG_IACS > 2
132 unsigned long iac3;
133 unsigned long iac4;
134#endif
135 unsigned long dac1;
136 unsigned long dac2;
137#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
138 unsigned long dvc1;
139 unsigned long dvc2;
140#endif
141#endif
142};
143
144struct thread_struct {
145 unsigned long ksp; /* Kernel stack pointer */
146
147#ifdef CONFIG_PPC64
148 unsigned long ksp_vsid;
149#endif
150 struct pt_regs *regs; /* Pointer to saved register state */
151 mm_segment_t addr_limit; /* for get_fs() validation */
152#ifdef CONFIG_BOOKE
153 /* BookE base exception scratch space; align on cacheline */
154 unsigned long normsave[8] ____cacheline_aligned;
155#endif
156#ifdef CONFIG_PPC32
157 void *pgdir; /* root of page-table tree */
158 unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
159#ifdef CONFIG_PPC_RTAS
160 unsigned long rtas_sp; /* stack pointer for when in RTAS */
161#endif
162#endif
163#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
164 unsigned long kuap; /* opened segments for user access */
165#endif
166#ifdef CONFIG_VMAP_STACK
167 unsigned long srr0;
168 unsigned long srr1;
169 unsigned long dar;
170 unsigned long dsisr;
171#endif
172 /* Debug Registers */
173 struct debug_reg debug;
174 struct thread_fp_state fp_state;
175 struct thread_fp_state *fp_save_area;
176 int fpexc_mode; /* floating-point exception mode */
177 unsigned int align_ctl; /* alignment handling control */
178#ifdef CONFIG_HAVE_HW_BREAKPOINT
179 struct perf_event *ptrace_bps[HBP_NUM];
180 /*
181 * Helps identify source of single-step exception and subsequent
182 * hw-breakpoint enablement
183 */
184 struct perf_event *last_hit_ubp;
185#endif /* CONFIG_HAVE_HW_BREAKPOINT */
186 struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
187 unsigned long trap_nr; /* last trap # on this thread */
188 u8 load_slb; /* Ages out SLB preload cache entries */
189 u8 load_fp;
190#ifdef CONFIG_ALTIVEC
191 u8 load_vec;
192 struct thread_vr_state vr_state;
193 struct thread_vr_state *vr_save_area;
194 unsigned long vrsave;
195 int used_vr; /* set if process has used altivec */
196#endif /* CONFIG_ALTIVEC */
197#ifdef CONFIG_VSX
198 /* VSR status */
199 int used_vsr; /* set if process has used VSX */
200#endif /* CONFIG_VSX */
201#ifdef CONFIG_SPE
202 unsigned long evr[32]; /* upper 32-bits of SPE regs */
203 u64 acc; /* Accumulator */
204 unsigned long spefscr; /* SPE & eFP status */
205 unsigned long spefscr_last; /* SPEFSCR value on last prctl
206 call or trap return */
207 int used_spe; /* set if process has used spe */
208#endif /* CONFIG_SPE */
209#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
210 u8 load_tm;
211 u64 tm_tfhar; /* Transaction fail handler addr */
212 u64 tm_texasr; /* Transaction exception & summary */
213 u64 tm_tfiar; /* Transaction fail instr address reg */
214 struct pt_regs ckpt_regs; /* Checkpointed registers */
215
216 unsigned long tm_tar;
217 unsigned long tm_ppr;
218 unsigned long tm_dscr;
219
220 /*
221 * Checkpointed FP and VSX 0-31 register set.
222 *
223 * When a transaction is active/signalled/scheduled etc., *regs is the
224 * most recent set of/speculated GPRs with ckpt_regs being the older
225 * checkpointed regs to which we roll back if transaction aborts.
226 *
227 * These are analogous to how ckpt_regs and pt_regs work
228 */
229 struct thread_fp_state ckfp_state; /* Checkpointed FP state */
230 struct thread_vr_state ckvr_state; /* Checkpointed VR state */
231 unsigned long ckvrsave; /* Checkpointed VRSAVE */
232#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
233#ifdef CONFIG_PPC_MEM_KEYS
234 unsigned long amr;
235 unsigned long iamr;
236 unsigned long uamor;
237#endif
238#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
239 void* kvm_shadow_vcpu; /* KVM internal data */
240#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
241#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
242 struct kvm_vcpu *kvm_vcpu;
243#endif
244#ifdef CONFIG_PPC64
245 unsigned long dscr;
246 unsigned long fscr;
247 /*
248 * This member element dscr_inherit indicates that the process
249 * has explicitly attempted and changed the DSCR register value
250 * for itself. Hence kernel wont use the default CPU DSCR value
251 * contained in the PACA structure anymore during process context
252 * switch. Once this variable is set, this behaviour will also be
253 * inherited to all the children of this process from that point
254 * onwards.
255 */
256 int dscr_inherit;
257 unsigned long tidr;
258#endif
259#ifdef CONFIG_PPC_BOOK3S_64
260 unsigned long tar;
261 unsigned long ebbrr;
262 unsigned long ebbhr;
263 unsigned long bescr;
264 unsigned long siar;
265 unsigned long sdar;
266 unsigned long sier;
267 unsigned long mmcr2;
268 unsigned mmcr0;
269
270 unsigned used_ebb;
271 unsigned int used_vas;
272#endif
273};
274
275#define ARCH_MIN_TASKALIGN 16
276
277#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
278#define INIT_SP_LIMIT ((unsigned long)&init_stack)
279
280#ifdef CONFIG_SPE
281#define SPEFSCR_INIT \
282 .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
283 .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
284#else
285#define SPEFSCR_INIT
286#endif
287
288#ifdef CONFIG_PPC32
289#define INIT_THREAD { \
290 .ksp = INIT_SP, \
291 .ksp_limit = INIT_SP_LIMIT, \
292 .addr_limit = KERNEL_DS, \
293 .pgdir = swapper_pg_dir, \
294 .fpexc_mode = MSR_FE0 | MSR_FE1, \
295 SPEFSCR_INIT \
296}
297#else
298#define INIT_THREAD { \
299 .ksp = INIT_SP, \
300 .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
301 .addr_limit = KERNEL_DS, \
302 .fpexc_mode = 0, \
303 .fscr = FSCR_TAR | FSCR_EBB \
304}
305#endif
306
307#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
308
309unsigned long get_wchan(struct task_struct *p);
310
311#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
312#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
313
314/* Get/set floating-point exception mode */
315#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
316#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
317
318extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
319extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
320
321#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
322#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
323
324extern int get_endian(struct task_struct *tsk, unsigned long adr);
325extern int set_endian(struct task_struct *tsk, unsigned int val);
326
327#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
328#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
329
330extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
331extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
332
333extern void load_fp_state(struct thread_fp_state *fp);
334extern void store_fp_state(struct thread_fp_state *fp);
335extern void load_vr_state(struct thread_vr_state *vr);
336extern void store_vr_state(struct thread_vr_state *vr);
337
338static inline unsigned int __unpack_fe01(unsigned long msr_bits)
339{
340 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
341}
342
343static inline unsigned long __pack_fe01(unsigned int fpmode)
344{
345 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
346}
347
348#ifdef CONFIG_PPC64
349#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
350
351#define spin_begin() HMT_low()
352
353#define spin_cpu_relax() barrier()
354
355#define spin_end() HMT_medium()
356
357#define spin_until_cond(cond) \
358do { \
359 if (unlikely(!(cond))) { \
360 spin_begin(); \
361 do { \
362 spin_cpu_relax(); \
363 } while (!(cond)); \
364 spin_end(); \
365 } \
366} while (0)
367
368#else
369#define cpu_relax() barrier()
370#endif
371
372/* Check that a certain kernel stack pointer is valid in task_struct p */
373int validate_sp(unsigned long sp, struct task_struct *p,
374 unsigned long nbytes);
375
376/*
377 * Prefetch macros.
378 */
379#define ARCH_HAS_PREFETCH
380#define ARCH_HAS_PREFETCHW
381#define ARCH_HAS_SPINLOCK_PREFETCH
382
383static inline void prefetch(const void *x)
384{
385 if (unlikely(!x))
386 return;
387
388 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
389}
390
391static inline void prefetchw(const void *x)
392{
393 if (unlikely(!x))
394 return;
395
396 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
397}
398
399#define spin_lock_prefetch(x) prefetchw(x)
400
401#define HAVE_ARCH_PICK_MMAP_LAYOUT
402
403#ifdef CONFIG_PPC64
404static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
405{
406 if (is_32)
407 return sp & 0x0ffffffffUL;
408 return sp;
409}
410#else
411static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
412{
413 return sp;
414}
415#endif
416
417/* asm stubs */
418extern unsigned long isa300_idle_stop_noloss(unsigned long psscr_val);
419extern unsigned long isa300_idle_stop_mayloss(unsigned long psscr_val);
420extern unsigned long isa206_idle_insn_mayloss(unsigned long type);
421#ifdef CONFIG_PPC_970_NAP
422extern void power4_idle_nap(void);
423#endif
424
425extern unsigned long cpuidle_disable;
426enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
427
428extern int powersave_nap; /* set if nap mode can be used in idle loop */
429
430extern void power7_idle_type(unsigned long type);
431extern void power9_idle_type(unsigned long stop_psscr_val,
432 unsigned long stop_psscr_mask);
433
434extern void flush_instruction_cache(void);
435extern void hard_reset_now(void);
436extern void poweroff_now(void);
437extern int fix_alignment(struct pt_regs *);
438extern void cvt_fd(float *from, double *to);
439extern void cvt_df(double *from, float *to);
440extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
441
442#ifdef CONFIG_PPC64
443/*
444 * We handle most unaligned accesses in hardware. On the other hand
445 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
446 * powers of 2 writes until it reaches sufficient alignment).
447 *
448 * Based on this we disable the IP header alignment in network drivers.
449 */
450#define NET_IP_ALIGN 0
451#endif
452
453#endif /* __KERNEL__ */
454#endif /* __ASSEMBLY__ */
455#endif /* _ASM_POWERPC_PROCESSOR_H */