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1Thine Electronics THC63LVD1024 LVDS decoder
2-------------------------------------------
3
4The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS streams
5to parallel data outputs. The chip supports single/dual input/output modes,
6handling up to two LVDS input streams and up to two digital CMOS/TTL outputs.
7
8Single or dual operation mode, output data mapping and DDR output modes are
9configured through input signals and the chip does not expose any control bus.
10
11Required properties:
12- compatible: Shall be "thine,thc63lvd1024"
13- vcc-supply: Power supply for TTL output, TTL CLOCKOUT signal, LVDS input,
14 PPL and digital circuitry
15
16Optional properties:
17- powerdown-gpios: Power down GPIO signal, pin name "/PDWN". Active low
18- oe-gpios: Output enable GPIO signal, pin name "OE". Active high
19
20The THC63LVD1024 video port connections are modeled according
21to OF graph bindings specified by Documentation/devicetree/bindings/graph.txt
22
23Required video port nodes:
24- port@0: First LVDS input port
25- port@2: First digital CMOS/TTL parallel output
26
27Optional video port nodes:
28- port@1: Second LVDS input port
29- port@3: Second digital CMOS/TTL parallel output
30
31The device can operate in single-link mode or dual-link mode. In single-link
32mode, all pixels are received on port@0, and port@1 shall not contain any
33endpoint. In dual-link mode, even-numbered pixels are received on port@0 and
34odd-numbered pixels on port@1, and both port@0 and port@1 shall contain
35endpoints.
36
37Example:
38--------
39
40 thc63lvd1024: lvds-decoder {
41 compatible = "thine,thc63lvd1024";
42
43 vcc-supply = <®_lvds_vcc>;
44 powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
45
46 ports {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 port@0 {
51 reg = <0>;
52
53 lvds_dec_in_0: endpoint {
54 remote-endpoint = <&lvds_out>;
55 };
56 };
57
58 port@2{
59 reg = <2>;
60
61 lvds_dec_out_2: endpoint {
62 remote-endpoint = <&adv7511_in>;
63 };
64 };
65 };
66 };