Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2015 Linaro Ltd.
4 */
5#ifndef __QCOM_SCM_H
6#define __QCOM_SCM_H
7
8#include <linux/err.h>
9#include <linux/types.h>
10#include <linux/cpumask.h>
11
12#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
13#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
14#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
15#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
16
17struct qcom_scm_hdcp_req {
18 u32 addr;
19 u32 val;
20};
21
22struct qcom_scm_vmperm {
23 int vmid;
24 int perm;
25};
26
27enum qcom_scm_ocmem_client {
28 QCOM_SCM_OCMEM_UNUSED_ID = 0x0,
29 QCOM_SCM_OCMEM_GRAPHICS_ID,
30 QCOM_SCM_OCMEM_VIDEO_ID,
31 QCOM_SCM_OCMEM_LP_AUDIO_ID,
32 QCOM_SCM_OCMEM_SENSORS_ID,
33 QCOM_SCM_OCMEM_OTHER_OS_ID,
34 QCOM_SCM_OCMEM_DEBUG_ID,
35};
36
37enum qcom_scm_sec_dev_id {
38 QCOM_SCM_MDSS_DEV_ID = 1,
39 QCOM_SCM_OCMEM_DEV_ID = 5,
40 QCOM_SCM_PCIE0_DEV_ID = 11,
41 QCOM_SCM_PCIE1_DEV_ID = 12,
42 QCOM_SCM_GFX_DEV_ID = 18,
43 QCOM_SCM_UFS_DEV_ID = 19,
44 QCOM_SCM_ICE_DEV_ID = 20,
45};
46
47#define QCOM_SCM_VMID_HLOS 0x3
48#define QCOM_SCM_VMID_MSS_MSA 0xF
49#define QCOM_SCM_VMID_WLAN 0x18
50#define QCOM_SCM_VMID_WLAN_CE 0x19
51#define QCOM_SCM_PERM_READ 0x4
52#define QCOM_SCM_PERM_WRITE 0x2
53#define QCOM_SCM_PERM_EXEC 0x1
54#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
55#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
56
57#if IS_ENABLED(CONFIG_QCOM_SCM)
58extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
59extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
60extern bool qcom_scm_is_available(void);
61extern bool qcom_scm_hdcp_available(void);
62extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
63 u32 *resp);
64extern bool qcom_scm_ocmem_lock_available(void);
65extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
66 u32 size, u32 mode);
67extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
68 u32 size);
69extern bool qcom_scm_pas_supported(u32 peripheral);
70extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
71 size_t size);
72extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
73 phys_addr_t size);
74extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
75extern int qcom_scm_pas_shutdown(u32 peripheral);
76extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
77 unsigned int *src,
78 const struct qcom_scm_vmperm *newvm,
79 unsigned int dest_cnt);
80extern void qcom_scm_cpu_power_down(u32 flags);
81extern u32 qcom_scm_get_version(void);
82extern int qcom_scm_set_remote_state(u32 state, u32 id);
83extern bool qcom_scm_restore_sec_cfg_available(void);
84extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
85extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
86extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
87extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
88extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
89extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
90#else
91
92#include <linux/errno.h>
93
94static inline
95int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
96{
97 return -ENODEV;
98}
99static inline
100int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
101{
102 return -ENODEV;
103}
104static inline bool qcom_scm_is_available(void) { return false; }
105static inline bool qcom_scm_hdcp_available(void) { return false; }
106static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
107 u32 *resp) { return -ENODEV; }
108static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
109static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
110 size_t size) { return -ENODEV; }
111static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
112 phys_addr_t size) { return -ENODEV; }
113static inline int
114qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
115static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
116static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
117 unsigned int *src,
118 const struct qcom_scm_vmperm *newvm,
119 unsigned int dest_cnt) { return -ENODEV; }
120static inline void qcom_scm_cpu_power_down(u32 flags) {}
121static inline u32 qcom_scm_get_version(void) { return 0; }
122static inline u32
123qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
124static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
125static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
126static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
127static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { return -ENODEV; }
128static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
129static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
130#endif
131#endif