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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Broadcom Starfighter2 private context
4 *
5 * Copyright (C) 2014, Broadcom Corporation
6 */
7
8#ifndef __BCM_SF2_H
9#define __BCM_SF2_H
10
11#include <linux/platform_device.h>
12#include <linux/kernel.h>
13#include <linux/io.h>
14#include <linux/spinlock.h>
15#include <linux/mutex.h>
16#include <linux/mii.h>
17#include <linux/ethtool.h>
18#include <linux/types.h>
19#include <linux/bitops.h>
20#include <linux/if_vlan.h>
21#include <linux/reset.h>
22
23#include <net/dsa.h>
24
25#include "bcm_sf2_regs.h"
26#include "b53/b53_priv.h"
27
28struct bcm_sf2_hw_params {
29 u16 top_rev;
30 u16 core_rev;
31 u16 gphy_rev;
32 u32 num_gphy;
33 u8 num_acb_queue;
34 u8 num_rgmii;
35 u8 num_ports;
36 u8 fcb_pause_override:1;
37 u8 acb_packets_inflight:1;
38};
39
40#define BCM_SF2_REGS_NAME {\
41 "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \
42}
43
44#define BCM_SF2_REGS_NUM 6
45
46struct bcm_sf2_port_status {
47 unsigned int link;
48};
49
50struct bcm_sf2_cfp_priv {
51 /* Mutex protecting concurrent accesses to the CFP registers */
52 struct mutex lock;
53 DECLARE_BITMAP(used, CFP_NUM_RULES);
54 DECLARE_BITMAP(unique, CFP_NUM_RULES);
55 unsigned int rules_cnt;
56 struct list_head rules_list;
57};
58
59struct bcm_sf2_priv {
60 /* Base registers, keep those in order with BCM_SF2_REGS_NAME */
61 void __iomem *core;
62 void __iomem *reg;
63 void __iomem *intrl2_0;
64 void __iomem *intrl2_1;
65 void __iomem *fcb;
66 void __iomem *acb;
67
68 struct reset_control *rcdev;
69
70 /* Register offsets indirection tables */
71 u32 type;
72 const u16 *reg_offsets;
73 unsigned int core_reg_align;
74 unsigned int num_cfp_rules;
75
76 /* spinlock protecting access to the indirect registers */
77 spinlock_t indir_lock;
78
79 int irq0;
80 int irq1;
81 u32 irq0_stat;
82 u32 irq0_mask;
83 u32 irq1_stat;
84 u32 irq1_mask;
85
86 /* Backing b53_device */
87 struct b53_device *dev;
88
89 struct bcm_sf2_hw_params hw_params;
90
91 struct bcm_sf2_port_status port_sts[DSA_MAX_PORTS];
92
93 /* Mask of ports enabled for Wake-on-LAN */
94 u32 wol_ports_mask;
95
96 /* MoCA port location */
97 int moca_port;
98
99 /* Bitmask of ports having an integrated PHY */
100 unsigned int int_phy_mask;
101
102 /* Master and slave MDIO bus controller */
103 unsigned int indir_phy_mask;
104 struct device_node *master_mii_dn;
105 struct mii_bus *slave_mii_bus;
106 struct mii_bus *master_mii_bus;
107
108 /* Bitmask of ports needing BRCM tags */
109 unsigned int brcm_tag_mask;
110
111 /* CFP rules context */
112 struct bcm_sf2_cfp_priv cfp;
113};
114
115static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds)
116{
117 struct b53_device *dev = ds->priv;
118
119 return dev->priv;
120}
121
122static inline u32 bcm_sf2_mangle_addr(struct bcm_sf2_priv *priv, u32 off)
123{
124 return off << priv->core_reg_align;
125}
126
127#define SF2_IO_MACRO(name) \
128static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \
129{ \
130 return readl_relaxed(priv->name + off); \
131} \
132static inline void name##_writel(struct bcm_sf2_priv *priv, \
133 u32 val, u32 off) \
134{ \
135 writel_relaxed(val, priv->name + off); \
136} \
137
138/* Accesses to 64-bits register requires us to latch the hi/lo pairs
139 * using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
140 * spinlock is automatically grabbed and released to provide relative
141 * atomiticy with latched reads/writes.
142 */
143#define SF2_IO64_MACRO(name) \
144static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off) \
145{ \
146 u32 indir, dir; \
147 spin_lock(&priv->indir_lock); \
148 dir = name##_readl(priv, off); \
149 indir = reg_readl(priv, REG_DIR_DATA_READ); \
150 spin_unlock(&priv->indir_lock); \
151 return (u64)indir << 32 | dir; \
152} \
153static inline void name##_writeq(struct bcm_sf2_priv *priv, u64 val, \
154 u32 off) \
155{ \
156 spin_lock(&priv->indir_lock); \
157 reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE); \
158 name##_writel(priv, lower_32_bits(val), off); \
159 spin_unlock(&priv->indir_lock); \
160}
161
162#define SWITCH_INTR_L2(which) \
163static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \
164 u32 mask) \
165{ \
166 priv->irq##which##_mask &= ~(mask); \
167 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
168} \
169static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
170 u32 mask) \
171{ \
172 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
173 priv->irq##which##_mask |= (mask); \
174} \
175
176static inline u32 core_readl(struct bcm_sf2_priv *priv, u32 off)
177{
178 u32 tmp = bcm_sf2_mangle_addr(priv, off);
179 return readl_relaxed(priv->core + tmp);
180}
181
182static inline void core_writel(struct bcm_sf2_priv *priv, u32 val, u32 off)
183{
184 u32 tmp = bcm_sf2_mangle_addr(priv, off);
185 writel_relaxed(val, priv->core + tmp);
186}
187
188static inline u32 reg_readl(struct bcm_sf2_priv *priv, u16 off)
189{
190 return readl_relaxed(priv->reg + priv->reg_offsets[off]);
191}
192
193static inline void reg_writel(struct bcm_sf2_priv *priv, u32 val, u16 off)
194{
195 writel_relaxed(val, priv->reg + priv->reg_offsets[off]);
196}
197
198SF2_IO64_MACRO(core);
199SF2_IO_MACRO(intrl2_0);
200SF2_IO_MACRO(intrl2_1);
201SF2_IO_MACRO(fcb);
202SF2_IO_MACRO(acb);
203
204SWITCH_INTR_L2(0);
205SWITCH_INTR_L2(1);
206
207/* RXNFC */
208int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,
209 struct ethtool_rxnfc *nfc, u32 *rule_locs);
210int bcm_sf2_set_rxnfc(struct dsa_switch *ds, int port,
211 struct ethtool_rxnfc *nfc);
212int bcm_sf2_cfp_rst(struct bcm_sf2_priv *priv);
213void bcm_sf2_cfp_exit(struct dsa_switch *ds);
214int bcm_sf2_cfp_resume(struct dsa_switch *ds);
215void bcm_sf2_cfp_get_strings(struct dsa_switch *ds, int port,
216 u32 stringset, uint8_t *data);
217void bcm_sf2_cfp_get_ethtool_stats(struct dsa_switch *ds, int port,
218 uint64_t *data);
219int bcm_sf2_cfp_get_sset_count(struct dsa_switch *ds, int port, int sset);
220
221#endif /* __BCM_SF2_H */