tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2006-2009 Texas Instruments Inc
4 */
5#ifndef _DM644X_CCDC_REGS_H
6#define _DM644X_CCDC_REGS_H
7
8/**************************************************************************\
9* Register OFFSET Definitions
10\**************************************************************************/
11#define CCDC_PID 0x0
12#define CCDC_PCR 0x4
13#define CCDC_SYN_MODE 0x8
14#define CCDC_HD_VD_WID 0xc
15#define CCDC_PIX_LINES 0x10
16#define CCDC_HORZ_INFO 0x14
17#define CCDC_VERT_START 0x18
18#define CCDC_VERT_LINES 0x1c
19#define CCDC_CULLING 0x20
20#define CCDC_HSIZE_OFF 0x24
21#define CCDC_SDOFST 0x28
22#define CCDC_SDR_ADDR 0x2c
23#define CCDC_CLAMP 0x30
24#define CCDC_DCSUB 0x34
25#define CCDC_COLPTN 0x38
26#define CCDC_BLKCMP 0x3c
27#define CCDC_FPC 0x40
28#define CCDC_FPC_ADDR 0x44
29#define CCDC_VDINT 0x48
30#define CCDC_ALAW 0x4c
31#define CCDC_REC656IF 0x50
32#define CCDC_CCDCFG 0x54
33#define CCDC_FMTCFG 0x58
34#define CCDC_FMT_HORZ 0x5c
35#define CCDC_FMT_VERT 0x60
36#define CCDC_FMT_ADDR0 0x64
37#define CCDC_FMT_ADDR1 0x68
38#define CCDC_FMT_ADDR2 0x6c
39#define CCDC_FMT_ADDR3 0x70
40#define CCDC_FMT_ADDR4 0x74
41#define CCDC_FMT_ADDR5 0x78
42#define CCDC_FMT_ADDR6 0x7c
43#define CCDC_FMT_ADDR7 0x80
44#define CCDC_PRGEVEN_0 0x84
45#define CCDC_PRGEVEN_1 0x88
46#define CCDC_PRGODD_0 0x8c
47#define CCDC_PRGODD_1 0x90
48#define CCDC_VP_OUT 0x94
49#define CCDC_REG_END 0x98
50
51/***************************************************************
52* Define for various register bit mask and shifts for CCDC
53****************************************************************/
54#define CCDC_FID_POL_MASK 1
55#define CCDC_FID_POL_SHIFT 4
56#define CCDC_HD_POL_MASK 1
57#define CCDC_HD_POL_SHIFT 3
58#define CCDC_VD_POL_MASK 1
59#define CCDC_VD_POL_SHIFT 2
60#define CCDC_HSIZE_OFF_MASK 0xffffffe0
61#define CCDC_32BYTE_ALIGN_VAL 31
62#define CCDC_FRM_FMT_MASK 0x1
63#define CCDC_FRM_FMT_SHIFT 7
64#define CCDC_DATA_SZ_MASK 7
65#define CCDC_DATA_SZ_SHIFT 8
66#define CCDC_PIX_FMT_MASK 3
67#define CCDC_PIX_FMT_SHIFT 12
68#define CCDC_VP2SDR_DISABLE 0xFFFBFFFF
69#define CCDC_WEN_ENABLE BIT(17)
70#define CCDC_SDR2RSZ_DISABLE 0xFFF7FFFF
71#define CCDC_VDHDEN_ENABLE BIT(16)
72#define CCDC_LPF_ENABLE BIT(14)
73#define CCDC_ALAW_ENABLE BIT(3)
74#define CCDC_ALAW_GAMMA_WD_MASK 7
75#define CCDC_BLK_CLAMP_ENABLE BIT(31)
76#define CCDC_BLK_SGAIN_MASK 0x1F
77#define CCDC_BLK_ST_PXL_MASK 0x7FFF
78#define CCDC_BLK_ST_PXL_SHIFT 10
79#define CCDC_BLK_SAMPLE_LN_MASK 7
80#define CCDC_BLK_SAMPLE_LN_SHIFT 28
81#define CCDC_BLK_SAMPLE_LINE_MASK 7
82#define CCDC_BLK_SAMPLE_LINE_SHIFT 25
83#define CCDC_BLK_DC_SUB_MASK 0x03FFF
84#define CCDC_BLK_COMP_MASK 0xFF
85#define CCDC_BLK_COMP_GB_COMP_SHIFT 8
86#define CCDC_BLK_COMP_GR_COMP_SHIFT 16
87#define CCDC_BLK_COMP_R_COMP_SHIFT 24
88#define CCDC_LATCH_ON_VSYNC_DISABLE BIT(15)
89#define CCDC_FPC_ENABLE BIT(15)
90#define CCDC_FPC_DISABLE 0
91#define CCDC_FPC_FPC_NUM_MASK 0x7FFF
92#define CCDC_DATA_PACK_ENABLE BIT(11)
93#define CCDC_FMTCFG_VPIN_MASK 7
94#define CCDC_FMTCFG_VPIN_SHIFT 12
95#define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF
96#define CCDC_FMT_HORZ_FMTSPH_MASK 0x1FFF
97#define CCDC_FMT_HORZ_FMTSPH_SHIFT 16
98#define CCDC_FMT_VERT_FMTLNV_MASK 0x1FFF
99#define CCDC_FMT_VERT_FMTSLV_MASK 0x1FFF
100#define CCDC_FMT_VERT_FMTSLV_SHIFT 16
101#define CCDC_VP_OUT_VERT_NUM_MASK 0x3FFF
102#define CCDC_VP_OUT_VERT_NUM_SHIFT 17
103#define CCDC_VP_OUT_HORZ_NUM_MASK 0x1FFF
104#define CCDC_VP_OUT_HORZ_NUM_SHIFT 4
105#define CCDC_VP_OUT_HORZ_ST_MASK 0xF
106#define CCDC_HORZ_INFO_SPH_SHIFT 16
107#define CCDC_VERT_START_SLV0_SHIFT 16
108#define CCDC_VDINT_VDINT0_SHIFT 16
109#define CCDC_VDINT_VDINT1_MASK 0xFFFF
110#define CCDC_PPC_RAW 1
111#define CCDC_DCSUB_DEFAULT_VAL 0
112#define CCDC_CLAMP_DEFAULT_VAL 0
113#define CCDC_ENABLE_VIDEO_PORT 0x8000
114#define CCDC_DISABLE_VIDEO_PORT 0
115#define CCDC_COLPTN_VAL 0xBB11BB11
116#define CCDC_TWO_BYTES_PER_PIXEL 2
117#define CCDC_INTERLACED_IMAGE_INVERT 0x4B6D
118#define CCDC_INTERLACED_NO_IMAGE_INVERT 0x0249
119#define CCDC_PROGRESSIVE_IMAGE_INVERT 0x4000
120#define CCDC_PROGRESSIVE_NO_IMAGE_INVERT 0
121#define CCDC_INTERLACED_HEIGHT_SHIFT 1
122#define CCDC_SYN_MODE_INPMOD_SHIFT 12
123#define CCDC_SYN_MODE_INPMOD_MASK 3
124#define CCDC_SYN_MODE_8BITS (7 << 8)
125#define CCDC_SYN_MODE_10BITS (6 << 8)
126#define CCDC_SYN_MODE_11BITS (5 << 8)
127#define CCDC_SYN_MODE_12BITS (4 << 8)
128#define CCDC_SYN_MODE_13BITS (3 << 8)
129#define CCDC_SYN_MODE_14BITS (2 << 8)
130#define CCDC_SYN_MODE_15BITS (1 << 8)
131#define CCDC_SYN_MODE_16BITS (0 << 8)
132#define CCDC_SYN_FLDMODE_MASK 1
133#define CCDC_SYN_FLDMODE_SHIFT 7
134#define CCDC_REC656IF_BT656_EN 3
135#define CCDC_SYN_MODE_VD_POL_NEGATIVE BIT(2)
136#define CCDC_CCDCFG_Y8POS_SHIFT 11
137#define CCDC_CCDCFG_BW656_10BIT BIT(5)
138#define CCDC_SDOFST_FIELD_INTERLEAVED 0x249
139#define CCDC_NO_CULLING 0xffff00ff
140#endif