Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include "amdgpu_ctx.h"
32
33#include <linux/atomic.h>
34#include <linux/wait.h>
35#include <linux/list.h>
36#include <linux/kref.h>
37#include <linux/rbtree.h>
38#include <linux/hashtable.h>
39#include <linux/dma-fence.h>
40
41#include <drm/ttm/ttm_bo_api.h>
42#include <drm/ttm/ttm_bo_driver.h>
43#include <drm/ttm/ttm_placement.h>
44#include <drm/ttm/ttm_module.h>
45#include <drm/ttm/ttm_execbuf_util.h>
46
47#include <drm/amdgpu_drm.h>
48#include <drm/drm_gem.h>
49#include <drm/drm_ioctl.h>
50#include <drm/gpu_scheduler.h>
51
52#include <kgd_kfd_interface.h>
53#include "dm_pp_interface.h"
54#include "kgd_pp_interface.h"
55
56#include "amd_shared.h"
57#include "amdgpu_mode.h"
58#include "amdgpu_ih.h"
59#include "amdgpu_irq.h"
60#include "amdgpu_ucode.h"
61#include "amdgpu_ttm.h"
62#include "amdgpu_psp.h"
63#include "amdgpu_gds.h"
64#include "amdgpu_sync.h"
65#include "amdgpu_ring.h"
66#include "amdgpu_vm.h"
67#include "amdgpu_dpm.h"
68#include "amdgpu_acp.h"
69#include "amdgpu_uvd.h"
70#include "amdgpu_vce.h"
71#include "amdgpu_vcn.h"
72#include "amdgpu_mn.h"
73#include "amdgpu_gmc.h"
74#include "amdgpu_gfx.h"
75#include "amdgpu_sdma.h"
76#include "amdgpu_nbio.h"
77#include "amdgpu_dm.h"
78#include "amdgpu_virt.h"
79#include "amdgpu_csa.h"
80#include "amdgpu_gart.h"
81#include "amdgpu_debugfs.h"
82#include "amdgpu_job.h"
83#include "amdgpu_bo_list.h"
84#include "amdgpu_gem.h"
85#include "amdgpu_doorbell.h"
86#include "amdgpu_amdkfd.h"
87#include "amdgpu_smu.h"
88#include "amdgpu_discovery.h"
89#include "amdgpu_mes.h"
90#include "amdgpu_umc.h"
91#include "amdgpu_mmhub.h"
92
93#define MAX_GPU_INSTANCE 16
94
95struct amdgpu_gpu_instance
96{
97 struct amdgpu_device *adev;
98 int mgpu_fan_enabled;
99};
100
101struct amdgpu_mgpu_info
102{
103 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
104 struct mutex mutex;
105 uint32_t num_gpu;
106 uint32_t num_dgpu;
107 uint32_t num_apu;
108};
109
110#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
111
112/*
113 * Modules parameters.
114 */
115extern int amdgpu_modeset;
116extern int amdgpu_vram_limit;
117extern int amdgpu_vis_vram_limit;
118extern int amdgpu_gart_size;
119extern int amdgpu_gtt_size;
120extern int amdgpu_moverate;
121extern int amdgpu_benchmarking;
122extern int amdgpu_testing;
123extern int amdgpu_audio;
124extern int amdgpu_disp_priority;
125extern int amdgpu_hw_i2c;
126extern int amdgpu_pcie_gen2;
127extern int amdgpu_msi;
128extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
129extern int amdgpu_dpm;
130extern int amdgpu_fw_load_type;
131extern int amdgpu_aspm;
132extern int amdgpu_runtime_pm;
133extern uint amdgpu_ip_block_mask;
134extern int amdgpu_bapm;
135extern int amdgpu_deep_color;
136extern int amdgpu_vm_size;
137extern int amdgpu_vm_block_size;
138extern int amdgpu_vm_fragment_size;
139extern int amdgpu_vm_fault_stop;
140extern int amdgpu_vm_debug;
141extern int amdgpu_vm_update_mode;
142extern int amdgpu_exp_hw_support;
143extern int amdgpu_dc;
144extern int amdgpu_sched_jobs;
145extern int amdgpu_sched_hw_submission;
146extern uint amdgpu_pcie_gen_cap;
147extern uint amdgpu_pcie_lane_cap;
148extern uint amdgpu_cg_mask;
149extern uint amdgpu_pg_mask;
150extern uint amdgpu_sdma_phase_quantum;
151extern char *amdgpu_disable_cu;
152extern char *amdgpu_virtual_display;
153extern uint amdgpu_pp_feature_mask;
154extern uint amdgpu_force_long_training;
155extern int amdgpu_job_hang_limit;
156extern int amdgpu_lbpw;
157extern int amdgpu_compute_multipipe;
158extern int amdgpu_gpu_recovery;
159extern int amdgpu_emu_mode;
160extern uint amdgpu_smu_memory_pool_size;
161extern uint amdgpu_dc_feature_mask;
162extern uint amdgpu_dm_abm_level;
163extern struct amdgpu_mgpu_info mgpu_info;
164extern int amdgpu_ras_enable;
165extern uint amdgpu_ras_mask;
166extern int amdgpu_async_gfx_ring;
167extern int amdgpu_mcbp;
168extern int amdgpu_discovery;
169extern int amdgpu_mes;
170extern int amdgpu_noretry;
171extern int amdgpu_force_asic_type;
172#ifdef CONFIG_HSA_AMD
173extern int sched_policy;
174#else
175static const int sched_policy = KFD_SCHED_POLICY_HWS;
176#endif
177
178#ifdef CONFIG_DRM_AMDGPU_SI
179extern int amdgpu_si_support;
180#endif
181#ifdef CONFIG_DRM_AMDGPU_CIK
182extern int amdgpu_cik_support;
183#endif
184
185#define AMDGPU_VM_MAX_NUM_CTX 4096
186#define AMDGPU_SG_THRESHOLD (256*1024*1024)
187#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
188#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
189#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
190#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
191/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
192#define AMDGPU_IB_POOL_SIZE 16
193#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
194#define AMDGPUFB_CONN_LIMIT 4
195#define AMDGPU_BIOS_NUM_SCRATCH 16
196
197/* hard reset data */
198#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
199
200/* reset flags */
201#define AMDGPU_RESET_GFX (1 << 0)
202#define AMDGPU_RESET_COMPUTE (1 << 1)
203#define AMDGPU_RESET_DMA (1 << 2)
204#define AMDGPU_RESET_CP (1 << 3)
205#define AMDGPU_RESET_GRBM (1 << 4)
206#define AMDGPU_RESET_DMA1 (1 << 5)
207#define AMDGPU_RESET_RLC (1 << 6)
208#define AMDGPU_RESET_SEM (1 << 7)
209#define AMDGPU_RESET_IH (1 << 8)
210#define AMDGPU_RESET_VMC (1 << 9)
211#define AMDGPU_RESET_MC (1 << 10)
212#define AMDGPU_RESET_DISPLAY (1 << 11)
213#define AMDGPU_RESET_UVD (1 << 12)
214#define AMDGPU_RESET_VCE (1 << 13)
215#define AMDGPU_RESET_VCE1 (1 << 14)
216
217/* max cursor sizes (in pixels) */
218#define CIK_CURSOR_WIDTH 128
219#define CIK_CURSOR_HEIGHT 128
220
221struct amdgpu_device;
222struct amdgpu_ib;
223struct amdgpu_cs_parser;
224struct amdgpu_job;
225struct amdgpu_irq_src;
226struct amdgpu_fpriv;
227struct amdgpu_bo_va_mapping;
228struct amdgpu_atif;
229struct kfd_vm_fault_info;
230
231enum amdgpu_cp_irq {
232 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
233 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
234 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
235 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
236 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
237 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
238 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
239 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
240 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
241 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
242
243 AMDGPU_CP_IRQ_LAST
244};
245
246enum amdgpu_thermal_irq {
247 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
248 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
249
250 AMDGPU_THERMAL_IRQ_LAST
251};
252
253enum amdgpu_kiq_irq {
254 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
255 AMDGPU_CP_KIQ_IRQ_LAST
256};
257
258#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
259#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
260#define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
261
262int amdgpu_device_ip_set_clockgating_state(void *dev,
263 enum amd_ip_block_type block_type,
264 enum amd_clockgating_state state);
265int amdgpu_device_ip_set_powergating_state(void *dev,
266 enum amd_ip_block_type block_type,
267 enum amd_powergating_state state);
268void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
269 u32 *flags);
270int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
271 enum amd_ip_block_type block_type);
272bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
273 enum amd_ip_block_type block_type);
274
275#define AMDGPU_MAX_IP_NUM 16
276
277struct amdgpu_ip_block_status {
278 bool valid;
279 bool sw;
280 bool hw;
281 bool late_initialized;
282 bool hang;
283};
284
285struct amdgpu_ip_block_version {
286 const enum amd_ip_block_type type;
287 const u32 major;
288 const u32 minor;
289 const u32 rev;
290 const struct amd_ip_funcs *funcs;
291};
292
293#define HW_REV(_Major, _Minor, _Rev) \
294 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
295
296struct amdgpu_ip_block {
297 struct amdgpu_ip_block_status status;
298 const struct amdgpu_ip_block_version *version;
299};
300
301int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
302 enum amd_ip_block_type type,
303 u32 major, u32 minor);
304
305struct amdgpu_ip_block *
306amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
307 enum amd_ip_block_type type);
308
309int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
310 const struct amdgpu_ip_block_version *ip_block_version);
311
312/*
313 * BIOS.
314 */
315bool amdgpu_get_bios(struct amdgpu_device *adev);
316bool amdgpu_read_bios(struct amdgpu_device *adev);
317
318/*
319 * Clocks
320 */
321
322#define AMDGPU_MAX_PPLL 3
323
324struct amdgpu_clock {
325 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
326 struct amdgpu_pll spll;
327 struct amdgpu_pll mpll;
328 /* 10 Khz units */
329 uint32_t default_mclk;
330 uint32_t default_sclk;
331 uint32_t default_dispclk;
332 uint32_t current_dispclk;
333 uint32_t dp_extclk;
334 uint32_t max_pixel_clock;
335};
336
337/* sub-allocation manager, it has to be protected by another lock.
338 * By conception this is an helper for other part of the driver
339 * like the indirect buffer or semaphore, which both have their
340 * locking.
341 *
342 * Principe is simple, we keep a list of sub allocation in offset
343 * order (first entry has offset == 0, last entry has the highest
344 * offset).
345 *
346 * When allocating new object we first check if there is room at
347 * the end total_size - (last_object_offset + last_object_size) >=
348 * alloc_size. If so we allocate new object there.
349 *
350 * When there is not enough room at the end, we start waiting for
351 * each sub object until we reach object_offset+object_size >=
352 * alloc_size, this object then become the sub object we return.
353 *
354 * Alignment can't be bigger than page size.
355 *
356 * Hole are not considered for allocation to keep things simple.
357 * Assumption is that there won't be hole (all object on same
358 * alignment).
359 */
360
361#define AMDGPU_SA_NUM_FENCE_LISTS 32
362
363struct amdgpu_sa_manager {
364 wait_queue_head_t wq;
365 struct amdgpu_bo *bo;
366 struct list_head *hole;
367 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
368 struct list_head olist;
369 unsigned size;
370 uint64_t gpu_addr;
371 void *cpu_ptr;
372 uint32_t domain;
373 uint32_t align;
374};
375
376/* sub-allocation buffer */
377struct amdgpu_sa_bo {
378 struct list_head olist;
379 struct list_head flist;
380 struct amdgpu_sa_manager *manager;
381 unsigned soffset;
382 unsigned eoffset;
383 struct dma_fence *fence;
384};
385
386int amdgpu_fence_slab_init(void);
387void amdgpu_fence_slab_fini(void);
388
389/*
390 * IRQS.
391 */
392
393struct amdgpu_flip_work {
394 struct delayed_work flip_work;
395 struct work_struct unpin_work;
396 struct amdgpu_device *adev;
397 int crtc_id;
398 u32 target_vblank;
399 uint64_t base;
400 struct drm_pending_vblank_event *event;
401 struct amdgpu_bo *old_abo;
402 struct dma_fence *excl;
403 unsigned shared_count;
404 struct dma_fence **shared;
405 struct dma_fence_cb cb;
406 bool async;
407};
408
409
410/*
411 * CP & rings.
412 */
413
414struct amdgpu_ib {
415 struct amdgpu_sa_bo *sa_bo;
416 uint32_t length_dw;
417 uint64_t gpu_addr;
418 uint32_t *ptr;
419 uint32_t flags;
420};
421
422extern const struct drm_sched_backend_ops amdgpu_sched_ops;
423
424/*
425 * file private structure
426 */
427
428struct amdgpu_fpriv {
429 struct amdgpu_vm vm;
430 struct amdgpu_bo_va *prt_va;
431 struct amdgpu_bo_va *csa_va;
432 struct mutex bo_list_lock;
433 struct idr bo_list_handles;
434 struct amdgpu_ctx_mgr ctx_mgr;
435};
436
437int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
438
439int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
440 unsigned size, struct amdgpu_ib *ib);
441void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
442 struct dma_fence *f);
443int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
444 struct amdgpu_ib *ibs, struct amdgpu_job *job,
445 struct dma_fence **f);
446int amdgpu_ib_pool_init(struct amdgpu_device *adev);
447void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
448int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
449
450/*
451 * CS.
452 */
453struct amdgpu_cs_chunk {
454 uint32_t chunk_id;
455 uint32_t length_dw;
456 void *kdata;
457};
458
459struct amdgpu_cs_post_dep {
460 struct drm_syncobj *syncobj;
461 struct dma_fence_chain *chain;
462 u64 point;
463};
464
465struct amdgpu_cs_parser {
466 struct amdgpu_device *adev;
467 struct drm_file *filp;
468 struct amdgpu_ctx *ctx;
469
470 /* chunks */
471 unsigned nchunks;
472 struct amdgpu_cs_chunk *chunks;
473
474 /* scheduler job object */
475 struct amdgpu_job *job;
476 struct drm_sched_entity *entity;
477
478 /* buffer objects */
479 struct ww_acquire_ctx ticket;
480 struct amdgpu_bo_list *bo_list;
481 struct amdgpu_mn *mn;
482 struct amdgpu_bo_list_entry vm_pd;
483 struct list_head validated;
484 struct dma_fence *fence;
485 uint64_t bytes_moved_threshold;
486 uint64_t bytes_moved_vis_threshold;
487 uint64_t bytes_moved;
488 uint64_t bytes_moved_vis;
489
490 /* user fence */
491 struct amdgpu_bo_list_entry uf_entry;
492
493 unsigned num_post_deps;
494 struct amdgpu_cs_post_dep *post_deps;
495};
496
497static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
498 uint32_t ib_idx, int idx)
499{
500 return p->job->ibs[ib_idx].ptr[idx];
501}
502
503static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
504 uint32_t ib_idx, int idx,
505 uint32_t value)
506{
507 p->job->ibs[ib_idx].ptr[idx] = value;
508}
509
510/*
511 * Writeback
512 */
513#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */
514
515struct amdgpu_wb {
516 struct amdgpu_bo *wb_obj;
517 volatile uint32_t *wb;
518 uint64_t gpu_addr;
519 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
520 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
521};
522
523int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
524void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
525
526/*
527 * Benchmarking
528 */
529void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
530
531
532/*
533 * Testing
534 */
535void amdgpu_test_moves(struct amdgpu_device *adev);
536
537/*
538 * ASIC specific register table accessible by UMD
539 */
540struct amdgpu_allowed_register_entry {
541 uint32_t reg_offset;
542 bool grbm_indexed;
543};
544
545enum amd_reset_method {
546 AMD_RESET_METHOD_LEGACY = 0,
547 AMD_RESET_METHOD_MODE0,
548 AMD_RESET_METHOD_MODE1,
549 AMD_RESET_METHOD_MODE2,
550 AMD_RESET_METHOD_BACO
551};
552
553/*
554 * ASIC specific functions.
555 */
556struct amdgpu_asic_funcs {
557 bool (*read_disabled_bios)(struct amdgpu_device *adev);
558 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
559 u8 *bios, u32 length_bytes);
560 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
561 u32 sh_num, u32 reg_offset, u32 *value);
562 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
563 int (*reset)(struct amdgpu_device *adev);
564 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
565 /* get the reference clock */
566 u32 (*get_xclk)(struct amdgpu_device *adev);
567 /* MM block clocks */
568 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
569 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
570 /* static power management */
571 int (*get_pcie_lanes)(struct amdgpu_device *adev);
572 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
573 /* get config memsize register */
574 u32 (*get_config_memsize)(struct amdgpu_device *adev);
575 /* flush hdp write queue */
576 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
577 /* invalidate hdp read cache */
578 void (*invalidate_hdp)(struct amdgpu_device *adev,
579 struct amdgpu_ring *ring);
580 /* check if the asic needs a full reset of if soft reset will work */
581 bool (*need_full_reset)(struct amdgpu_device *adev);
582 /* initialize doorbell layout for specific asic*/
583 void (*init_doorbell_index)(struct amdgpu_device *adev);
584 /* PCIe bandwidth usage */
585 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
586 uint64_t *count1);
587 /* do we need to reset the asic at init time (e.g., kexec) */
588 bool (*need_reset_on_init)(struct amdgpu_device *adev);
589 /* PCIe replay counter */
590 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
591};
592
593/*
594 * IOCTL.
595 */
596int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
597 struct drm_file *filp);
598
599int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
600int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
601 struct drm_file *filp);
602int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
603int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
604 struct drm_file *filp);
605
606/* VRAM scratch page for HDP bug, default vram page */
607struct amdgpu_vram_scratch {
608 struct amdgpu_bo *robj;
609 volatile uint32_t *ptr;
610 u64 gpu_addr;
611};
612
613/*
614 * ACPI
615 */
616struct amdgpu_atcs_functions {
617 bool get_ext_state;
618 bool pcie_perf_req;
619 bool pcie_dev_rdy;
620 bool pcie_bus_width;
621};
622
623struct amdgpu_atcs {
624 struct amdgpu_atcs_functions functions;
625};
626
627/*
628 * Firmware VRAM reservation
629 */
630struct amdgpu_fw_vram_usage {
631 u64 start_offset;
632 u64 size;
633 struct amdgpu_bo *reserved_bo;
634 void *va;
635
636 /* Offset on the top of VRAM, used as c2p write buffer.
637 */
638 u64 mem_train_fb_loc;
639 bool mem_train_support;
640};
641
642/*
643 * CGS
644 */
645struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
646void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
647
648/*
649 * Core structure, functions and helpers.
650 */
651typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
652typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
653
654typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
655typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
656
657typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
658typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
659
660struct amdgpu_mmio_remap {
661 u32 reg_offset;
662 resource_size_t bus_addr;
663};
664
665struct amdgpu_df_funcs {
666 void (*sw_init)(struct amdgpu_device *adev);
667 void (*sw_fini)(struct amdgpu_device *adev);
668 void (*enable_broadcast_mode)(struct amdgpu_device *adev,
669 bool enable);
670 u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
671 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
672 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
673 bool enable);
674 void (*get_clockgating_state)(struct amdgpu_device *adev,
675 u32 *flags);
676 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
677 bool enable);
678 int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
679 int is_enable);
680 int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
681 int is_disable);
682 void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
683 uint64_t *count);
684 uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
685 void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
686 uint32_t ficadl_val, uint32_t ficadh_val);
687};
688/* Define the HW IP blocks will be used in driver , add more if necessary */
689enum amd_hw_ip_block_type {
690 GC_HWIP = 1,
691 HDP_HWIP,
692 SDMA0_HWIP,
693 SDMA1_HWIP,
694 SDMA2_HWIP,
695 SDMA3_HWIP,
696 SDMA4_HWIP,
697 SDMA5_HWIP,
698 SDMA6_HWIP,
699 SDMA7_HWIP,
700 MMHUB_HWIP,
701 ATHUB_HWIP,
702 NBIO_HWIP,
703 MP0_HWIP,
704 MP1_HWIP,
705 UVD_HWIP,
706 VCN_HWIP = UVD_HWIP,
707 VCE_HWIP,
708 DF_HWIP,
709 DCE_HWIP,
710 OSSSYS_HWIP,
711 SMUIO_HWIP,
712 PWR_HWIP,
713 NBIF_HWIP,
714 THM_HWIP,
715 CLK_HWIP,
716 UMC_HWIP,
717 RSMU_HWIP,
718 MAX_HWIP
719};
720
721#define HWIP_MAX_INSTANCE 8
722
723struct amd_powerplay {
724 void *pp_handle;
725 const struct amd_pm_funcs *pp_funcs;
726};
727
728#define AMDGPU_RESET_MAGIC_NUM 64
729#define AMDGPU_MAX_DF_PERFMONS 4
730struct amdgpu_device {
731 struct device *dev;
732 struct drm_device *ddev;
733 struct pci_dev *pdev;
734
735#ifdef CONFIG_DRM_AMD_ACP
736 struct amdgpu_acp acp;
737#endif
738
739 /* ASIC */
740 enum amd_asic_type asic_type;
741 uint32_t family;
742 uint32_t rev_id;
743 uint32_t external_rev_id;
744 unsigned long flags;
745 int usec_timeout;
746 const struct amdgpu_asic_funcs *asic_funcs;
747 bool shutdown;
748 bool need_swiotlb;
749 bool accel_working;
750 struct notifier_block acpi_nb;
751 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
752 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
753 unsigned debugfs_count;
754#if defined(CONFIG_DEBUG_FS)
755 struct dentry *debugfs_preempt;
756 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
757#endif
758 struct amdgpu_atif *atif;
759 struct amdgpu_atcs atcs;
760 struct mutex srbm_mutex;
761 /* GRBM index mutex. Protects concurrent access to GRBM index */
762 struct mutex grbm_idx_mutex;
763 struct dev_pm_domain vga_pm_domain;
764 bool have_disp_power_ref;
765 bool have_atomics_support;
766
767 /* BIOS */
768 bool is_atom_fw;
769 uint8_t *bios;
770 uint32_t bios_size;
771 struct amdgpu_bo *stolen_vga_memory;
772 struct amdgpu_bo *discovery_memory;
773 uint32_t bios_scratch_reg_offset;
774 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
775
776 /* Register/doorbell mmio */
777 resource_size_t rmmio_base;
778 resource_size_t rmmio_size;
779 void __iomem *rmmio;
780 /* protects concurrent MM_INDEX/DATA based register access */
781 spinlock_t mmio_idx_lock;
782 struct amdgpu_mmio_remap rmmio_remap;
783 /* protects concurrent SMC based register access */
784 spinlock_t smc_idx_lock;
785 amdgpu_rreg_t smc_rreg;
786 amdgpu_wreg_t smc_wreg;
787 /* protects concurrent PCIE register access */
788 spinlock_t pcie_idx_lock;
789 amdgpu_rreg_t pcie_rreg;
790 amdgpu_wreg_t pcie_wreg;
791 amdgpu_rreg_t pciep_rreg;
792 amdgpu_wreg_t pciep_wreg;
793 amdgpu_rreg64_t pcie_rreg64;
794 amdgpu_wreg64_t pcie_wreg64;
795 /* protects concurrent UVD register access */
796 spinlock_t uvd_ctx_idx_lock;
797 amdgpu_rreg_t uvd_ctx_rreg;
798 amdgpu_wreg_t uvd_ctx_wreg;
799 /* protects concurrent DIDT register access */
800 spinlock_t didt_idx_lock;
801 amdgpu_rreg_t didt_rreg;
802 amdgpu_wreg_t didt_wreg;
803 /* protects concurrent gc_cac register access */
804 spinlock_t gc_cac_idx_lock;
805 amdgpu_rreg_t gc_cac_rreg;
806 amdgpu_wreg_t gc_cac_wreg;
807 /* protects concurrent se_cac register access */
808 spinlock_t se_cac_idx_lock;
809 amdgpu_rreg_t se_cac_rreg;
810 amdgpu_wreg_t se_cac_wreg;
811 /* protects concurrent ENDPOINT (audio) register access */
812 spinlock_t audio_endpt_idx_lock;
813 amdgpu_block_rreg_t audio_endpt_rreg;
814 amdgpu_block_wreg_t audio_endpt_wreg;
815 void __iomem *rio_mem;
816 resource_size_t rio_mem_size;
817 struct amdgpu_doorbell doorbell;
818
819 /* clock/pll info */
820 struct amdgpu_clock clock;
821
822 /* MC */
823 struct amdgpu_gmc gmc;
824 struct amdgpu_gart gart;
825 dma_addr_t dummy_page_addr;
826 struct amdgpu_vm_manager vm_manager;
827 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
828 unsigned num_vmhubs;
829
830 /* memory management */
831 struct amdgpu_mman mman;
832 struct amdgpu_vram_scratch vram_scratch;
833 struct amdgpu_wb wb;
834 atomic64_t num_bytes_moved;
835 atomic64_t num_evictions;
836 atomic64_t num_vram_cpu_page_faults;
837 atomic_t gpu_reset_counter;
838 atomic_t vram_lost_counter;
839
840 /* data for buffer migration throttling */
841 struct {
842 spinlock_t lock;
843 s64 last_update_us;
844 s64 accum_us; /* accumulated microseconds */
845 s64 accum_us_vis; /* for visible VRAM */
846 u32 log2_max_MBps;
847 } mm_stats;
848
849 /* display */
850 bool enable_virtual_display;
851 struct amdgpu_mode_info mode_info;
852 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
853 struct work_struct hotplug_work;
854 struct amdgpu_irq_src crtc_irq;
855 struct amdgpu_irq_src vupdate_irq;
856 struct amdgpu_irq_src pageflip_irq;
857 struct amdgpu_irq_src hpd_irq;
858
859 /* rings */
860 u64 fence_context;
861 unsigned num_rings;
862 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
863 bool ib_pool_ready;
864 struct amdgpu_sa_manager ring_tmp_bo;
865
866 /* interrupts */
867 struct amdgpu_irq irq;
868
869 /* powerplay */
870 struct amd_powerplay powerplay;
871 bool pp_force_state_enabled;
872
873 /* smu */
874 struct smu_context smu;
875
876 /* dpm */
877 struct amdgpu_pm pm;
878 u32 cg_flags;
879 u32 pg_flags;
880
881 /* nbio */
882 struct amdgpu_nbio nbio;
883
884 /* mmhub */
885 struct amdgpu_mmhub mmhub;
886
887 /* gfx */
888 struct amdgpu_gfx gfx;
889
890 /* sdma */
891 struct amdgpu_sdma sdma;
892
893 /* uvd */
894 struct amdgpu_uvd uvd;
895
896 /* vce */
897 struct amdgpu_vce vce;
898
899 /* vcn */
900 struct amdgpu_vcn vcn;
901
902 /* firmwares */
903 struct amdgpu_firmware firmware;
904
905 /* PSP */
906 struct psp_context psp;
907
908 /* GDS */
909 struct amdgpu_gds gds;
910
911 /* KFD */
912 struct amdgpu_kfd_dev kfd;
913
914 /* UMC */
915 struct amdgpu_umc umc;
916
917 /* display related functionality */
918 struct amdgpu_display_manager dm;
919
920 /* discovery */
921 uint8_t *discovery;
922
923 /* mes */
924 bool enable_mes;
925 struct amdgpu_mes mes;
926
927 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
928 int num_ip_blocks;
929 struct mutex mn_lock;
930 DECLARE_HASHTABLE(mn_hash, 7);
931
932 /* tracking pinned memory */
933 atomic64_t vram_pin_size;
934 atomic64_t visible_pin_size;
935 atomic64_t gart_pin_size;
936
937 /* soc15 register offset based on ip, instance and segment */
938 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
939
940 const struct amdgpu_df_funcs *df_funcs;
941
942 /* delayed work_func for deferring clockgating during resume */
943 struct delayed_work delayed_init_work;
944
945 struct amdgpu_virt virt;
946 /* firmware VRAM reservation */
947 struct amdgpu_fw_vram_usage fw_vram_usage;
948
949 /* link all shadow bo */
950 struct list_head shadow_list;
951 struct mutex shadow_list_lock;
952 /* keep an lru list of rings by HW IP */
953 struct list_head ring_lru_list;
954 spinlock_t ring_lru_list_lock;
955
956 /* record hw reset is performed */
957 bool has_hw_reset;
958 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
959
960 /* s3/s4 mask */
961 bool in_suspend;
962
963 /* record last mm index being written through WREG32*/
964 unsigned long last_mm_index;
965 bool in_gpu_reset;
966 enum pp_mp1_state mp1_state;
967 struct mutex lock_reset;
968 struct amdgpu_doorbell_index doorbell_index;
969
970 struct mutex notifier_lock;
971
972 int asic_reset_res;
973 struct work_struct xgmi_reset_work;
974
975 long gfx_timeout;
976 long sdma_timeout;
977 long video_timeout;
978 long compute_timeout;
979
980 uint64_t unique_id;
981 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
982
983 /* device pstate */
984 int pstate;
985};
986
987static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
988{
989 return container_of(bdev, struct amdgpu_device, mman.bdev);
990}
991
992int amdgpu_device_init(struct amdgpu_device *adev,
993 struct drm_device *ddev,
994 struct pci_dev *pdev,
995 uint32_t flags);
996void amdgpu_device_fini(struct amdgpu_device *adev);
997int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
998
999void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1000 uint32_t *buf, size_t size, bool write);
1001uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
1002 uint32_t acc_flags);
1003void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1004 uint32_t acc_flags);
1005void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1006uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1007
1008u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1009void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1010
1011bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1012bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1013
1014int emu_soc_asic_init(struct amdgpu_device *adev);
1015
1016/*
1017 * Registers read & write functions.
1018 */
1019
1020#define AMDGPU_REGS_IDX (1<<0)
1021#define AMDGPU_REGS_NO_KIQ (1<<1)
1022
1023#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1024#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1025
1026#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1027#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1028
1029#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1030#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1031#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1032#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1033#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
1034#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1035#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1036#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1037#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1038#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1039#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1040#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1041#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1042#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1043#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1044#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1045#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1046#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1047#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1048#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1049#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1050#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1051#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1052#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1053#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1054#define WREG32_P(reg, val, mask) \
1055 do { \
1056 uint32_t tmp_ = RREG32(reg); \
1057 tmp_ &= (mask); \
1058 tmp_ |= ((val) & ~(mask)); \
1059 WREG32(reg, tmp_); \
1060 } while (0)
1061#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1062#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1063#define WREG32_PLL_P(reg, val, mask) \
1064 do { \
1065 uint32_t tmp_ = RREG32_PLL(reg); \
1066 tmp_ &= (mask); \
1067 tmp_ |= ((val) & ~(mask)); \
1068 WREG32_PLL(reg, tmp_); \
1069 } while (0)
1070#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1071#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1072#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1073
1074#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1075#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1076
1077#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1078 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1079 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1080
1081#define REG_GET_FIELD(value, reg, field) \
1082 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1083
1084#define WREG32_FIELD(reg, field, val) \
1085 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1086
1087#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1088 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1089
1090/*
1091 * BIOS helpers.
1092 */
1093#define RBIOS8(i) (adev->bios[i])
1094#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1095#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1096
1097/*
1098 * ASICs macro.
1099 */
1100#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1101#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1102#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1103#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1104#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1105#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1106#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1107#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1108#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1109#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1110#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1111#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1112#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1113#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1114#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
1115#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1116#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1117#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1118#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1119#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1120#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1121
1122/* Common functions */
1123bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1124int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1125 struct amdgpu_job* job);
1126void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1127bool amdgpu_device_need_post(struct amdgpu_device *adev);
1128
1129void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1130 u64 num_vis_bytes);
1131int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1132void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1133 const u32 *registers,
1134 const u32 array_size);
1135
1136bool amdgpu_device_is_px(struct drm_device *dev);
1137bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1138 struct amdgpu_device *peer_adev);
1139
1140/* atpx handler */
1141#if defined(CONFIG_VGA_SWITCHEROO)
1142void amdgpu_register_atpx_handler(void);
1143void amdgpu_unregister_atpx_handler(void);
1144bool amdgpu_has_atpx_dgpu_power_cntl(void);
1145bool amdgpu_is_atpx_hybrid(void);
1146bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1147bool amdgpu_has_atpx(void);
1148#else
1149static inline void amdgpu_register_atpx_handler(void) {}
1150static inline void amdgpu_unregister_atpx_handler(void) {}
1151static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1152static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1153static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1154static inline bool amdgpu_has_atpx(void) { return false; }
1155#endif
1156
1157#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1158void *amdgpu_atpx_get_dhandle(void);
1159#else
1160static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1161#endif
1162
1163/*
1164 * KMS
1165 */
1166extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1167extern const int amdgpu_max_kms_ioctl;
1168
1169int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
1170void amdgpu_driver_unload_kms(struct drm_device *dev);
1171void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1172int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1173void amdgpu_driver_postclose_kms(struct drm_device *dev,
1174 struct drm_file *file_priv);
1175int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1176int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1177int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
1178u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1179int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1180void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1181long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1182 unsigned long arg);
1183
1184/*
1185 * functions used by amdgpu_encoder.c
1186 */
1187struct amdgpu_afmt_acr {
1188 u32 clock;
1189
1190 int n_32khz;
1191 int cts_32khz;
1192
1193 int n_44_1khz;
1194 int cts_44_1khz;
1195
1196 int n_48khz;
1197 int cts_48khz;
1198
1199};
1200
1201struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1202
1203/* amdgpu_acpi.c */
1204#if defined(CONFIG_ACPI)
1205int amdgpu_acpi_init(struct amdgpu_device *adev);
1206void amdgpu_acpi_fini(struct amdgpu_device *adev);
1207bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1208int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1209 u8 perf_req, bool advertise);
1210int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1211
1212void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1213 struct amdgpu_dm_backlight_caps *caps);
1214#else
1215static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1216static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1217#endif
1218
1219int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1220 uint64_t addr, struct amdgpu_bo **bo,
1221 struct amdgpu_bo_va_mapping **mapping);
1222
1223#if defined(CONFIG_DRM_AMD_DC)
1224int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1225#else
1226static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1227#endif
1228
1229
1230void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1231void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1232
1233#include "amdgpu_object.h"
1234
1235/* used by df_v3_6.c and amdgpu_pmu.c */
1236#define AMDGPU_PMU_ATTR(_name, _object) \
1237static ssize_t \
1238_name##_show(struct device *dev, \
1239 struct device_attribute *attr, \
1240 char *page) \
1241{ \
1242 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \
1243 return sprintf(page, _object "\n"); \
1244} \
1245 \
1246static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
1247
1248#endif
1249