tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2016 AmLogic, Inc.
4 * Author: Michael Turquette <mturquette@baylibre.com>
5 *
6 * Copyright (c) 2017 Amlogic, inc.
7 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
8 *
9 */
10#ifndef __AXG_H
11#define __AXG_H
12
13/*
14 * Clock controller register offsets
15 *
16 * Register offsets from the data sheet must be multiplied by 4 before
17 * adding them to the base address to get the right value.
18 */
19#define HHI_MIPI_CNTL0 0x00
20#define HHI_GP0_PLL_CNTL 0x40
21#define HHI_GP0_PLL_CNTL2 0x44
22#define HHI_GP0_PLL_CNTL3 0x48
23#define HHI_GP0_PLL_CNTL4 0x4c
24#define HHI_GP0_PLL_CNTL5 0x50
25#define HHI_GP0_PLL_STS 0x54
26#define HHI_GP0_PLL_CNTL1 0x58
27#define HHI_HIFI_PLL_CNTL 0x80
28#define HHI_HIFI_PLL_CNTL2 0x84
29#define HHI_HIFI_PLL_CNTL3 0x88
30#define HHI_HIFI_PLL_CNTL4 0x8C
31#define HHI_HIFI_PLL_CNTL5 0x90
32#define HHI_HIFI_PLL_STS 0x94
33#define HHI_HIFI_PLL_CNTL1 0x98
34
35#define HHI_XTAL_DIVN_CNTL 0xbc
36#define HHI_GCLK2_MPEG0 0xc0
37#define HHI_GCLK2_MPEG1 0xc4
38#define HHI_GCLK2_MPEG2 0xc8
39#define HHI_GCLK2_OTHER 0xd0
40#define HHI_GCLK2_AO 0xd4
41#define HHI_PCIE_PLL_CNTL 0xd8
42#define HHI_PCIE_PLL_CNTL1 0xdC
43#define HHI_PCIE_PLL_CNTL2 0xe0
44#define HHI_PCIE_PLL_CNTL3 0xe4
45#define HHI_PCIE_PLL_CNTL4 0xe8
46#define HHI_PCIE_PLL_CNTL5 0xec
47#define HHI_PCIE_PLL_CNTL6 0xf0
48#define HHI_PCIE_PLL_STS 0xf4
49
50#define HHI_MEM_PD_REG0 0x100
51#define HHI_VPU_MEM_PD_REG0 0x104
52#define HHI_VIID_CLK_DIV 0x128
53#define HHI_VIID_CLK_CNTL 0x12c
54
55#define HHI_GCLK_MPEG0 0x140
56#define HHI_GCLK_MPEG1 0x144
57#define HHI_GCLK_MPEG2 0x148
58#define HHI_GCLK_OTHER 0x150
59#define HHI_GCLK_AO 0x154
60#define HHI_SYS_CPU_CLK_CNTL1 0x15c
61#define HHI_SYS_CPU_RESET_CNTL 0x160
62#define HHI_VID_CLK_DIV 0x164
63#define HHI_SPICC_HCLK_CNTL 0x168
64
65#define HHI_MPEG_CLK_CNTL 0x174
66#define HHI_VID_CLK_CNTL 0x17c
67#define HHI_TS_CLK_CNTL 0x190
68#define HHI_VID_CLK_CNTL2 0x194
69#define HHI_SYS_CPU_CLK_CNTL0 0x19c
70#define HHI_VID_PLL_CLK_DIV 0x1a0
71#define HHI_VPU_CLK_CNTL 0x1bC
72
73#define HHI_VAPBCLK_CNTL 0x1F4
74
75#define HHI_GEN_CLK_CNTL 0x228
76
77#define HHI_VDIN_MEAS_CLK_CNTL 0x250
78#define HHI_NAND_CLK_CNTL 0x25C
79#define HHI_SD_EMMC_CLK_CNTL 0x264
80
81#define HHI_MPLL_CNTL 0x280
82#define HHI_MPLL_CNTL2 0x284
83#define HHI_MPLL_CNTL3 0x288
84#define HHI_MPLL_CNTL4 0x28C
85#define HHI_MPLL_CNTL5 0x290
86#define HHI_MPLL_CNTL6 0x294
87#define HHI_MPLL_CNTL7 0x298
88#define HHI_MPLL_CNTL8 0x29C
89#define HHI_MPLL_CNTL9 0x2A0
90#define HHI_MPLL_CNTL10 0x2A4
91
92#define HHI_MPLL3_CNTL0 0x2E0
93#define HHI_MPLL3_CNTL1 0x2E4
94#define HHI_PLL_TOP_MISC 0x2E8
95
96#define HHI_SYS_PLL_CNTL1 0x2FC
97#define HHI_SYS_PLL_CNTL 0x300
98#define HHI_SYS_PLL_CNTL2 0x304
99#define HHI_SYS_PLL_CNTL3 0x308
100#define HHI_SYS_PLL_CNTL4 0x30c
101#define HHI_SYS_PLL_CNTL5 0x310
102#define HHI_SYS_PLL_STS 0x314
103#define HHI_DPLL_TOP_I 0x318
104#define HHI_DPLL_TOP2_I 0x31C
105
106/*
107 * CLKID index values
108 *
109 * These indices are entirely contrived and do not map onto the hardware.
110 * It has now been decided to expose everything by default in the DT header:
111 * include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
112 * to expose, such as the internal muxes and dividers of composite clocks,
113 * will remain defined here.
114 */
115#define CLKID_MPEG_SEL 8
116#define CLKID_MPEG_DIV 9
117#define CLKID_SD_EMMC_B_CLK0_SEL 61
118#define CLKID_SD_EMMC_B_CLK0_DIV 62
119#define CLKID_SD_EMMC_C_CLK0_SEL 63
120#define CLKID_SD_EMMC_C_CLK0_DIV 64
121#define CLKID_MPLL0_DIV 65
122#define CLKID_MPLL1_DIV 66
123#define CLKID_MPLL2_DIV 67
124#define CLKID_MPLL3_DIV 68
125#define CLKID_MPLL_PREDIV 70
126#define CLKID_FCLK_DIV2_DIV 71
127#define CLKID_FCLK_DIV3_DIV 72
128#define CLKID_FCLK_DIV4_DIV 73
129#define CLKID_FCLK_DIV5_DIV 74
130#define CLKID_FCLK_DIV7_DIV 75
131#define CLKID_PCIE_PLL 76
132#define CLKID_PCIE_MUX 77
133#define CLKID_PCIE_REF 78
134#define CLKID_GEN_CLK_SEL 82
135#define CLKID_GEN_CLK_DIV 83
136#define CLKID_SYS_PLL_DCO 85
137#define CLKID_FIXED_PLL_DCO 86
138#define CLKID_GP0_PLL_DCO 87
139#define CLKID_HIFI_PLL_DCO 88
140#define CLKID_PCIE_PLL_DCO 89
141#define CLKID_PCIE_PLL_OD 90
142
143#define NR_CLKS 91
144
145/* include the CLKIDs that have been made part of the DT binding */
146#include <dt-bindings/clock/axg-clkc.h>
147
148#endif /* __AXG_H */