arch/arm64/include/asm/sysreg.h at v5.5

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Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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kernel / arch / arm64 / include / asm / sysreg.h
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  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Macros for accessing system registers with older binutils.
  4 *
  5 * Copyright (C) 2014 ARM Ltd.
  6 * Author: Catalin Marinas <catalin.marinas@arm.com>
  7 */
  8
  9#ifndef __ASM_SYSREG_H
 10#define __ASM_SYSREG_H
 11
 12#include <linux/bits.h>
 13#include <linux/stringify.h>
 14
 15/*
 16 * ARMv8 ARM reserves the following encoding for system registers:
 17 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
 18 *  C5.2, version:ARM DDI 0487A.f)
 19 *	[20-19] : Op0
 20 *	[18-16] : Op1
 21 *	[15-12] : CRn
 22 *	[11-8]  : CRm
 23 *	[7-5]   : Op2
 24 */
 25#define Op0_shift	19
 26#define Op0_mask	0x3
 27#define Op1_shift	16
 28#define Op1_mask	0x7
 29#define CRn_shift	12
 30#define CRn_mask	0xf
 31#define CRm_shift	8
 32#define CRm_mask	0xf
 33#define Op2_shift	5
 34#define Op2_mask	0x7
 35
 36#define sys_reg(op0, op1, crn, crm, op2) \
 37	(((op0) << Op0_shift) | ((op1) << Op1_shift) | \
 38	 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
 39	 ((op2) << Op2_shift))
 40
 41#define sys_insn	sys_reg
 42
 43#define sys_reg_Op0(id)	(((id) >> Op0_shift) & Op0_mask)
 44#define sys_reg_Op1(id)	(((id) >> Op1_shift) & Op1_mask)
 45#define sys_reg_CRn(id)	(((id) >> CRn_shift) & CRn_mask)
 46#define sys_reg_CRm(id)	(((id) >> CRm_shift) & CRm_mask)
 47#define sys_reg_Op2(id)	(((id) >> Op2_shift) & Op2_mask)
 48
 49#ifndef CONFIG_BROKEN_GAS_INST
 50
 51#ifdef __ASSEMBLY__
 52#define __emit_inst(x)			.inst (x)
 53#else
 54#define __emit_inst(x)			".inst " __stringify((x)) "\n\t"
 55#endif
 56
 57#else  /* CONFIG_BROKEN_GAS_INST */
 58
 59#ifndef CONFIG_CPU_BIG_ENDIAN
 60#define __INSTR_BSWAP(x)		(x)
 61#else  /* CONFIG_CPU_BIG_ENDIAN */
 62#define __INSTR_BSWAP(x)		((((x) << 24) & 0xff000000)	| \
 63					 (((x) <<  8) & 0x00ff0000)	| \
 64					 (((x) >>  8) & 0x0000ff00)	| \
 65					 (((x) >> 24) & 0x000000ff))
 66#endif	/* CONFIG_CPU_BIG_ENDIAN */
 67
 68#ifdef __ASSEMBLY__
 69#define __emit_inst(x)			.long __INSTR_BSWAP(x)
 70#else  /* __ASSEMBLY__ */
 71#define __emit_inst(x)			".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
 72#endif	/* __ASSEMBLY__ */
 73
 74#endif	/* CONFIG_BROKEN_GAS_INST */
 75
 76/*
 77 * Instructions for modifying PSTATE fields.
 78 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
 79 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
 80 * for accessing PSTATE fields have the following encoding:
 81 *	Op0 = 0, CRn = 4
 82 *	Op1, Op2 encodes the PSTATE field modified and defines the constraints.
 83 *	CRm = Imm4 for the instruction.
 84 *	Rt = 0x1f
 85 */
 86#define pstate_field(op1, op2)		((op1) << Op1_shift | (op2) << Op2_shift)
 87#define PSTATE_Imm_shift		CRm_shift
 88
 89#define PSTATE_PAN			pstate_field(0, 4)
 90#define PSTATE_UAO			pstate_field(0, 3)
 91#define PSTATE_SSBS			pstate_field(3, 1)
 92
 93#define SET_PSTATE_PAN(x)		__emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
 94#define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
 95#define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
 96
 97#define __SYS_BARRIER_INSN(CRm, op2, Rt) \
 98	__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
 99
100#define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)
101
102#define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)
103#define SYS_DC_CSW			sys_insn(1, 0, 7, 10, 2)
104#define SYS_DC_CISW			sys_insn(1, 0, 7, 14, 2)
105
106#define SYS_OSDTRRX_EL1			sys_reg(2, 0, 0, 0, 2)
107#define SYS_MDCCINT_EL1			sys_reg(2, 0, 0, 2, 0)
108#define SYS_MDSCR_EL1			sys_reg(2, 0, 0, 2, 2)
109#define SYS_OSDTRTX_EL1			sys_reg(2, 0, 0, 3, 2)
110#define SYS_OSECCR_EL1			sys_reg(2, 0, 0, 6, 2)
111#define SYS_DBGBVRn_EL1(n)		sys_reg(2, 0, 0, n, 4)
112#define SYS_DBGBCRn_EL1(n)		sys_reg(2, 0, 0, n, 5)
113#define SYS_DBGWVRn_EL1(n)		sys_reg(2, 0, 0, n, 6)
114#define SYS_DBGWCRn_EL1(n)		sys_reg(2, 0, 0, n, 7)
115#define SYS_MDRAR_EL1			sys_reg(2, 0, 1, 0, 0)
116#define SYS_OSLAR_EL1			sys_reg(2, 0, 1, 0, 4)
117#define SYS_OSLSR_EL1			sys_reg(2, 0, 1, 1, 4)
118#define SYS_OSDLR_EL1			sys_reg(2, 0, 1, 3, 4)
119#define SYS_DBGPRCR_EL1			sys_reg(2, 0, 1, 4, 4)
120#define SYS_DBGCLAIMSET_EL1		sys_reg(2, 0, 7, 8, 6)
121#define SYS_DBGCLAIMCLR_EL1		sys_reg(2, 0, 7, 9, 6)
122#define SYS_DBGAUTHSTATUS_EL1		sys_reg(2, 0, 7, 14, 6)
123#define SYS_MDCCSR_EL0			sys_reg(2, 3, 0, 1, 0)
124#define SYS_DBGDTR_EL0			sys_reg(2, 3, 0, 4, 0)
125#define SYS_DBGDTRRX_EL0		sys_reg(2, 3, 0, 5, 0)
126#define SYS_DBGDTRTX_EL0		sys_reg(2, 3, 0, 5, 0)
127#define SYS_DBGVCR32_EL2		sys_reg(2, 4, 0, 7, 0)
128
129#define SYS_MIDR_EL1			sys_reg(3, 0, 0, 0, 0)
130#define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
131#define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
132
133#define SYS_ID_PFR0_EL1			sys_reg(3, 0, 0, 1, 0)
134#define SYS_ID_PFR1_EL1			sys_reg(3, 0, 0, 1, 1)
135#define SYS_ID_DFR0_EL1			sys_reg(3, 0, 0, 1, 2)
136#define SYS_ID_AFR0_EL1			sys_reg(3, 0, 0, 1, 3)
137#define SYS_ID_MMFR0_EL1		sys_reg(3, 0, 0, 1, 4)
138#define SYS_ID_MMFR1_EL1		sys_reg(3, 0, 0, 1, 5)
139#define SYS_ID_MMFR2_EL1		sys_reg(3, 0, 0, 1, 6)
140#define SYS_ID_MMFR3_EL1		sys_reg(3, 0, 0, 1, 7)
141
142#define SYS_ID_ISAR0_EL1		sys_reg(3, 0, 0, 2, 0)
143#define SYS_ID_ISAR1_EL1		sys_reg(3, 0, 0, 2, 1)
144#define SYS_ID_ISAR2_EL1		sys_reg(3, 0, 0, 2, 2)
145#define SYS_ID_ISAR3_EL1		sys_reg(3, 0, 0, 2, 3)
146#define SYS_ID_ISAR4_EL1		sys_reg(3, 0, 0, 2, 4)
147#define SYS_ID_ISAR5_EL1		sys_reg(3, 0, 0, 2, 5)
148#define SYS_ID_MMFR4_EL1		sys_reg(3, 0, 0, 2, 6)
149
150#define SYS_MVFR0_EL1			sys_reg(3, 0, 0, 3, 0)
151#define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
152#define SYS_MVFR2_EL1			sys_reg(3, 0, 0, 3, 2)
153
154#define SYS_ID_AA64PFR0_EL1		sys_reg(3, 0, 0, 4, 0)
155#define SYS_ID_AA64PFR1_EL1		sys_reg(3, 0, 0, 4, 1)
156#define SYS_ID_AA64ZFR0_EL1		sys_reg(3, 0, 0, 4, 4)
157
158#define SYS_ID_AA64DFR0_EL1		sys_reg(3, 0, 0, 5, 0)
159#define SYS_ID_AA64DFR1_EL1		sys_reg(3, 0, 0, 5, 1)
160
161#define SYS_ID_AA64AFR0_EL1		sys_reg(3, 0, 0, 5, 4)
162#define SYS_ID_AA64AFR1_EL1		sys_reg(3, 0, 0, 5, 5)
163
164#define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)
165#define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)
166
167#define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
168#define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
169#define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)
170
171#define SYS_SCTLR_EL1			sys_reg(3, 0, 1, 0, 0)
172#define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
173#define SYS_CPACR_EL1			sys_reg(3, 0, 1, 0, 2)
174
175#define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)
176
177#define SYS_TTBR0_EL1			sys_reg(3, 0, 2, 0, 0)
178#define SYS_TTBR1_EL1			sys_reg(3, 0, 2, 0, 1)
179#define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
180
181#define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
182#define SYS_APIAKEYHI_EL1		sys_reg(3, 0, 2, 1, 1)
183#define SYS_APIBKEYLO_EL1		sys_reg(3, 0, 2, 1, 2)
184#define SYS_APIBKEYHI_EL1		sys_reg(3, 0, 2, 1, 3)
185
186#define SYS_APDAKEYLO_EL1		sys_reg(3, 0, 2, 2, 0)
187#define SYS_APDAKEYHI_EL1		sys_reg(3, 0, 2, 2, 1)
188#define SYS_APDBKEYLO_EL1		sys_reg(3, 0, 2, 2, 2)
189#define SYS_APDBKEYHI_EL1		sys_reg(3, 0, 2, 2, 3)
190
191#define SYS_APGAKEYLO_EL1		sys_reg(3, 0, 2, 3, 0)
192#define SYS_APGAKEYHI_EL1		sys_reg(3, 0, 2, 3, 1)
193
194#define SYS_SPSR_EL1			sys_reg(3, 0, 4, 0, 0)
195#define SYS_ELR_EL1			sys_reg(3, 0, 4, 0, 1)
196
197#define SYS_ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
198
199#define SYS_AFSR0_EL1			sys_reg(3, 0, 5, 1, 0)
200#define SYS_AFSR1_EL1			sys_reg(3, 0, 5, 1, 1)
201#define SYS_ESR_EL1			sys_reg(3, 0, 5, 2, 0)
202
203#define SYS_ERRIDR_EL1			sys_reg(3, 0, 5, 3, 0)
204#define SYS_ERRSELR_EL1			sys_reg(3, 0, 5, 3, 1)
205#define SYS_ERXFR_EL1			sys_reg(3, 0, 5, 4, 0)
206#define SYS_ERXCTLR_EL1			sys_reg(3, 0, 5, 4, 1)
207#define SYS_ERXSTATUS_EL1		sys_reg(3, 0, 5, 4, 2)
208#define SYS_ERXADDR_EL1			sys_reg(3, 0, 5, 4, 3)
209#define SYS_ERXMISC0_EL1		sys_reg(3, 0, 5, 5, 0)
210#define SYS_ERXMISC1_EL1		sys_reg(3, 0, 5, 5, 1)
211
212#define SYS_FAR_EL1			sys_reg(3, 0, 6, 0, 0)
213#define SYS_PAR_EL1			sys_reg(3, 0, 7, 4, 0)
214
215#define SYS_PAR_EL1_F			BIT(0)
216#define SYS_PAR_EL1_FST			GENMASK(6, 1)
217
218/*** Statistical Profiling Extension ***/
219/* ID registers */
220#define SYS_PMSIDR_EL1			sys_reg(3, 0, 9, 9, 7)
221#define SYS_PMSIDR_EL1_FE_SHIFT		0
222#define SYS_PMSIDR_EL1_FT_SHIFT		1
223#define SYS_PMSIDR_EL1_FL_SHIFT		2
224#define SYS_PMSIDR_EL1_ARCHINST_SHIFT	3
225#define SYS_PMSIDR_EL1_LDS_SHIFT	4
226#define SYS_PMSIDR_EL1_ERND_SHIFT	5
227#define SYS_PMSIDR_EL1_INTERVAL_SHIFT	8
228#define SYS_PMSIDR_EL1_INTERVAL_MASK	0xfUL
229#define SYS_PMSIDR_EL1_MAXSIZE_SHIFT	12
230#define SYS_PMSIDR_EL1_MAXSIZE_MASK	0xfUL
231#define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT	16
232#define SYS_PMSIDR_EL1_COUNTSIZE_MASK	0xfUL
233
234#define SYS_PMBIDR_EL1			sys_reg(3, 0, 9, 10, 7)
235#define SYS_PMBIDR_EL1_ALIGN_SHIFT	0
236#define SYS_PMBIDR_EL1_ALIGN_MASK	0xfU
237#define SYS_PMBIDR_EL1_P_SHIFT		4
238#define SYS_PMBIDR_EL1_F_SHIFT		5
239
240/* Sampling controls */
241#define SYS_PMSCR_EL1			sys_reg(3, 0, 9, 9, 0)
242#define SYS_PMSCR_EL1_E0SPE_SHIFT	0
243#define SYS_PMSCR_EL1_E1SPE_SHIFT	1
244#define SYS_PMSCR_EL1_CX_SHIFT		3
245#define SYS_PMSCR_EL1_PA_SHIFT		4
246#define SYS_PMSCR_EL1_TS_SHIFT		5
247#define SYS_PMSCR_EL1_PCT_SHIFT		6
248
249#define SYS_PMSCR_EL2			sys_reg(3, 4, 9, 9, 0)
250#define SYS_PMSCR_EL2_E0HSPE_SHIFT	0
251#define SYS_PMSCR_EL2_E2SPE_SHIFT	1
252#define SYS_PMSCR_EL2_CX_SHIFT		3
253#define SYS_PMSCR_EL2_PA_SHIFT		4
254#define SYS_PMSCR_EL2_TS_SHIFT		5
255#define SYS_PMSCR_EL2_PCT_SHIFT		6
256
257#define SYS_PMSICR_EL1			sys_reg(3, 0, 9, 9, 2)
258
259#define SYS_PMSIRR_EL1			sys_reg(3, 0, 9, 9, 3)
260#define SYS_PMSIRR_EL1_RND_SHIFT	0
261#define SYS_PMSIRR_EL1_INTERVAL_SHIFT	8
262#define SYS_PMSIRR_EL1_INTERVAL_MASK	0xffffffUL
263
264/* Filtering controls */
265#define SYS_PMSFCR_EL1			sys_reg(3, 0, 9, 9, 4)
266#define SYS_PMSFCR_EL1_FE_SHIFT		0
267#define SYS_PMSFCR_EL1_FT_SHIFT		1
268#define SYS_PMSFCR_EL1_FL_SHIFT		2
269#define SYS_PMSFCR_EL1_B_SHIFT		16
270#define SYS_PMSFCR_EL1_LD_SHIFT		17
271#define SYS_PMSFCR_EL1_ST_SHIFT		18
272
273#define SYS_PMSEVFR_EL1			sys_reg(3, 0, 9, 9, 5)
274#define SYS_PMSEVFR_EL1_RES0		0x0000ffff00ff0f55UL
275
276#define SYS_PMSLATFR_EL1		sys_reg(3, 0, 9, 9, 6)
277#define SYS_PMSLATFR_EL1_MINLAT_SHIFT	0
278
279/* Buffer controls */
280#define SYS_PMBLIMITR_EL1		sys_reg(3, 0, 9, 10, 0)
281#define SYS_PMBLIMITR_EL1_E_SHIFT	0
282#define SYS_PMBLIMITR_EL1_FM_SHIFT	1
283#define SYS_PMBLIMITR_EL1_FM_MASK	0x3UL
284#define SYS_PMBLIMITR_EL1_FM_STOP_IRQ	(0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
285
286#define SYS_PMBPTR_EL1			sys_reg(3, 0, 9, 10, 1)
287
288/* Buffer error reporting */
289#define SYS_PMBSR_EL1			sys_reg(3, 0, 9, 10, 3)
290#define SYS_PMBSR_EL1_COLL_SHIFT	16
291#define SYS_PMBSR_EL1_S_SHIFT		17
292#define SYS_PMBSR_EL1_EA_SHIFT		18
293#define SYS_PMBSR_EL1_DL_SHIFT		19
294#define SYS_PMBSR_EL1_EC_SHIFT		26
295#define SYS_PMBSR_EL1_EC_MASK		0x3fUL
296
297#define SYS_PMBSR_EL1_EC_BUF		(0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
298#define SYS_PMBSR_EL1_EC_FAULT_S1	(0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
299#define SYS_PMBSR_EL1_EC_FAULT_S2	(0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
300
301#define SYS_PMBSR_EL1_FAULT_FSC_SHIFT	0
302#define SYS_PMBSR_EL1_FAULT_FSC_MASK	0x3fUL
303
304#define SYS_PMBSR_EL1_BUF_BSC_SHIFT	0
305#define SYS_PMBSR_EL1_BUF_BSC_MASK	0x3fUL
306
307#define SYS_PMBSR_EL1_BUF_BSC_FULL	(0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
308
309/*** End of Statistical Profiling Extension ***/
310
311#define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
312#define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
313
314#define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)
315#define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)
316
317#define SYS_LORSA_EL1			sys_reg(3, 0, 10, 4, 0)
318#define SYS_LOREA_EL1			sys_reg(3, 0, 10, 4, 1)
319#define SYS_LORN_EL1			sys_reg(3, 0, 10, 4, 2)
320#define SYS_LORC_EL1			sys_reg(3, 0, 10, 4, 3)
321#define SYS_LORID_EL1			sys_reg(3, 0, 10, 4, 7)
322
323#define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)
324#define SYS_DISR_EL1			sys_reg(3, 0, 12, 1, 1)
325
326#define SYS_ICC_IAR0_EL1		sys_reg(3, 0, 12, 8, 0)
327#define SYS_ICC_EOIR0_EL1		sys_reg(3, 0, 12, 8, 1)
328#define SYS_ICC_HPPIR0_EL1		sys_reg(3, 0, 12, 8, 2)
329#define SYS_ICC_BPR0_EL1		sys_reg(3, 0, 12, 8, 3)
330#define SYS_ICC_AP0Rn_EL1(n)		sys_reg(3, 0, 12, 8, 4 | n)
331#define SYS_ICC_AP0R0_EL1		SYS_ICC_AP0Rn_EL1(0)
332#define SYS_ICC_AP0R1_EL1		SYS_ICC_AP0Rn_EL1(1)
333#define SYS_ICC_AP0R2_EL1		SYS_ICC_AP0Rn_EL1(2)
334#define SYS_ICC_AP0R3_EL1		SYS_ICC_AP0Rn_EL1(3)
335#define SYS_ICC_AP1Rn_EL1(n)		sys_reg(3, 0, 12, 9, n)
336#define SYS_ICC_AP1R0_EL1		SYS_ICC_AP1Rn_EL1(0)
337#define SYS_ICC_AP1R1_EL1		SYS_ICC_AP1Rn_EL1(1)
338#define SYS_ICC_AP1R2_EL1		SYS_ICC_AP1Rn_EL1(2)
339#define SYS_ICC_AP1R3_EL1		SYS_ICC_AP1Rn_EL1(3)
340#define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
341#define SYS_ICC_RPR_EL1			sys_reg(3, 0, 12, 11, 3)
342#define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)
343#define SYS_ICC_ASGI1R_EL1		sys_reg(3, 0, 12, 11, 6)
344#define SYS_ICC_SGI0R_EL1		sys_reg(3, 0, 12, 11, 7)
345#define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)
346#define SYS_ICC_EOIR1_EL1		sys_reg(3, 0, 12, 12, 1)
347#define SYS_ICC_HPPIR1_EL1		sys_reg(3, 0, 12, 12, 2)
348#define SYS_ICC_BPR1_EL1		sys_reg(3, 0, 12, 12, 3)
349#define SYS_ICC_CTLR_EL1		sys_reg(3, 0, 12, 12, 4)
350#define SYS_ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
351#define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
352#define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
353
354#define SYS_CONTEXTIDR_EL1		sys_reg(3, 0, 13, 0, 1)
355#define SYS_TPIDR_EL1			sys_reg(3, 0, 13, 0, 4)
356
357#define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
358
359#define SYS_CCSIDR_EL1			sys_reg(3, 1, 0, 0, 0)
360#define SYS_CLIDR_EL1			sys_reg(3, 1, 0, 0, 1)
361#define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
362
363#define SYS_CSSELR_EL1			sys_reg(3, 2, 0, 0, 0)
364
365#define SYS_CTR_EL0			sys_reg(3, 3, 0, 0, 1)
366#define SYS_DCZID_EL0			sys_reg(3, 3, 0, 0, 7)
367
368#define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
369#define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
370#define SYS_PMCNTENCLR_EL0		sys_reg(3, 3, 9, 12, 2)
371#define SYS_PMOVSCLR_EL0		sys_reg(3, 3, 9, 12, 3)
372#define SYS_PMSWINC_EL0			sys_reg(3, 3, 9, 12, 4)
373#define SYS_PMSELR_EL0			sys_reg(3, 3, 9, 12, 5)
374#define SYS_PMCEID0_EL0			sys_reg(3, 3, 9, 12, 6)
375#define SYS_PMCEID1_EL0			sys_reg(3, 3, 9, 12, 7)
376#define SYS_PMCCNTR_EL0			sys_reg(3, 3, 9, 13, 0)
377#define SYS_PMXEVTYPER_EL0		sys_reg(3, 3, 9, 13, 1)
378#define SYS_PMXEVCNTR_EL0		sys_reg(3, 3, 9, 13, 2)
379#define SYS_PMUSERENR_EL0		sys_reg(3, 3, 9, 14, 0)
380#define SYS_PMOVSSET_EL0		sys_reg(3, 3, 9, 14, 3)
381
382#define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
383#define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)
384
385#define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)
386
387#define SYS_CNTP_TVAL_EL0		sys_reg(3, 3, 14, 2, 0)
388#define SYS_CNTP_CTL_EL0		sys_reg(3, 3, 14, 2, 1)
389#define SYS_CNTP_CVAL_EL0		sys_reg(3, 3, 14, 2, 2)
390
391#define SYS_CNTV_CTL_EL0		sys_reg(3, 3, 14, 3, 1)
392#define SYS_CNTV_CVAL_EL0		sys_reg(3, 3, 14, 3, 2)
393
394#define SYS_AARCH32_CNTP_TVAL		sys_reg(0, 0, 14, 2, 0)
395#define SYS_AARCH32_CNTP_CTL		sys_reg(0, 0, 14, 2, 1)
396#define SYS_AARCH32_CNTP_CVAL		sys_reg(0, 2, 0, 14, 0)
397
398#define __PMEV_op2(n)			((n) & 0x7)
399#define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))
400#define SYS_PMEVCNTRn_EL0(n)		sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
401#define __TYPER_CRm(n)			(0xc | (((n) >> 3) & 0x3))
402#define SYS_PMEVTYPERn_EL0(n)		sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
403
404#define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)
405
406#define SYS_ZCR_EL2			sys_reg(3, 4, 1, 2, 0)
407#define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)
408#define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
409#define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
410#define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)
411#define SYS_ESR_EL2			sys_reg(3, 4, 5, 2, 0)
412#define SYS_VSESR_EL2			sys_reg(3, 4, 5, 2, 3)
413#define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)
414#define SYS_FAR_EL2			sys_reg(3, 4, 6, 0, 0)
415
416#define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1,  1)
417#define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
418#define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
419#define SYS_ICH_AP0R1_EL2		__SYS__AP0Rx_EL2(1)
420#define SYS_ICH_AP0R2_EL2		__SYS__AP0Rx_EL2(2)
421#define SYS_ICH_AP0R3_EL2		__SYS__AP0Rx_EL2(3)
422
423#define __SYS__AP1Rx_EL2(x)		sys_reg(3, 4, 12, 9, x)
424#define SYS_ICH_AP1R0_EL2		__SYS__AP1Rx_EL2(0)
425#define SYS_ICH_AP1R1_EL2		__SYS__AP1Rx_EL2(1)
426#define SYS_ICH_AP1R2_EL2		__SYS__AP1Rx_EL2(2)
427#define SYS_ICH_AP1R3_EL2		__SYS__AP1Rx_EL2(3)
428
429#define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)
430#define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
431#define SYS_ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
432#define SYS_ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
433#define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)
434#define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
435#define SYS_ICH_ELRSR_EL2		sys_reg(3, 4, 12, 11, 5)
436#define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
437
438#define __SYS__LR0_EL2(x)		sys_reg(3, 4, 12, 12, x)
439#define SYS_ICH_LR0_EL2			__SYS__LR0_EL2(0)
440#define SYS_ICH_LR1_EL2			__SYS__LR0_EL2(1)
441#define SYS_ICH_LR2_EL2			__SYS__LR0_EL2(2)
442#define SYS_ICH_LR3_EL2			__SYS__LR0_EL2(3)
443#define SYS_ICH_LR4_EL2			__SYS__LR0_EL2(4)
444#define SYS_ICH_LR5_EL2			__SYS__LR0_EL2(5)
445#define SYS_ICH_LR6_EL2			__SYS__LR0_EL2(6)
446#define SYS_ICH_LR7_EL2			__SYS__LR0_EL2(7)
447
448#define __SYS__LR8_EL2(x)		sys_reg(3, 4, 12, 13, x)
449#define SYS_ICH_LR8_EL2			__SYS__LR8_EL2(0)
450#define SYS_ICH_LR9_EL2			__SYS__LR8_EL2(1)
451#define SYS_ICH_LR10_EL2		__SYS__LR8_EL2(2)
452#define SYS_ICH_LR11_EL2		__SYS__LR8_EL2(3)
453#define SYS_ICH_LR12_EL2		__SYS__LR8_EL2(4)
454#define SYS_ICH_LR13_EL2		__SYS__LR8_EL2(5)
455#define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
456#define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
457
458/* VHE encodings for architectural EL0/1 system registers */
459#define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
460#define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)
461#define SYS_ZCR_EL12			sys_reg(3, 5, 1, 2, 0)
462#define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
463#define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
464#define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
465#define SYS_SPSR_EL12			sys_reg(3, 5, 4, 0, 0)
466#define SYS_ELR_EL12			sys_reg(3, 5, 4, 0, 1)
467#define SYS_AFSR0_EL12			sys_reg(3, 5, 5, 1, 0)
468#define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)
469#define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)
470#define SYS_FAR_EL12			sys_reg(3, 5, 6, 0, 0)
471#define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
472#define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
473#define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
474#define SYS_CONTEXTIDR_EL12		sys_reg(3, 5, 13, 0, 1)
475#define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
476#define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
477#define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
478#define SYS_CNTP_CVAL_EL02		sys_reg(3, 5, 14, 2, 2)
479#define SYS_CNTV_TVAL_EL02		sys_reg(3, 5, 14, 3, 0)
480#define SYS_CNTV_CTL_EL02		sys_reg(3, 5, 14, 3, 1)
481#define SYS_CNTV_CVAL_EL02		sys_reg(3, 5, 14, 3, 2)
482
483/* Common SCTLR_ELx flags. */
484#define SCTLR_ELx_DSSBS	(BIT(44))
485#define SCTLR_ELx_ENIA	(BIT(31))
486#define SCTLR_ELx_ENIB	(BIT(30))
487#define SCTLR_ELx_ENDA	(BIT(27))
488#define SCTLR_ELx_EE    (BIT(25))
489#define SCTLR_ELx_IESB	(BIT(21))
490#define SCTLR_ELx_WXN	(BIT(19))
491#define SCTLR_ELx_ENDB	(BIT(13))
492#define SCTLR_ELx_I	(BIT(12))
493#define SCTLR_ELx_SA	(BIT(3))
494#define SCTLR_ELx_C	(BIT(2))
495#define SCTLR_ELx_A	(BIT(1))
496#define SCTLR_ELx_M	(BIT(0))
497
498#define SCTLR_ELx_FLAGS	(SCTLR_ELx_M  | SCTLR_ELx_A | SCTLR_ELx_C | \
499			 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB)
500
501/* SCTLR_EL2 specific flags. */
502#define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \
503			 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
504			 (BIT(29)))
505
506#ifdef CONFIG_CPU_BIG_ENDIAN
507#define ENDIAN_SET_EL2		SCTLR_ELx_EE
508#else
509#define ENDIAN_SET_EL2		0
510#endif
511
512/* SCTLR_EL1 specific flags. */
513#define SCTLR_EL1_UCI		(BIT(26))
514#define SCTLR_EL1_E0E		(BIT(24))
515#define SCTLR_EL1_SPAN		(BIT(23))
516#define SCTLR_EL1_NTWE		(BIT(18))
517#define SCTLR_EL1_NTWI		(BIT(16))
518#define SCTLR_EL1_UCT		(BIT(15))
519#define SCTLR_EL1_DZE		(BIT(14))
520#define SCTLR_EL1_UMA		(BIT(9))
521#define SCTLR_EL1_SED		(BIT(8))
522#define SCTLR_EL1_ITD		(BIT(7))
523#define SCTLR_EL1_CP15BEN	(BIT(5))
524#define SCTLR_EL1_SA0		(BIT(4))
525
526#define SCTLR_EL1_RES1	((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
527			 (BIT(29)))
528
529#ifdef CONFIG_CPU_BIG_ENDIAN
530#define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
531#else
532#define ENDIAN_SET_EL1		0
533#endif
534
535#define SCTLR_EL1_SET	(SCTLR_ELx_M    | SCTLR_ELx_C    | SCTLR_ELx_SA   |\
536			 SCTLR_EL1_SA0  | SCTLR_EL1_SED  | SCTLR_ELx_I    |\
537			 SCTLR_EL1_DZE  | SCTLR_EL1_UCT                   |\
538			 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\
539			 ENDIAN_SET_EL1 | SCTLR_EL1_UCI  | SCTLR_EL1_RES1)
540
541/* id_aa64isar0 */
542#define ID_AA64ISAR0_TS_SHIFT		52
543#define ID_AA64ISAR0_FHM_SHIFT		48
544#define ID_AA64ISAR0_DP_SHIFT		44
545#define ID_AA64ISAR0_SM4_SHIFT		40
546#define ID_AA64ISAR0_SM3_SHIFT		36
547#define ID_AA64ISAR0_SHA3_SHIFT		32
548#define ID_AA64ISAR0_RDM_SHIFT		28
549#define ID_AA64ISAR0_ATOMICS_SHIFT	20
550#define ID_AA64ISAR0_CRC32_SHIFT	16
551#define ID_AA64ISAR0_SHA2_SHIFT		12
552#define ID_AA64ISAR0_SHA1_SHIFT		8
553#define ID_AA64ISAR0_AES_SHIFT		4
554
555/* id_aa64isar1 */
556#define ID_AA64ISAR1_SB_SHIFT		36
557#define ID_AA64ISAR1_FRINTTS_SHIFT	32
558#define ID_AA64ISAR1_GPI_SHIFT		28
559#define ID_AA64ISAR1_GPA_SHIFT		24
560#define ID_AA64ISAR1_LRCPC_SHIFT	20
561#define ID_AA64ISAR1_FCMA_SHIFT		16
562#define ID_AA64ISAR1_JSCVT_SHIFT	12
563#define ID_AA64ISAR1_API_SHIFT		8
564#define ID_AA64ISAR1_APA_SHIFT		4
565#define ID_AA64ISAR1_DPB_SHIFT		0
566
567#define ID_AA64ISAR1_APA_NI		0x0
568#define ID_AA64ISAR1_APA_ARCHITECTED	0x1
569#define ID_AA64ISAR1_API_NI		0x0
570#define ID_AA64ISAR1_API_IMP_DEF	0x1
571#define ID_AA64ISAR1_GPA_NI		0x0
572#define ID_AA64ISAR1_GPA_ARCHITECTED	0x1
573#define ID_AA64ISAR1_GPI_NI		0x0
574#define ID_AA64ISAR1_GPI_IMP_DEF	0x1
575
576/* id_aa64pfr0 */
577#define ID_AA64PFR0_CSV3_SHIFT		60
578#define ID_AA64PFR0_CSV2_SHIFT		56
579#define ID_AA64PFR0_DIT_SHIFT		48
580#define ID_AA64PFR0_SVE_SHIFT		32
581#define ID_AA64PFR0_RAS_SHIFT		28
582#define ID_AA64PFR0_GIC_SHIFT		24
583#define ID_AA64PFR0_ASIMD_SHIFT		20
584#define ID_AA64PFR0_FP_SHIFT		16
585#define ID_AA64PFR0_EL3_SHIFT		12
586#define ID_AA64PFR0_EL2_SHIFT		8
587#define ID_AA64PFR0_EL1_SHIFT		4
588#define ID_AA64PFR0_EL0_SHIFT		0
589
590#define ID_AA64PFR0_SVE			0x1
591#define ID_AA64PFR0_RAS_V1		0x1
592#define ID_AA64PFR0_FP_NI		0xf
593#define ID_AA64PFR0_FP_SUPPORTED	0x0
594#define ID_AA64PFR0_ASIMD_NI		0xf
595#define ID_AA64PFR0_ASIMD_SUPPORTED	0x0
596#define ID_AA64PFR0_EL1_64BIT_ONLY	0x1
597#define ID_AA64PFR0_EL0_64BIT_ONLY	0x1
598#define ID_AA64PFR0_EL0_32BIT_64BIT	0x2
599
600/* id_aa64pfr1 */
601#define ID_AA64PFR1_SSBS_SHIFT		4
602
603#define ID_AA64PFR1_SSBS_PSTATE_NI	0
604#define ID_AA64PFR1_SSBS_PSTATE_ONLY	1
605#define ID_AA64PFR1_SSBS_PSTATE_INSNS	2
606
607/* id_aa64zfr0 */
608#define ID_AA64ZFR0_SM4_SHIFT		40
609#define ID_AA64ZFR0_SHA3_SHIFT		32
610#define ID_AA64ZFR0_BITPERM_SHIFT	16
611#define ID_AA64ZFR0_AES_SHIFT		4
612#define ID_AA64ZFR0_SVEVER_SHIFT	0
613
614#define ID_AA64ZFR0_SM4			0x1
615#define ID_AA64ZFR0_SHA3		0x1
616#define ID_AA64ZFR0_BITPERM		0x1
617#define ID_AA64ZFR0_AES			0x1
618#define ID_AA64ZFR0_AES_PMULL		0x2
619#define ID_AA64ZFR0_SVEVER_SVE2		0x1
620
621/* id_aa64mmfr0 */
622#define ID_AA64MMFR0_TGRAN4_SHIFT	28
623#define ID_AA64MMFR0_TGRAN64_SHIFT	24
624#define ID_AA64MMFR0_TGRAN16_SHIFT	20
625#define ID_AA64MMFR0_BIGENDEL0_SHIFT	16
626#define ID_AA64MMFR0_SNSMEM_SHIFT	12
627#define ID_AA64MMFR0_BIGENDEL_SHIFT	8
628#define ID_AA64MMFR0_ASID_SHIFT		4
629#define ID_AA64MMFR0_PARANGE_SHIFT	0
630
631#define ID_AA64MMFR0_TGRAN4_NI		0xf
632#define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0
633#define ID_AA64MMFR0_TGRAN64_NI		0xf
634#define ID_AA64MMFR0_TGRAN64_SUPPORTED	0x0
635#define ID_AA64MMFR0_TGRAN16_NI		0x0
636#define ID_AA64MMFR0_TGRAN16_SUPPORTED	0x1
637#define ID_AA64MMFR0_PARANGE_48		0x5
638#define ID_AA64MMFR0_PARANGE_52		0x6
639
640#ifdef CONFIG_ARM64_PA_BITS_52
641#define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_52
642#else
643#define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_48
644#endif
645
646/* id_aa64mmfr1 */
647#define ID_AA64MMFR1_PAN_SHIFT		20
648#define ID_AA64MMFR1_LOR_SHIFT		16
649#define ID_AA64MMFR1_HPD_SHIFT		12
650#define ID_AA64MMFR1_VHE_SHIFT		8
651#define ID_AA64MMFR1_VMIDBITS_SHIFT	4
652#define ID_AA64MMFR1_HADBS_SHIFT	0
653
654#define ID_AA64MMFR1_VMIDBITS_8		0
655#define ID_AA64MMFR1_VMIDBITS_16	2
656
657/* id_aa64mmfr2 */
658#define ID_AA64MMFR2_FWB_SHIFT		40
659#define ID_AA64MMFR2_AT_SHIFT		32
660#define ID_AA64MMFR2_LVA_SHIFT		16
661#define ID_AA64MMFR2_IESB_SHIFT		12
662#define ID_AA64MMFR2_LSM_SHIFT		8
663#define ID_AA64MMFR2_UAO_SHIFT		4
664#define ID_AA64MMFR2_CNP_SHIFT		0
665
666/* id_aa64dfr0 */
667#define ID_AA64DFR0_PMSVER_SHIFT	32
668#define ID_AA64DFR0_CTX_CMPS_SHIFT	28
669#define ID_AA64DFR0_WRPS_SHIFT		20
670#define ID_AA64DFR0_BRPS_SHIFT		12
671#define ID_AA64DFR0_PMUVER_SHIFT	8
672#define ID_AA64DFR0_TRACEVER_SHIFT	4
673#define ID_AA64DFR0_DEBUGVER_SHIFT	0
674
675#define ID_ISAR5_RDM_SHIFT		24
676#define ID_ISAR5_CRC32_SHIFT		16
677#define ID_ISAR5_SHA2_SHIFT		12
678#define ID_ISAR5_SHA1_SHIFT		8
679#define ID_ISAR5_AES_SHIFT		4
680#define ID_ISAR5_SEVL_SHIFT		0
681
682#define MVFR0_FPROUND_SHIFT		28
683#define MVFR0_FPSHVEC_SHIFT		24
684#define MVFR0_FPSQRT_SHIFT		20
685#define MVFR0_FPDIVIDE_SHIFT		16
686#define MVFR0_FPTRAP_SHIFT		12
687#define MVFR0_FPDP_SHIFT		8
688#define MVFR0_FPSP_SHIFT		4
689#define MVFR0_SIMD_SHIFT		0
690
691#define MVFR1_SIMDFMAC_SHIFT		28
692#define MVFR1_FPHP_SHIFT		24
693#define MVFR1_SIMDHP_SHIFT		20
694#define MVFR1_SIMDSP_SHIFT		16
695#define MVFR1_SIMDINT_SHIFT		12
696#define MVFR1_SIMDLS_SHIFT		8
697#define MVFR1_FPDNAN_SHIFT		4
698#define MVFR1_FPFTZ_SHIFT		0
699
700
701#define ID_AA64MMFR0_TGRAN4_SHIFT	28
702#define ID_AA64MMFR0_TGRAN64_SHIFT	24
703#define ID_AA64MMFR0_TGRAN16_SHIFT	20
704
705#define ID_AA64MMFR0_TGRAN4_NI		0xf
706#define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0
707#define ID_AA64MMFR0_TGRAN64_NI		0xf
708#define ID_AA64MMFR0_TGRAN64_SUPPORTED	0x0
709#define ID_AA64MMFR0_TGRAN16_NI		0x0
710#define ID_AA64MMFR0_TGRAN16_SUPPORTED	0x1
711
712#if defined(CONFIG_ARM64_4K_PAGES)
713#define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN4_SHIFT
714#define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN4_SUPPORTED
715#elif defined(CONFIG_ARM64_16K_PAGES)
716#define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN16_SHIFT
717#define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN16_SUPPORTED
718#elif defined(CONFIG_ARM64_64K_PAGES)
719#define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN64_SHIFT
720#define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN64_SUPPORTED
721#endif
722
723
724/*
725 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which
726 * are reserved by the SVE architecture for future expansion of the LEN
727 * field, with compatible semantics.
728 */
729#define ZCR_ELx_LEN_SHIFT	0
730#define ZCR_ELx_LEN_SIZE	9
731#define ZCR_ELx_LEN_MASK	0x1ff
732
733#define CPACR_EL1_ZEN_EL1EN	(BIT(16)) /* enable EL1 access */
734#define CPACR_EL1_ZEN_EL0EN	(BIT(17)) /* enable EL0 access, if EL1EN set */
735#define CPACR_EL1_ZEN		(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
736
737
738/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
739#define SYS_MPIDR_SAFE_VAL	(BIT(31))
740
741#ifdef __ASSEMBLY__
742
743	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
744	.equ	.L__reg_num_x\num, \num
745	.endr
746	.equ	.L__reg_num_xzr, 31
747
748	.macro	mrs_s, rt, sreg
749	 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
750	.endm
751
752	.macro	msr_s, sreg, rt
753	__emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
754	.endm
755
756#else
757
758#include <linux/build_bug.h>
759#include <linux/types.h>
760
761#define __DEFINE_MRS_MSR_S_REGNUM				\
762"	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
763"	.equ	.L__reg_num_x\\num, \\num\n"			\
764"	.endr\n"						\
765"	.equ	.L__reg_num_xzr, 31\n"
766
767#define DEFINE_MRS_S						\
768	__DEFINE_MRS_MSR_S_REGNUM				\
769"	.macro	mrs_s, rt, sreg\n"				\
770	__emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt))	\
771"	.endm\n"
772
773#define DEFINE_MSR_S						\
774	__DEFINE_MRS_MSR_S_REGNUM				\
775"	.macro	msr_s, sreg, rt\n"				\
776	__emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt))	\
777"	.endm\n"
778
779#define UNDEFINE_MRS_S						\
780"	.purgem	mrs_s\n"
781
782#define UNDEFINE_MSR_S						\
783"	.purgem	msr_s\n"
784
785#define __mrs_s(v, r)						\
786	DEFINE_MRS_S						\
787"	mrs_s " v ", " __stringify(r) "\n"			\
788	UNDEFINE_MRS_S
789
790#define __msr_s(r, v)						\
791	DEFINE_MSR_S						\
792"	msr_s " __stringify(r) ", " v "\n"			\
793	UNDEFINE_MSR_S
794
795/*
796 * Unlike read_cpuid, calls to read_sysreg are never expected to be
797 * optimized away or replaced with synthetic values.
798 */
799#define read_sysreg(r) ({					\
800	u64 __val;						\
801	asm volatile("mrs %0, " __stringify(r) : "=r" (__val));	\
802	__val;							\
803})
804
805/*
806 * The "Z" constraint normally means a zero immediate, but when combined with
807 * the "%x0" template means XZR.
808 */
809#define write_sysreg(v, r) do {					\
810	u64 __val = (u64)(v);					\
811	asm volatile("msr " __stringify(r) ", %x0"		\
812		     : : "rZ" (__val));				\
813} while (0)
814
815/*
816 * For registers without architectural names, or simply unsupported by
817 * GAS.
818 */
819#define read_sysreg_s(r) ({						\
820	u64 __val;							\
821	asm volatile(__mrs_s("%0", r) : "=r" (__val));			\
822	__val;								\
823})
824
825#define write_sysreg_s(v, r) do {					\
826	u64 __val = (u64)(v);						\
827	asm volatile(__msr_s(r, "%x0") : : "rZ" (__val));		\
828} while (0)
829
830/*
831 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
832 * set mask are set. Other bits are left as-is.
833 */
834#define sysreg_clear_set(sysreg, clear, set) do {			\
835	u64 __scs_val = read_sysreg(sysreg);				\
836	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
837	if (__scs_new != __scs_val)					\
838		write_sysreg(__scs_new, sysreg);			\
839} while (0)
840
841#endif
842
843#endif	/* __ASM_SYSREG_H */
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