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1Device Tree Clock bindings for Altera's SoCFPGA platform
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
13 can get gated.
14
15- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16- clocks : shall be the input parent clock phandle for the clock. This is
17 either an oscillator or a pll output.
18- #clock-cells : from common clock binding, shall be set to 0.
19
20Optional properties:
21- fixed-divider : If clocks have a fixed divider value, use this property.
22- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
23 and the bit index.
24- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
25 the divider register, bit shift, and width.
26- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
27 the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
28 value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
29 hold/delay times that is needed for the SD/MMC CIU clock. The values of both
30 can be 0-315 degrees, in 45 degree increments.